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18#include "qemu/osdep.h"
19#include "disas/dis-asm.h"
20
21#define DEFINE_TABLE
22
23typedef enum
24 {
25 HEX_0,
26 HEX_1,
27 HEX_2,
28 HEX_3,
29 HEX_4,
30 HEX_5,
31 HEX_6,
32 HEX_7,
33 HEX_8,
34 HEX_9,
35 HEX_A,
36 HEX_B,
37 HEX_C,
38 HEX_D,
39 HEX_E,
40 HEX_F,
41 HEX_XX00,
42 HEX_00YY,
43 REG_N,
44 REG_N_D,
45 REG_N_B01,
46 REG_M,
47 SDT_REG_N,
48 REG_NM,
49 REG_B,
50 BRANCH_12,
51 BRANCH_8,
52 IMM0_4,
53 IMM0_4BY2,
54 IMM0_4BY4,
55 IMM1_4,
56 IMM1_4BY2,
57 IMM1_4BY4,
58 PCRELIMM_8BY2,
59 PCRELIMM_8BY4,
60 IMM0_8,
61 IMM0_8BY2,
62 IMM0_8BY4,
63 IMM1_8,
64 IMM1_8BY2,
65 IMM1_8BY4,
66 PPI,
67 NOPX,
68 NOPY,
69 MOVX,
70 MOVY,
71 MOVX_NOPY,
72 MOVY_NOPX,
73 PSH,
74 PMUL,
75 PPI3,
76 PPI3NC,
77 PDC,
78 PPIC,
79 REPEAT,
80 IMM0_3c,
81 IMM0_3s,
82 IMM0_3Uc,
83 IMM0_3Us,
84 IMM0_20_4,
85 IMM0_20,
86 IMM0_20BY8,
87 DISP0_12,
88 DISP0_12BY2,
89 DISP0_12BY4,
90 DISP0_12BY8,
91 DISP1_12,
92 DISP1_12BY2,
93 DISP1_12BY4,
94 DISP1_12BY8
95 }
96sh_nibble_type;
97
98typedef enum
99 {
100 A_END,
101 A_BDISP12,
102 A_BDISP8,
103 A_DEC_M,
104 A_DEC_N,
105 A_DISP_GBR,
106 A_PC,
107 A_DISP_PC,
108 A_DISP_PC_ABS,
109 A_DISP_REG_M,
110 A_DISP_REG_N,
111 A_GBR,
112 A_IMM,
113 A_INC_M,
114 A_INC_N,
115 A_IND_M,
116 A_IND_N,
117 A_IND_R0_REG_M,
118 A_IND_R0_REG_N,
119 A_MACH,
120 A_MACL,
121 A_PR,
122 A_R0,
123 A_R0_GBR,
124 A_REG_M,
125 A_REG_N,
126 A_REG_B,
127 A_SR,
128 A_VBR,
129 A_TBR,
130 A_DISP_TBR,
131 A_DISP2_TBR,
132 A_DEC_R15,
133 A_INC_R15,
134 A_MOD,
135 A_RE,
136 A_RS,
137 A_DSR,
138 DSP_REG_M,
139 DSP_REG_N,
140 DSP_REG_X,
141 DSP_REG_Y,
142 DSP_REG_E,
143 DSP_REG_F,
144 DSP_REG_G,
145 DSP_REG_A_M,
146 DSP_REG_AX,
147 DSP_REG_XY,
148 DSP_REG_AY,
149 DSP_REG_YX,
150 AX_INC_N,
151 AY_INC_N,
152 AXY_INC_N,
153 AYX_INC_N,
154 AX_IND_N,
155 AY_IND_N,
156 AXY_IND_N,
157 AYX_IND_N,
158 AX_PMOD_N,
159 AXY_PMOD_N,
160 AY_PMOD_N,
161 AYX_PMOD_N,
162 AS_DEC_N,
163 AS_INC_N,
164 AS_IND_N,
165 AS_PMOD_N,
166 A_A0,
167 A_X0,
168 A_X1,
169 A_Y0,
170 A_Y1,
171 A_SSR,
172 A_SPC,
173 A_SGR,
174 A_DBR,
175 F_REG_N,
176 F_REG_M,
177 D_REG_N,
178 D_REG_M,
179 X_REG_N,
180 X_REG_M,
181 DX_REG_N,
182 DX_REG_M,
183 V_REG_N,
184 V_REG_M,
185 XMTRX_M4,
186 F_FR0,
187 FPUL_N,
188 FPUL_M,
189 FPSCR_N,
190 FPSCR_M
191 }
192sh_arg_type;
193
194typedef enum
195 {
196 A_A1_NUM = 5,
197 A_A0_NUM = 7,
198 A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,
199 A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM
200 }
201sh_dsp_reg_nums;
202
203#define arch_sh1_base 0x0001
204#define arch_sh2_base 0x0002
205#define arch_sh3_base 0x0004
206#define arch_sh4_base 0x0008
207#define arch_sh4a_base 0x0010
208#define arch_sh2a_base 0x0020
209
210
211
212#define arch_op32 0x00100000
213
214#define arch_sh_no_mmu 0x04000000
215#define arch_sh_has_mmu 0x08000000
216#define arch_sh_no_co 0x10000000
217#define arch_sh_sp_fpu 0x20000000
218#define arch_sh_dp_fpu 0x40000000
219#define arch_sh_has_dsp 0x80000000
220
221
222#define arch_sh_base_mask 0x0000003f
223#define arch_opann_mask 0x00100000
224#define arch_sh_mmu_mask 0x0c000000
225#define arch_sh_co_mask 0xf0000000
226
227
228#define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)
229#define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)
230#define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
231#define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
232#define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
233#define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)
234#define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)
235#define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)
236#define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)
237#define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)
238#define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)
239#define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
240#define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
241#define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)
242#define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
243#define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)
244
245#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
246#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
247#define SH_VALID_MMU_ARCH_SET(SET) (((SET) & arch_sh_mmu_mask) != 0)
248#define SH_VALID_CO_ARCH_SET(SET) (((SET) & arch_sh_co_mask) != 0)
249#define SH_VALID_ARCH_SET(SET) \
250 (SH_VALID_BASE_ARCH_SET (SET) \
251 && SH_VALID_MMU_ARCH_SET (SET) \
252 && SH_VALID_CO_ARCH_SET (SET))
253#define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \
254 SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2))
255
256#define SH_ARCH_SET_HAS_FPU(SET) \
257 (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0)
258#define SH_ARCH_SET_HAS_DSP(SET) \
259 (((SET) & arch_sh_has_dsp) != 0)
260
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264
265#define SH_ARCH_UNKNOWN_ARCH 0xffffffff
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295#define arch_sh1_up (arch_sh1 | arch_sh2_up)
296#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up)
297#define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up)
298#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up)
299#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
300#define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
301#define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
302
303
304#define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up)
305#define arch_sh3e_up (arch_sh3e | arch_sh4_up)
306#define arch_sh4_up (arch_sh4 | arch_sh4a_up)
307#define arch_sh4a_up (arch_sh4a)
308
309
310#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
311#define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
312#define arch_sh4al_dsp_up (arch_sh4al_dsp)
313
314
315#define arch_sh2a_up (arch_sh2a)
316#define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up)
317
318
319typedef struct
320{
321 const char *name;
322 sh_arg_type arg[4];
323 sh_nibble_type nibbles[9];
324 unsigned int arch;
325} sh_opcode_info;
326
327#ifdef DEFINE_TABLE
328
329static const sh_opcode_info sh_table[] =
330 {
331{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up},
332
333{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up},
334
335{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up},
336
337{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up},
338
339{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up},
340
341{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up},
342
343{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up},
344
345{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up},
346
347{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up},
348
349{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up},
350
351{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up},
352
353{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
354
355{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
356
357{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
358
359{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
360
361{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},
362
363{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up},
364
365{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up},
366
367{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up},
368
369{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up},
370
371{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up},
372
373{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up},
374
375{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up},
376
377{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up},
378
379{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up},
380
381{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up},
382
383{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up},
384
385{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up},
386
387{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up},
388
389{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up},
390
391{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up},
392
393{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up},
394
395{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up},
396
397{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up},
398
399{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up},
400
401{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up},
402
403{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up},
404
405{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up},
406
407{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up},
408
409{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up},
410
411{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
412
413{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
414
415{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up},
416
417{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},
418
419{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up},
420
421{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up},
422
423{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up},
424
425{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up},
426
427{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
428
429{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up},
430
431{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up},
432
433{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up},
434
435{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up},
436
437{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},
438
439{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},
440
441{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},
442
443{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up},
444
445{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up},
446
447{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up},
448
449{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},
450
451{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up},
452
453{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},
454{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},
455
456{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
457
458{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
459
460{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up},
461
462{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up},
463
464{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up},
465
466{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
467
468{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
469
470{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
471
472{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
473
474{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
475
476{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
477
478{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},
479
480{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},
481
482{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up},
483
484{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up},
485
486{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up},
487
488{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up},
489
490{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up},
491
492{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up},
493
494{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up},
495
496{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up},
497
498{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
499
500{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},
501
502{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
503
504{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
505
506{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
507
508{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up},
509
510{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up},
511
512{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up},
513
514{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up},
515
516{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up},
517
518{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up},
519
520{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up},
521
522{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up},
523
524{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up},
525
526{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up},
527
528{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up},
529
530{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up},
531
532{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up},
533{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up},
534
535{"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
536
537{"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
538{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up},
539
540{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up},
541
542{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up},
543
544{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up},
545
546{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up},
547
548{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up},
549
550{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up},
551
552{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up},
553
554{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up},
555
556{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up},
557
558{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up},
559
560{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up},
561{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up},
562
563{"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32},
564
565{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32},
566{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up},
567
568{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up},
569
570{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up},
571
572{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up},
573
574{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up},
575
576{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up},
577
578{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up},
579
580{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up},
581
582{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up},
583
584{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up},
585
586{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
587
588{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up},
589{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up},
590
591{"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32},
592
593{"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
594{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
595{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up},
596
597{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
598{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
599
600{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up},
601
602{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up},
603{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up},
604
605{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
606{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
607
608{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up},
609
610{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
611{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
612
613{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up},
614
615{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up},
616
617{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
618
619{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
620{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up},
621
622{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up},
623
624{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
625
626
627{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
628
629{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up},
630
631{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
632
633{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up},
634
635{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
636
637{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up},
638
639{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up},
640
641{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up},
642
643{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up},
644
645{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up},
646
647{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up},
648
649{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up},
650{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up},
651
652{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up},
653{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up},
654
655{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
656
657{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up},
658
659{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
660
661{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
662
663{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
664
665{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
666
667{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up},
668
669{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up},
670
671{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up},
672
673{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up},
674
675{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up},
676
677{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up},
678
679{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up},
680
681{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up},
682
683{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up},
684
685{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up},
686
687{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up},
688
689{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up},
690
691{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up},
692
693{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up},
694
695{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up},
696
697{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
698
699{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
700
701{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up},
702
703{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up},
704
705{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
706
707{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
708
709{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up},
710
711 {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
712
713{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up},
714
715{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up},
716
717{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up},
718
719{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up},
720
721{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up},
722
723{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up},
724
725{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up},
726
727{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
728
729{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up},
730
731{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up},
732
733{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up},
734
735{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up},
736
737{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up},
738
739{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up},
740
741{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
742
743{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
744
745{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
746
747{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
748
749{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
750
751{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
752
753{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up},
754
755{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up},
756
757{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up},
758
759{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up},
760
761{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up},
762
763{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
764
765{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
766
767{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up},
768
769{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up},
770
771{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up},
772
773{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
774
775{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up},
776
777{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up},
778
779{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up},
780
781{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up},
782
783{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up},
784
785{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up},
786
787{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up},
788
789{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up},
790
791{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
792
793{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
794
795{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up},
796
797{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up},
798
799{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up},
800
801{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up},
802
803{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up},
804
805{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up},
806
807{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up},
808
809{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up},
810
811{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up},
812
813{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up},
814
815{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up},
816
817{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up},
818
819{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up},
820
821{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up},
822
823 {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up},
824
825 {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up},
826
827 {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
828
829 {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
830
831 {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
832
833 {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up},
834
835 {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
836
837 {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
838
839 {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
840
841 {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up},
842
843 {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up},
844
845 {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
846
847 {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
848
849 {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up},
850
851 {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
852
853 {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
854
855 {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up},
856 {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up},
857 {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
858 {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
859 {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
860 {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
861 {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
862 {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
863
864 {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up},
865{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up},
866{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up},
867 {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up},
868{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up},
869{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up},
870
871 {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up},
872{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up},
873{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up},
874 {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up},
875{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up},
876{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up},
877
878 {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
879 {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
880 {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
881 {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
882 {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
883 {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
884
885 {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up},
886{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up},
887{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up},
888 {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up},
889{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up},
890{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up},
891
892 {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up},
893{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up},
894{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up},
895 {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up},
896{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up},
897{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up},
898
899 {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up},
900
901{"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up},
902
903{"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up},
904
905{"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up},
906
907{"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up},
908
909{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
910
911{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up},
912
913{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up},
914
915{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up},
916
917{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up},
918
919{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up},
920
921{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up},
922
923{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up},
924
925{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up},
926
927{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
928{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
929
930
931{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up},
932 {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
933
934{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up},
935 {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
936
937{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
938
939{"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up},
940
941{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up},
942
943{"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up},
944
945{"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up},
946
947{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up},
948
949{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
950
951{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
952
953{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up},
954
955{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up},
956
957{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
958
959{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up},
960
961{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up},
962
963{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
964
965{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up},
966
967{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
968
969{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up},
970
971{"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up},
972
973{"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up},
974
975{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
976
977{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
978
979{"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up},
980
981{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
982
983{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
984{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up},
985
986{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
987{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up},
988
989{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
990{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up},
991
992{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
993{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up},
994
995{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up},
996
997{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up},
998
999{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
1000{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up},
1001
1002{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
1003
1004{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up},
1005
1006{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up},
1007
1008{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
1009
1010{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
1011{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up},
1012
1013{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
1014
1015{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
1016{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up},
1017
1018{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
1019{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
1020
1021{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
1022{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
1023
1024{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
1025{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
1026
1027{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
1028{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
1029
1030{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
1031{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
1032
1033{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
1034{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
1035
1036{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
1037
1038{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
1039
1040{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
1041
1042{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
1043
1044{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
1045
1046{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
1047
1048{"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
1049
1050{"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
1051
1052{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
1053
1054{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
1055
1056{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
1057
1058{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
1059
1060{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
1061
1062{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
1063
1064{"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
1065
1066{"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
1067
1068{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
1069{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up},
1070
1071{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
1072{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up},
1073
1074{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
1075
1076{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
1077
1078{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up},
1079
1080{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up},
1081
1082{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up},
1083{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up},
1084
1085{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up},
1086
1087{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
1088
1089{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
1090{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up},
1091
1092{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
1093{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up},
1094
1095{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up},
1096
1097 {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
1098
1099{"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1100 {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
1101
1102{"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1103 {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
1104
1105{"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1106 {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
1107
1108{"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1109 {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up},
1110 {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up},
1111 {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up},
1112 {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up},
1113 {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up},
1114 {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up},
1115 {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up},
1116 {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up},
1117 {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up},
1118 {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up},
1119 {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up},
1120 {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up},
1121 {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up},
1122 {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up},
1123 {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up},
1124 {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up},
1125 {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up},
1126 {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up},
1127 {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up},
1128 {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up},
1129
1130
1131{"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1132
1133{"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1134
1135{"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1136
1137{"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1138
1139{"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1140
1141{"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1142
1143{"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32},
1144
1145{"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32},
1146
1147{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
1148
1149{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
1150
1151{ 0, {0}, {0}, 0 }
1152};
1153
1154#endif
1155
1156#ifdef ARCH_all
1157#define INCLUDE_SHMEDIA
1158#endif
1159
1160static void
1161print_movxy (const sh_opcode_info *op, int rn, int rm,
1162 fprintf_function fprintf_fn, void *stream)
1163{
1164 int n;
1165
1166 fprintf_fn (stream, "%s\t", op->name);
1167 for (n = 0; n < 2; n++)
1168 {
1169 switch (op->arg[n])
1170 {
1171 case A_IND_N:
1172 case AX_IND_N:
1173 case AXY_IND_N:
1174 case AY_IND_N:
1175 case AYX_IND_N:
1176 fprintf_fn (stream, "@r%d", rn);
1177 break;
1178 case A_INC_N:
1179 case AX_INC_N:
1180 case AXY_INC_N:
1181 case AY_INC_N:
1182 case AYX_INC_N:
1183 fprintf_fn (stream, "@r%d+", rn);
1184 break;
1185 case AX_PMOD_N:
1186 case AXY_PMOD_N:
1187 fprintf_fn (stream, "@r%d+r8", rn);
1188 break;
1189 case AY_PMOD_N:
1190 case AYX_PMOD_N:
1191 fprintf_fn (stream, "@r%d+r9", rn);
1192 break;
1193 case DSP_REG_A_M:
1194 fprintf_fn (stream, "a%c", '0' + rm);
1195 break;
1196 case DSP_REG_X:
1197 fprintf_fn (stream, "x%c", '0' + rm);
1198 break;
1199 case DSP_REG_Y:
1200 fprintf_fn (stream, "y%c", '0' + rm);
1201 break;
1202 case DSP_REG_AX:
1203 fprintf_fn (stream, "%c%c",
1204 (rm & 1) ? 'x' : 'a',
1205 (rm & 2) ? '1' : '0');
1206 break;
1207 case DSP_REG_XY:
1208 fprintf_fn (stream, "%c%c",
1209 (rm & 1) ? 'y' : 'x',
1210 (rm & 2) ? '1' : '0');
1211 break;
1212 case DSP_REG_AY:
1213 fprintf_fn (stream, "%c%c",
1214 (rm & 2) ? 'y' : 'a',
1215 (rm & 1) ? '1' : '0');
1216 break;
1217 case DSP_REG_YX:
1218 fprintf_fn (stream, "%c%c",
1219 (rm & 2) ? 'x' : 'y',
1220 (rm & 1) ? '1' : '0');
1221 break;
1222 default:
1223 abort ();
1224 }
1225 if (n == 0)
1226 fprintf_fn (stream, ",");
1227 }
1228}
1229
1230
1231
1232
1233
1234
1235static void
1236print_insn_ddt (int insn, struct disassemble_info *info)
1237{
1238 fprintf_function fprintf_fn = info->fprintf_func;
1239 void *stream = info->stream;
1240
1241
1242 if (insn == 0x000)
1243 fprintf_fn (stream, "nopx\tnopy");
1244
1245
1246
1247 if ((insn & 0x800) && (insn & 0x3ff))
1248 fprintf_fn (stream, "\t");
1249
1250
1251 if (((insn & 0xc) == 0 && (insn & 0x2a0))
1252 || ((insn & 3) == 0 && (insn & 0x150)))
1253 if (info->mach != bfd_mach_sh_dsp
1254 && info->mach != bfd_mach_sh3_dsp)
1255 {
1256 static const sh_opcode_info *first_movx, *first_movy;
1257 const sh_opcode_info *op;
1258 int is_movy;
1259
1260 if (! first_movx)
1261 {
1262 for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;)
1263 first_movx++;
1264 for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;)
1265 first_movy++;
1266 }
1267
1268 is_movy = ((insn & 3) != 0);
1269
1270 if (is_movy)
1271 op = first_movy;
1272 else
1273 op = first_movx;
1274
1275 while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
1276 || op->nibbles[3] != (unsigned) (insn & 0xf))
1277 op++;
1278
1279 print_movxy (op,
1280 (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
1281 + 2 * is_movy
1282 + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)),
1283 (insn >> 6) & 3,
1284 fprintf_fn, stream);
1285 }
1286 else
1287 fprintf_fn (stream, ".word 0x%x", insn);
1288 else
1289 {
1290 static const sh_opcode_info *first_movx, *first_movy;
1291 const sh_opcode_info *opx, *opy;
1292 unsigned int insn_x, insn_y;
1293
1294 if (! first_movx)
1295 {
1296 for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
1297 first_movx++;
1298 for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
1299 first_movy++;
1300 }
1301 insn_x = (insn >> 2) & 0xb;
1302 if (insn_x)
1303 {
1304 for (opx = first_movx; opx->nibbles[2] != insn_x;)
1305 opx++;
1306 print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
1307 fprintf_fn, stream);
1308 }
1309 insn_y = (insn & 3) | ((insn >> 1) & 8);
1310 if (insn_y)
1311 {
1312 if (insn_x)
1313 fprintf_fn (stream, "\t");
1314 for (opy = first_movy; opy->nibbles[2] != insn_y;)
1315 opy++;
1316 print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
1317 fprintf_fn, stream);
1318 }
1319 }
1320}
1321
1322static void
1323print_dsp_reg (int rm, fprintf_function fprintf_fn, void *stream)
1324{
1325 switch (rm)
1326 {
1327 case A_A1_NUM:
1328 fprintf_fn (stream, "a1");
1329 break;
1330 case A_A0_NUM:
1331 fprintf_fn (stream, "a0");
1332 break;
1333 case A_X0_NUM:
1334 fprintf_fn (stream, "x0");
1335 break;
1336 case A_X1_NUM:
1337 fprintf_fn (stream, "x1");
1338 break;
1339 case A_Y0_NUM:
1340 fprintf_fn (stream, "y0");
1341 break;
1342 case A_Y1_NUM:
1343 fprintf_fn (stream, "y1");
1344 break;
1345 case A_M0_NUM:
1346 fprintf_fn (stream, "m0");
1347 break;
1348 case A_A1G_NUM:
1349 fprintf_fn (stream, "a1g");
1350 break;
1351 case A_M1_NUM:
1352 fprintf_fn (stream, "m1");
1353 break;
1354 case A_A0G_NUM:
1355 fprintf_fn (stream, "a0g");
1356 break;
1357 default:
1358 fprintf_fn (stream, "0x%x", rm);
1359 break;
1360 }
1361}
1362
1363static void
1364print_insn_ppi (int field_b, struct disassemble_info *info)
1365{
1366 static const char *sx_tab[] = { "x0", "x1", "a0", "a1" };
1367 static const char *sy_tab[] = { "y0", "y1", "m0", "m1" };
1368 fprintf_function fprintf_fn = info->fprintf_func;
1369 void *stream = info->stream;
1370 unsigned int nib1, nib2, nib3;
1371 unsigned int altnib1, nib4;
1372 const char *dc = NULL;
1373 const sh_opcode_info *op;
1374
1375 if ((field_b & 0xe800) == 0)
1376 {
1377 fprintf_fn (stream, "psh%c\t#%d,",
1378 field_b & 0x1000 ? 'a' : 'l',
1379 (field_b >> 4) & 127);
1380 print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
1381 return;
1382 }
1383 if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
1384 {
1385 static const char *du_tab[] = { "x0", "y0", "a0", "a1" };
1386 static const char *se_tab[] = { "x0", "x1", "y0", "a1" };
1387 static const char *sf_tab[] = { "y0", "y1", "x0", "a1" };
1388 static const char *sg_tab[] = { "m0", "m1", "a0", "a1" };
1389
1390 if (field_b & 0x2000)
1391 {
1392 fprintf_fn (stream, "p%s %s,%s,%s\t",
1393 (field_b & 0x1000) ? "add" : "sub",
1394 sx_tab[(field_b >> 6) & 3],
1395 sy_tab[(field_b >> 4) & 3],
1396 du_tab[(field_b >> 0) & 3]);
1397 }
1398 else if ((field_b & 0xf0) == 0x10
1399 && info->mach != bfd_mach_sh_dsp
1400 && info->mach != bfd_mach_sh3_dsp)
1401 {
1402 fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
1403 }
1404 else if ((field_b & 0xf3) != 0)
1405 {
1406 fprintf_fn (stream, ".word 0x%x\t", field_b);
1407 }
1408 fprintf_fn (stream, "pmuls%c%s,%s,%s",
1409 field_b & 0x2000 ? ' ' : '\t',
1410 se_tab[(field_b >> 10) & 3],
1411 sf_tab[(field_b >> 8) & 3],
1412 sg_tab[(field_b >> 2) & 3]);
1413 return;
1414 }
1415
1416 nib1 = PPIC;
1417 nib2 = field_b >> 12 & 0xf;
1418 nib3 = field_b >> 8 & 0xf;
1419 nib4 = field_b >> 4 & 0xf;
1420 switch (nib3 & 0x3)
1421 {
1422 case 0:
1423 dc = "";
1424 nib1 = PPI3;
1425 break;
1426 case 1:
1427 dc = "";
1428 break;
1429 case 2:
1430 dc = "dct ";
1431 nib3 -= 1;
1432 break;
1433 case 3:
1434 dc = "dcf ";
1435 nib3 -= 2;
1436 break;
1437 }
1438 if (nib1 == PPI3)
1439 altnib1 = PPI3NC;
1440 else
1441 altnib1 = nib1;
1442 for (op = sh_table; op->name; op++)
1443 {
1444 if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1)
1445 && op->nibbles[2] == nib2
1446 && op->nibbles[3] == nib3)
1447 {
1448 int n;
1449
1450 switch (op->nibbles[4])
1451 {
1452 case HEX_0:
1453 break;
1454 case HEX_XX00:
1455 if ((nib4 & 3) != 0)
1456 continue;
1457 break;
1458 case HEX_1:
1459 if ((nib4 & 3) != 1)
1460 continue;
1461 break;
1462 case HEX_00YY:
1463 if ((nib4 & 0xc) != 0)
1464 continue;
1465 break;
1466 case HEX_4:
1467 if ((nib4 & 0xc) != 4)
1468 continue;
1469 break;
1470 default:
1471 abort ();
1472 }
1473 fprintf_fn (stream, "%s%s\t", dc, op->name);
1474 for (n = 0; n < 3 && op->arg[n] != A_END; n++)
1475 {
1476 if (n && op->arg[1] != A_END)
1477 fprintf_fn (stream, ",");
1478 switch (op->arg[n])
1479 {
1480 case DSP_REG_N:
1481 print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
1482 break;
1483 case DSP_REG_X:
1484 fprintf_fn (stream, "%s", sx_tab[(field_b >> 6) & 3]);
1485 break;
1486 case DSP_REG_Y:
1487 fprintf_fn (stream, "%s", sy_tab[(field_b >> 4) & 3]);
1488 break;
1489 case A_MACH:
1490 fprintf_fn (stream, "mach");
1491 break;
1492 case A_MACL:
1493 fprintf_fn (stream, "macl");
1494 break;
1495 default:
1496 abort ();
1497 }
1498 }
1499 return;
1500 }
1501 }
1502
1503 fprintf_fn (stream, ".word 0x%x", field_b);
1504}
1505
1506
1507
1508int
1509print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
1510{
1511 fprintf_function fprintf_fn = info->fprintf_func;
1512 void *stream = info->stream;
1513 unsigned char insn[4];
1514 unsigned char nibs[8];
1515 int status;
1516 bfd_vma relmask = ~(bfd_vma) 0;
1517 const sh_opcode_info *op;
1518 unsigned int target_arch;
1519 int allow_op32;
1520
1521 switch (info->mach)
1522 {
1523 case bfd_mach_sh:
1524 target_arch = arch_sh1;
1525 break;
1526 case bfd_mach_sh4:
1527 target_arch = arch_sh4;
1528 break;
1529 case bfd_mach_sh5:
1530#ifdef INCLUDE_SHMEDIA
1531 status = print_insn_sh64 (memaddr, info);
1532 if (status != -2)
1533 return status;
1534#endif
1535
1536
1537 target_arch = arch_sh4;
1538 break;
1539 default:
1540 fprintf (stderr, "sh architecture not supported\n");
1541 return -1;
1542 }
1543
1544 status = info->read_memory_func (memaddr, insn, 2, info);
1545
1546 if (status != 0)
1547 {
1548 info->memory_error_func (status, memaddr, info);
1549 return -1;
1550 }
1551
1552 if (info->endian == BFD_ENDIAN_LITTLE)
1553 {
1554 nibs[0] = (insn[1] >> 4) & 0xf;
1555 nibs[1] = insn[1] & 0xf;
1556
1557 nibs[2] = (insn[0] >> 4) & 0xf;
1558 nibs[3] = insn[0] & 0xf;
1559 }
1560 else
1561 {
1562 nibs[0] = (insn[0] >> 4) & 0xf;
1563 nibs[1] = insn[0] & 0xf;
1564
1565 nibs[2] = (insn[1] >> 4) & 0xf;
1566 nibs[3] = insn[1] & 0xf;
1567 }
1568 status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
1569 if (status != 0)
1570 allow_op32 = 0;
1571 else
1572 {
1573 allow_op32 = 1;
1574
1575 if (info->endian == BFD_ENDIAN_LITTLE)
1576 {
1577 nibs[4] = (insn[3] >> 4) & 0xf;
1578 nibs[5] = insn[3] & 0xf;
1579
1580 nibs[6] = (insn[2] >> 4) & 0xf;
1581 nibs[7] = insn[2] & 0xf;
1582 }
1583 else
1584 {
1585 nibs[4] = (insn[2] >> 4) & 0xf;
1586 nibs[5] = insn[2] & 0xf;
1587
1588 nibs[6] = (insn[3] >> 4) & 0xf;
1589 nibs[7] = insn[3] & 0xf;
1590 }
1591 }
1592
1593 if (nibs[0] == 0xf && (nibs[1] & 4) == 0
1594 && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
1595 {
1596 if (nibs[1] & 8)
1597 {
1598 int field_b;
1599
1600 status = info->read_memory_func (memaddr + 2, insn, 2, info);
1601
1602 if (status != 0)
1603 {
1604 info->memory_error_func (status, memaddr + 2, info);
1605 return -1;
1606 }
1607
1608 if (info->endian == BFD_ENDIAN_LITTLE)
1609 field_b = insn[1] << 8 | insn[0];
1610 else
1611 field_b = insn[0] << 8 | insn[1];
1612
1613 print_insn_ppi (field_b, info);
1614 print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
1615 return 4;
1616 }
1617 print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
1618 return 2;
1619 }
1620 for (op = sh_table; op->name; op++)
1621 {
1622 int n;
1623 int imm = 0;
1624 int rn = 0;
1625 int rm = 0;
1626 int rb = 0;
1627 int disp_pc;
1628 bfd_vma disp_pc_addr = 0;
1629 int disp = 0;
1630 int has_disp = 0;
1631 int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;
1632
1633 if (!allow_op32
1634 && SH_MERGE_ARCH_SET (op->arch, arch_op32))
1635 goto fail;
1636
1637 if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
1638 goto fail;
1639 for (n = 0; n < max_n; n++)
1640 {
1641 int i = op->nibbles[n];
1642
1643 if (i < 16)
1644 {
1645 if (nibs[n] == i)
1646 continue;
1647 goto fail;
1648 }
1649 switch (i)
1650 {
1651 case BRANCH_8:
1652 imm = (nibs[2] << 4) | (nibs[3]);
1653 if (imm & 0x80)
1654 imm |= ~0xff;
1655 imm = ((char) imm) * 2 + 4;
1656 goto ok;
1657 case BRANCH_12:
1658 imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
1659 if (imm & 0x800)
1660 imm |= ~0xfff;
1661 imm = imm * 2 + 4;
1662 goto ok;
1663 case IMM0_3c:
1664 if (nibs[3] & 0x8)
1665 goto fail;
1666 imm = nibs[3] & 0x7;
1667 break;
1668 case IMM0_3s:
1669 if (!(nibs[3] & 0x8))
1670 goto fail;
1671 imm = nibs[3] & 0x7;
1672 break;
1673 case IMM0_3Uc:
1674 if (nibs[2] & 0x8)
1675 goto fail;
1676 imm = nibs[2] & 0x7;
1677 break;
1678 case IMM0_3Us:
1679 if (!(nibs[2] & 0x8))
1680 goto fail;
1681 imm = nibs[2] & 0x7;
1682 break;
1683 case DISP0_12:
1684 case DISP1_12:
1685 disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
1686 has_disp = 1;
1687 goto ok;
1688 case DISP0_12BY2:
1689 case DISP1_12BY2:
1690 disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
1691 relmask = ~(bfd_vma) 1;
1692 has_disp = 1;
1693 goto ok;
1694 case DISP0_12BY4:
1695 case DISP1_12BY4:
1696 disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
1697 relmask = ~(bfd_vma) 3;
1698 has_disp = 1;
1699 goto ok;
1700 case DISP0_12BY8:
1701 case DISP1_12BY8:
1702 disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
1703 relmask = ~(bfd_vma) 7;
1704 has_disp = 1;
1705 goto ok;
1706 case IMM0_20_4:
1707 break;
1708 case IMM0_20:
1709 imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
1710 | (nibs[6] << 4) | nibs[7]);
1711 if (imm & 0x80000)
1712 imm -= 0x100000;
1713 goto ok;
1714 case IMM0_20BY8:
1715 imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
1716 | (nibs[6] << 4) | nibs[7]);
1717 imm <<= 8;
1718 if (imm & 0x8000000)
1719 imm -= 0x10000000;
1720 goto ok;
1721 case IMM0_4:
1722 case IMM1_4:
1723 imm = nibs[3];
1724 goto ok;
1725 case IMM0_4BY2:
1726 case IMM1_4BY2:
1727 imm = nibs[3] << 1;
1728 goto ok;
1729 case IMM0_4BY4:
1730 case IMM1_4BY4:
1731 imm = nibs[3] << 2;
1732 goto ok;
1733 case IMM0_8:
1734 case IMM1_8:
1735 imm = (nibs[2] << 4) | nibs[3];
1736 disp = imm;
1737 has_disp = 1;
1738 if (imm & 0x80)
1739 imm -= 0x100;
1740 goto ok;
1741 case PCRELIMM_8BY2:
1742 imm = ((nibs[2] << 4) | nibs[3]) << 1;
1743 relmask = ~(bfd_vma) 1;
1744 goto ok;
1745 case PCRELIMM_8BY4:
1746 imm = ((nibs[2] << 4) | nibs[3]) << 2;
1747 relmask = ~(bfd_vma) 3;
1748 goto ok;
1749 case IMM0_8BY2:
1750 case IMM1_8BY2:
1751 imm = ((nibs[2] << 4) | nibs[3]) << 1;
1752 goto ok;
1753 case IMM0_8BY4:
1754 case IMM1_8BY4:
1755 imm = ((nibs[2] << 4) | nibs[3]) << 2;
1756 goto ok;
1757 case REG_N_D:
1758 if ((nibs[n] & 1) != 0)
1759 goto fail;
1760
1761 case REG_N:
1762 rn = nibs[n];
1763 break;
1764 case REG_M:
1765 rm = nibs[n];
1766 break;
1767 case REG_N_B01:
1768 if ((nibs[n] & 0x3) != 1 )
1769 goto fail;
1770 rn = (nibs[n] & 0xc) >> 2;
1771 break;
1772 case REG_NM:
1773 rn = (nibs[n] & 0xc) >> 2;
1774 rm = (nibs[n] & 0x3);
1775 break;
1776 case REG_B:
1777 rb = nibs[n] & 0x07;
1778 break;
1779 case SDT_REG_N:
1780
1781 rn = nibs[n];
1782 if ((rn & 0xc) != 4)
1783 goto fail;
1784 rn = rn & 0x3;
1785 rn |= (!(rn & 2)) << 2;
1786 break;
1787 case PPI:
1788 case REPEAT:
1789 goto fail;
1790 default:
1791 abort ();
1792 }
1793 }
1794
1795 ok:
1796
1797
1798
1799 if (target_arch == arch_sh2a
1800 && ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
1801 || (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
1802 goto fail;
1803
1804 fprintf_fn (stream, "%s\t", op->name);
1805 disp_pc = 0;
1806 for (n = 0; n < 3 && op->arg[n] != A_END; n++)
1807 {
1808 if (n && op->arg[1] != A_END)
1809 fprintf_fn (stream, ",");
1810 switch (op->arg[n])
1811 {
1812 case A_IMM:
1813 fprintf_fn (stream, "#%d", imm);
1814 break;
1815 case A_R0:
1816 fprintf_fn (stream, "r0");
1817 break;
1818 case A_REG_N:
1819 fprintf_fn (stream, "r%d", rn);
1820 break;
1821 case A_INC_N:
1822 case AS_INC_N:
1823 fprintf_fn (stream, "@r%d+", rn);
1824 break;
1825 case A_DEC_N:
1826 case AS_DEC_N:
1827 fprintf_fn (stream, "@-r%d", rn);
1828 break;
1829 case A_IND_N:
1830 case AS_IND_N:
1831 fprintf_fn (stream, "@r%d", rn);
1832 break;
1833 case A_DISP_REG_N:
1834 fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
1835 break;
1836 case AS_PMOD_N:
1837 fprintf_fn (stream, "@r%d+r8", rn);
1838 break;
1839 case A_REG_M:
1840 fprintf_fn (stream, "r%d", rm);
1841 break;
1842 case A_INC_M:
1843 fprintf_fn (stream, "@r%d+", rm);
1844 break;
1845 case A_DEC_M:
1846 fprintf_fn (stream, "@-r%d", rm);
1847 break;
1848 case A_IND_M:
1849 fprintf_fn (stream, "@r%d", rm);
1850 break;
1851 case A_DISP_REG_M:
1852 fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
1853 break;
1854 case A_REG_B:
1855 fprintf_fn (stream, "r%d_bank", rb);
1856 break;
1857 case A_DISP_PC:
1858 disp_pc = 1;
1859 disp_pc_addr = imm + 4 + (memaddr & relmask);
1860 (*info->print_address_func) (disp_pc_addr, info);
1861 break;
1862 case A_IND_R0_REG_N:
1863 fprintf_fn (stream, "@(r0,r%d)", rn);
1864 break;
1865 case A_IND_R0_REG_M:
1866 fprintf_fn (stream, "@(r0,r%d)", rm);
1867 break;
1868 case A_DISP_GBR:
1869 fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
1870 break;
1871 case A_TBR:
1872 fprintf_fn (stream, "tbr");
1873 break;
1874 case A_DISP2_TBR:
1875 fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
1876 break;
1877 case A_INC_R15:
1878 fprintf_fn (stream, "@r15+");
1879 break;
1880 case A_DEC_R15:
1881 fprintf_fn (stream, "@-r15");
1882 break;
1883 case A_R0_GBR:
1884 fprintf_fn (stream, "@(r0,gbr)");
1885 break;
1886 case A_BDISP12:
1887 case A_BDISP8:
1888 {
1889 bfd_vma addr;
1890 addr = imm + memaddr;
1891 (*info->print_address_func) (addr, info);
1892 }
1893 break;
1894 case A_SR:
1895 fprintf_fn (stream, "sr");
1896 break;
1897 case A_GBR:
1898 fprintf_fn (stream, "gbr");
1899 break;
1900 case A_VBR:
1901 fprintf_fn (stream, "vbr");
1902 break;
1903 case A_DSR:
1904 fprintf_fn (stream, "dsr");
1905 break;
1906 case A_MOD:
1907 fprintf_fn (stream, "mod");
1908 break;
1909 case A_RE:
1910 fprintf_fn (stream, "re");
1911 break;
1912 case A_RS:
1913 fprintf_fn (stream, "rs");
1914 break;
1915 case A_A0:
1916 fprintf_fn (stream, "a0");
1917 break;
1918 case A_X0:
1919 fprintf_fn (stream, "x0");
1920 break;
1921 case A_X1:
1922 fprintf_fn (stream, "x1");
1923 break;
1924 case A_Y0:
1925 fprintf_fn (stream, "y0");
1926 break;
1927 case A_Y1:
1928 fprintf_fn (stream, "y1");
1929 break;
1930 case DSP_REG_M:
1931 print_dsp_reg (rm, fprintf_fn, stream);
1932 break;
1933 case A_SSR:
1934 fprintf_fn (stream, "ssr");
1935 break;
1936 case A_SPC:
1937 fprintf_fn (stream, "spc");
1938 break;
1939 case A_MACH:
1940 fprintf_fn (stream, "mach");
1941 break;
1942 case A_MACL:
1943 fprintf_fn (stream, "macl");
1944 break;
1945 case A_PR:
1946 fprintf_fn (stream, "pr");
1947 break;
1948 case A_SGR:
1949 fprintf_fn (stream, "sgr");
1950 break;
1951 case A_DBR:
1952 fprintf_fn (stream, "dbr");
1953 break;
1954 case F_REG_N:
1955 fprintf_fn (stream, "fr%d", rn);
1956 break;
1957 case F_REG_M:
1958 fprintf_fn (stream, "fr%d", rm);
1959 break;
1960 case DX_REG_N:
1961 if (rn & 1)
1962 {
1963 fprintf_fn (stream, "xd%d", rn & ~1);
1964 break;
1965 }
1966
1967 case D_REG_N:
1968 fprintf_fn (stream, "dr%d", rn);
1969 break;
1970 case DX_REG_M:
1971 if (rm & 1)
1972 {
1973 fprintf_fn (stream, "xd%d", rm & ~1);
1974 break;
1975 }
1976
1977 case D_REG_M:
1978 fprintf_fn (stream, "dr%d", rm);
1979 break;
1980 case FPSCR_M:
1981 case FPSCR_N:
1982 fprintf_fn (stream, "fpscr");
1983 break;
1984 case FPUL_M:
1985 case FPUL_N:
1986 fprintf_fn (stream, "fpul");
1987 break;
1988 case F_FR0:
1989 fprintf_fn (stream, "fr0");
1990 break;
1991 case V_REG_N:
1992 fprintf_fn (stream, "fv%d", rn * 4);
1993 break;
1994 case V_REG_M:
1995 fprintf_fn (stream, "fv%d", rm * 4);
1996 break;
1997 case XMTRX_M4:
1998 fprintf_fn (stream, "xmtrx");
1999 break;
2000 default:
2001 abort ();
2002 }
2003 }
2004
2005#if 0
2006
2007
2008
2009
2010
2011 if (!(info->flags & 1)
2012 && (op->name[0] == 'j'
2013 || (op->name[0] == 'b'
2014 && (op->name[1] == 'r'
2015 || op->name[1] == 's'))
2016 || (op->name[0] == 'r' && op->name[1] == 't')
2017 || (op->name[0] == 'b' && op->name[2] == '.')))
2018 {
2019 info->flags |= 1;
2020 fprintf_fn (stream, "\t(slot ");
2021 print_insn_sh (memaddr + 2, info);
2022 info->flags &= ~1;
2023 fprintf_fn (stream, ")");
2024 return 4;
2025 }
2026#endif
2027
2028 if (disp_pc && strcmp (op->name, "mova") != 0)
2029 {
2030 int size;
2031 bfd_byte bytes[4];
2032
2033 if (relmask == ~(bfd_vma) 1)
2034 size = 2;
2035 else
2036 size = 4;
2037 status = info->read_memory_func (disp_pc_addr, bytes, size, info);
2038 if (status == 0)
2039 {
2040 unsigned int val;
2041
2042 if (size == 2)
2043 {
2044 if (info->endian == BFD_ENDIAN_LITTLE)
2045 val = bfd_getl16 (bytes);
2046 else
2047 val = bfd_getb16 (bytes);
2048 }
2049 else
2050 {
2051 if (info->endian == BFD_ENDIAN_LITTLE)
2052 val = bfd_getl32 (bytes);
2053 else
2054 val = bfd_getb32 (bytes);
2055 }
2056 if ((*info->symbol_at_address_func) (val, info))
2057 {
2058 fprintf_fn (stream, "\t! ");
2059 (*info->print_address_func) (val, info);
2060 }
2061 else
2062 fprintf_fn (stream, "\t! 0x%x", val);
2063 }
2064 }
2065
2066 return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
2067 fail:
2068 ;
2069
2070 }
2071 fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
2072 return 2;
2073}
2074
