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11#include "qemu/osdep.h"
12#include "qapi/error.h"
13#include "qemu/module.h"
14#include "qemu/log.h"
15#include "cpu.h"
16#include "hw/arm/pxa.h"
17#include "hw/sysbus.h"
18#include "migration/vmstate.h"
19#include "qom/object.h"
20#include "target/arm/cpregs.h"
21
22#define ICIP 0x00
23#define ICMR 0x04
24#define ICLR 0x08
25#define ICFP 0x0c
26#define ICPR 0x10
27#define ICCR 0x14
28#define ICHP 0x18
29#define IPR0 0x1c
30#define IPR31 0x98
31#define ICIP2 0x9c
32#define ICMR2 0xa0
33#define ICLR2 0xa4
34#define ICFP2 0xa8
35#define ICPR2 0xac
36#define IPR32 0xb0
37#define IPR39 0xcc
38
39#define PXA2XX_PIC_SRCS 40
40
41#define TYPE_PXA2XX_PIC "pxa2xx_pic"
42OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPICState, PXA2XX_PIC)
43
44struct PXA2xxPICState {
45
46 SysBusDevice parent_obj;
47
48
49 MemoryRegion iomem;
50 ARMCPU *cpu;
51 uint32_t int_enabled[2];
52 uint32_t int_pending[2];
53 uint32_t is_fiq[2];
54 uint32_t int_idle;
55 uint32_t priority[PXA2XX_PIC_SRCS];
56};
57
58static void pxa2xx_pic_update(void *opaque)
59{
60 uint32_t mask[2];
61 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
62 CPUState *cpu = CPU(s->cpu);
63
64 if (cpu->halted) {
65 mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
66 mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
67 if (mask[0] || mask[1]) {
68 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
69 }
70 }
71
72 mask[0] = s->int_pending[0] & s->int_enabled[0];
73 mask[1] = s->int_pending[1] & s->int_enabled[1];
74
75 if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
76 cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
77 } else {
78 cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
79 }
80
81 if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
82 cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
83 } else {
84 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
85 }
86}
87
88
89
90static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
91{
92 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
93 int int_set = (irq >= 32);
94 irq &= 31;
95
96 if (level)
97 s->int_pending[int_set] |= 1 << irq;
98 else
99 s->int_pending[int_set] &= ~(1 << irq);
100
101 pxa2xx_pic_update(opaque);
102}
103
104static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
105 int i, int_set, irq;
106 uint32_t bit, mask[2];
107 uint32_t ichp = 0x003f003f;
108
109 mask[0] = s->int_pending[0] & s->int_enabled[0];
110 mask[1] = s->int_pending[1] & s->int_enabled[1];
111
112 for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
113 irq = s->priority[i] & 0x3f;
114 if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
115
116 bit = 1 << (irq & 31);
117 int_set = (irq >= 32);
118
119 if (mask[int_set] & bit & s->is_fiq[int_set]) {
120
121 ichp &= 0xffff0000;
122 ichp |= (1 << 15) | irq;
123 }
124
125 if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
126
127 ichp &= 0x0000ffff;
128 ichp |= (1U << 31) | (irq << 16);
129 }
130 }
131 }
132
133 return ichp;
134}
135
136static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
137 unsigned size)
138{
139 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
140
141 switch (offset) {
142 case ICIP:
143 return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
144 case ICIP2:
145 return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
146 case ICMR:
147 return s->int_enabled[0];
148 case ICMR2:
149 return s->int_enabled[1];
150 case ICLR:
151 return s->is_fiq[0];
152 case ICLR2:
153 return s->is_fiq[1];
154 case ICCR:
155 return (s->int_idle == 0);
156 case ICFP:
157 return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
158 case ICFP2:
159 return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
160 case ICPR:
161 return s->int_pending[0];
162 case ICPR2:
163 return s->int_pending[1];
164 case IPR0 ... IPR31:
165 return s->priority[0 + ((offset - IPR0 ) >> 2)];
166 case IPR32 ... IPR39:
167 return s->priority[32 + ((offset - IPR32) >> 2)];
168 case ICHP:
169 return pxa2xx_pic_highest(s);
170 default:
171 qemu_log_mask(LOG_GUEST_ERROR,
172 "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
173 "\n", offset);
174 return 0;
175 }
176}
177
178static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
179 uint64_t value, unsigned size)
180{
181 PXA2xxPICState *s = (PXA2xxPICState *) opaque;
182
183 switch (offset) {
184 case ICMR:
185 s->int_enabled[0] = value;
186 break;
187 case ICMR2:
188 s->int_enabled[1] = value;
189 break;
190 case ICLR:
191 s->is_fiq[0] = value;
192 break;
193 case ICLR2:
194 s->is_fiq[1] = value;
195 break;
196 case ICCR:
197 s->int_idle = (value & 1) ? 0 : ~0;
198 break;
199 case IPR0 ... IPR31:
200 s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
201 break;
202 case IPR32 ... IPR39:
203 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
204 break;
205 default:
206 qemu_log_mask(LOG_GUEST_ERROR,
207 "pxa2xx_pic_mem_write: bad register offset 0x%"
208 HWADDR_PRIx "\n", offset);
209 return;
210 }
211 pxa2xx_pic_update(opaque);
212}
213
214
215static const int pxa2xx_cp_reg_map[0x10] = {
216 [0x0 ... 0xf] = -1,
217 [0x0] = ICIP,
218 [0x1] = ICMR,
219 [0x2] = ICLR,
220 [0x3] = ICFP,
221 [0x4] = ICPR,
222 [0x5] = ICHP,
223 [0x6] = ICIP2,
224 [0x7] = ICMR2,
225 [0x8] = ICLR2,
226 [0x9] = ICFP2,
227 [0xa] = ICPR2,
228};
229
230static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
231{
232 int offset = pxa2xx_cp_reg_map[ri->crn];
233 return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
234}
235
236static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
237 uint64_t value)
238{
239 int offset = pxa2xx_cp_reg_map[ri->crn];
240 pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
241}
242
243#define REGINFO_FOR_PIC_CP(NAME, CRN) \
244 { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
245 .access = PL1_RW, .type = ARM_CP_IO, \
246 .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
247
248static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
249 REGINFO_FOR_PIC_CP("ICIP", 0),
250 REGINFO_FOR_PIC_CP("ICMR", 1),
251 REGINFO_FOR_PIC_CP("ICLR", 2),
252 REGINFO_FOR_PIC_CP("ICFP", 3),
253 REGINFO_FOR_PIC_CP("ICPR", 4),
254 REGINFO_FOR_PIC_CP("ICHP", 5),
255 REGINFO_FOR_PIC_CP("ICIP2", 6),
256 REGINFO_FOR_PIC_CP("ICMR2", 7),
257 REGINFO_FOR_PIC_CP("ICLR2", 8),
258 REGINFO_FOR_PIC_CP("ICFP2", 9),
259 REGINFO_FOR_PIC_CP("ICPR2", 0xa),
260};
261
262static const MemoryRegionOps pxa2xx_pic_ops = {
263 .read = pxa2xx_pic_mem_read,
264 .write = pxa2xx_pic_mem_write,
265 .endianness = DEVICE_NATIVE_ENDIAN,
266};
267
268static int pxa2xx_pic_post_load(void *opaque, int version_id)
269{
270 pxa2xx_pic_update(opaque);
271 return 0;
272}
273
274DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
275{
276 DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
277 PXA2xxPICState *s = PXA2XX_PIC(dev);
278
279 s->cpu = cpu;
280
281 s->int_pending[0] = 0;
282 s->int_pending[1] = 0;
283 s->int_enabled[0] = 0;
284 s->int_enabled[1] = 0;
285 s->is_fiq[0] = 0;
286 s->is_fiq[1] = 0;
287
288 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
289
290 qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
291
292
293 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
294 "pxa2xx-pic", 0x00100000);
295 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
296 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
297
298
299 define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
300
301 return dev;
302}
303
304static const VMStateDescription vmstate_pxa2xx_pic_regs = {
305 .name = "pxa2xx_pic",
306 .version_id = 0,
307 .minimum_version_id = 0,
308 .post_load = pxa2xx_pic_post_load,
309 .fields = (VMStateField[]) {
310 VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
311 VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
312 VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
313 VMSTATE_UINT32(int_idle, PXA2xxPICState),
314 VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
315 VMSTATE_END_OF_LIST(),
316 },
317};
318
319static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
320{
321 DeviceClass *dc = DEVICE_CLASS(klass);
322
323 dc->desc = "PXA2xx PIC";
324 dc->vmsd = &vmstate_pxa2xx_pic_regs;
325}
326
327static const TypeInfo pxa2xx_pic_info = {
328 .name = TYPE_PXA2XX_PIC,
329 .parent = TYPE_SYS_BUS_DEVICE,
330 .instance_size = sizeof(PXA2xxPICState),
331 .class_init = pxa2xx_pic_class_init,
332};
333
334static void pxa2xx_pic_register_types(void)
335{
336 type_register_static(&pxa2xx_pic_info);
337}
338
339type_init(pxa2xx_pic_register_types)
340
