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8#include "qemu/osdep.h"
9#include "qemu/units.h"
10#include "qemu/bitmap.h"
11#include "qemu/error-report.h"
12#include "qapi/error.h"
13#include "sysemu/qtest.h"
14#include "hw/boards.h"
15
16#include "qapi/qapi-visit-machine.h"
17#include "hw/cxl/cxl.h"
18#include "hw/cxl/cxl_host.h"
19#include "hw/pci/pci_bus.h"
20#include "hw/pci/pci_bridge.h"
21#include "hw/pci/pci_host.h"
22#include "hw/pci/pcie_port.h"
23#include "hw/pci-bridge/pci_expander_bridge.h"
24
25static void cxl_fixed_memory_window_config(CXLState *cxl_state,
26 CXLFixedMemoryWindowOptions *object,
27 Error **errp)
28{
29 g_autofree CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
30 strList *target;
31 int i;
32
33 for (target = object->targets; target; target = target->next) {
34 fw->num_targets++;
35 }
36
37 fw->enc_int_ways = cxl_interleave_ways_enc(fw->num_targets, errp);
38 if (*errp) {
39 return;
40 }
41
42 fw->targets = g_malloc0_n(fw->num_targets, sizeof(*fw->targets));
43 for (i = 0, target = object->targets; target; i++, target = target->next) {
44
45 fw->targets[i] = g_strdup(target->value);
46 }
47
48 if (object->size % (256 * MiB)) {
49 error_setg(errp,
50 "Size of a CXL fixed memory window must be a multiple of 256MiB");
51 return;
52 }
53 fw->size = object->size;
54
55 if (object->has_interleave_granularity) {
56 fw->enc_int_gran =
57 cxl_interleave_granularity_enc(object->interleave_granularity,
58 errp);
59 if (*errp) {
60 return;
61 }
62 } else {
63
64 fw->enc_int_gran = 0;
65 }
66
67 cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows,
68 g_steal_pointer(&fw));
69
70 return;
71}
72
73void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
74{
75 if (cxl_state && cxl_state->fixed_windows) {
76 GList *it;
77
78 for (it = cxl_state->fixed_windows; it; it = it->next) {
79 CXLFixedWindow *fw = it->data;
80 int i;
81
82 for (i = 0; i < fw->num_targets; i++) {
83 Object *o;
84 bool ambig;
85
86 o = object_resolve_path_type(fw->targets[i],
87 TYPE_PXB_CXL_DEVICE,
88 &ambig);
89 if (!o) {
90 error_setg(errp, "Could not resolve CXLFM target %s",
91 fw->targets[i]);
92 return;
93 }
94 fw->target_hbs[i] = PXB_CXL_DEV(o);
95 }
96 }
97 }
98}
99
100
101static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
102 uint8_t *target)
103{
104 uint32_t ctrl;
105 uint32_t ig_enc;
106 uint32_t iw_enc;
107 uint32_t target_idx;
108
109 ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
110 if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
111 return false;
112 }
113
114 ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
115 iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
116 target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
117
118 if (target_idx < 4) {
119 *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO],
120 target_idx * 8, 8);
121 } else {
122 *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_HI],
123 (target_idx - 4) * 8, 8);
124 }
125
126 return true;
127}
128
129static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
130{
131 CXLComponentState *hb_cstate, *usp_cstate;
132 PCIHostState *hb;
133 CXLUpstreamPort *usp;
134 int rb_index;
135 uint32_t *cache_mem;
136 uint8_t target;
137 bool target_found;
138 PCIDevice *rp, *d;
139
140
141 addr += fw->base;
142
143 rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
144 hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl.cxl_host_bridge);
145 if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
146 return NULL;
147 }
148
149 if (cxl_get_hb_passthrough(hb)) {
150 rp = pcie_find_port_first(hb->bus);
151 if (!rp) {
152 return NULL;
153 }
154 } else {
155 hb_cstate = cxl_get_hb_cstate(hb);
156 if (!hb_cstate) {
157 return NULL;
158 }
159
160 cache_mem = hb_cstate->crb.cache_mem_registers;
161
162 target_found = cxl_hdm_find_target(cache_mem, addr, &target);
163 if (!target_found) {
164 return NULL;
165 }
166
167 rp = pcie_find_port_by_pn(hb->bus, target);
168 if (!rp) {
169 return NULL;
170 }
171 }
172
173 d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
174 if (!d) {
175 return NULL;
176 }
177
178 if (object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
179 return d;
180 }
181
182
183
184
185
186 if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_USP)) {
187 return NULL;
188 }
189 usp = CXL_USP(d);
190
191 usp_cstate = cxl_usp_to_cstate(usp);
192 if (!usp_cstate) {
193 return NULL;
194 }
195
196 cache_mem = usp_cstate->crb.cache_mem_registers;
197
198 target_found = cxl_hdm_find_target(cache_mem, addr, &target);
199 if (!target_found) {
200 return NULL;
201 }
202
203 d = pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target);
204 if (!d) {
205 return NULL;
206 }
207
208 d = pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devices[0];
209 if (!d) {
210 return NULL;
211 }
212
213 if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
214 return NULL;
215 }
216
217 return d;
218}
219
220static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
221 unsigned size, MemTxAttrs attrs)
222{
223 CXLFixedWindow *fw = opaque;
224 PCIDevice *d;
225
226 d = cxl_cfmws_find_device(fw, addr);
227 if (d == NULL) {
228 *data = 0;
229
230 return MEMTX_ERROR;
231 }
232
233 return cxl_type3_read(d, addr + fw->base, data, size, attrs);
234}
235
236static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
237 uint64_t data, unsigned size,
238 MemTxAttrs attrs)
239{
240 CXLFixedWindow *fw = opaque;
241 PCIDevice *d;
242
243 d = cxl_cfmws_find_device(fw, addr);
244 if (d == NULL) {
245
246 return MEMTX_OK;
247 }
248
249 return cxl_type3_write(d, addr + fw->base, data, size, attrs);
250}
251
252const MemoryRegionOps cfmws_ops = {
253 .read_with_attrs = cxl_read_cfmws,
254 .write_with_attrs = cxl_write_cfmws,
255 .endianness = DEVICE_LITTLE_ENDIAN,
256 .valid = {
257 .min_access_size = 1,
258 .max_access_size = 8,
259 .unaligned = true,
260 },
261 .impl = {
262 .min_access_size = 1,
263 .max_access_size = 8,
264 .unaligned = true,
265 },
266};
267
268static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
269 void *opaque, Error **errp)
270{
271 CXLState *cxl_state = opaque;
272 bool value = cxl_state->is_enabled;
273
274 visit_type_bool(v, name, &value, errp);
275}
276
277static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
278 void *opaque, Error **errp)
279{
280 CXLState *cxl_state = opaque;
281 bool value;
282
283 if (!visit_type_bool(v, name, &value, errp)) {
284 return;
285 }
286 cxl_state->is_enabled = value;
287}
288
289static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
290 void *opaque, Error **errp)
291{
292 CXLFixedMemoryWindowOptionsList **list = opaque;
293
294 visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
295}
296
297static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
298 void *opaque, Error **errp)
299{
300 CXLState *state = opaque;
301 CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
302 CXLFixedMemoryWindowOptionsList *it;
303
304 visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
305 if (!cfmw_list) {
306 return;
307 }
308
309 for (it = cfmw_list; it; it = it->next) {
310 cxl_fixed_memory_window_config(state, it->value, errp);
311 }
312 state->cfmw_list = cfmw_list;
313}
314
315void cxl_machine_init(Object *obj, CXLState *state)
316{
317 object_property_add(obj, "cxl", "bool", machine_get_cxl,
318 machine_set_cxl, NULL, state);
319 object_property_set_description(obj, "cxl",
320 "Set on/off to enable/disable "
321 "CXL instantiation");
322
323 object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
324 machine_get_cfmw, machine_set_cfmw,
325 NULL, state);
326 object_property_set_description(obj, "cxl-fmw",
327 "CXL Fixed Memory Windows (array)");
328}
329
330void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
331{
332
333 if (bus) {
334 QLIST_FOREACH(bus, &bus->child, sibling) {
335 if (!pci_bus_is_root(bus)) {
336 continue;
337 }
338 if (pci_bus_is_cxl(bus)) {
339 if (!state->is_enabled) {
340 error_setg(errp, "CXL host bridges present, but cxl=off");
341 return;
342 }
343 pxb_cxl_hook_up_registers(state, bus, errp);
344 }
345 }
346 }
347}
348
