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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "hw/i386/x86.h"
28#include "hw/i386/pc.h"
29#include "hw/char/serial.h"
30#include "hw/char/parallel.h"
31#include "hw/i386/topology.h"
32#include "hw/i386/fw_cfg.h"
33#include "hw/i386/vmport.h"
34#include "sysemu/cpus.h"
35#include "hw/block/fdc.h"
36#include "hw/ide/internal.h"
37#include "hw/ide/isa.h"
38#include "hw/pci/pci.h"
39#include "hw/pci/pci_bus.h"
40#include "hw/pci-bridge/pci_expander_bridge.h"
41#include "hw/nvram/fw_cfg.h"
42#include "hw/timer/hpet.h"
43#include "hw/firmware/smbios.h"
44#include "hw/loader.h"
45#include "elf.h"
46#include "migration/vmstate.h"
47#include "multiboot.h"
48#include "hw/rtc/mc146818rtc.h"
49#include "hw/intc/i8259.h"
50#include "hw/intc/ioapic.h"
51#include "hw/timer/i8254.h"
52#include "hw/input/i8042.h"
53#include "hw/irq.h"
54#include "hw/audio/pcspk.h"
55#include "hw/pci/msi.h"
56#include "hw/sysbus.h"
57#include "sysemu/sysemu.h"
58#include "sysemu/tcg.h"
59#include "sysemu/numa.h"
60#include "sysemu/kvm.h"
61#include "sysemu/xen.h"
62#include "sysemu/reset.h"
63#include "sysemu/runstate.h"
64#include "kvm/kvm_i386.h"
65#include "hw/xen/xen.h"
66#include "hw/xen/start_info.h"
67#include "ui/qemu-spice.h"
68#include "exec/memory.h"
69#include "qemu/bitmap.h"
70#include "qemu/config-file.h"
71#include "qemu/error-report.h"
72#include "qemu/option.h"
73#include "qemu/cutils.h"
74#include "hw/acpi/acpi.h"
75#include "hw/acpi/cpu_hotplug.h"
76#include "acpi-build.h"
77#include "hw/mem/pc-dimm.h"
78#include "hw/mem/nvdimm.h"
79#include "hw/cxl/cxl.h"
80#include "hw/cxl/cxl_host.h"
81#include "qapi/error.h"
82#include "qapi/qapi-visit-common.h"
83#include "qapi/qapi-visit-machine.h"
84#include "qapi/visitor.h"
85#include "hw/core/cpu.h"
86#include "hw/usb.h"
87#include "hw/i386/intel_iommu.h"
88#include "hw/net/ne2000-isa.h"
89#include "standard-headers/asm-x86/bootparam.h"
90#include "hw/virtio/virtio-iommu.h"
91#include "hw/virtio/virtio-pmem-pci.h"
92#include "hw/virtio/virtio-mem-pci.h"
93#include "hw/i386/kvm/xen_overlay.h"
94#include "hw/i386/kvm/xen_evtchn.h"
95#include "hw/i386/kvm/xen_gnttab.h"
96#include "hw/i386/kvm/xen_xenstore.h"
97#include "hw/mem/memory-device.h"
98#include "sysemu/replay.h"
99#include "target/i386/cpu.h"
100#include "e820_memory_layout.h"
101#include "fw_cfg.h"
102#include "trace.h"
103#include CONFIG_DEVICES
104
105#ifdef CONFIG_XEN_EMU
106#include "hw/xen/xen-legacy-backend.h"
107#include "hw/xen/xen-bus.h"
108#endif
109
110
111
112
113
114#define PC_CPU_MODEL_IDS(v) \
115 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
116 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
117 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
118
119GlobalProperty pc_compat_7_2[] = {
120 { "ICH9-LPC", "noreboot", "true" },
121};
122const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
123
124GlobalProperty pc_compat_7_1[] = {};
125const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
126
127GlobalProperty pc_compat_7_0[] = {};
128const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
129
130GlobalProperty pc_compat_6_2[] = {
131 { "virtio-mem", "unplugged-inaccessible", "off" },
132};
133const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
134
135GlobalProperty pc_compat_6_1[] = {
136 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
137 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
138 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
139 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
140};
141const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
142
143GlobalProperty pc_compat_6_0[] = {
144 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
145 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
146 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
147 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
148 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
149 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
150};
151const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
152
153GlobalProperty pc_compat_5_2[] = {
154 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
155};
156const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
157
158GlobalProperty pc_compat_5_1[] = {
159 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
160 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
161};
162const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
163
164GlobalProperty pc_compat_5_0[] = {
165};
166const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
167
168GlobalProperty pc_compat_4_2[] = {
169 { "mch", "smbase-smram", "off" },
170};
171const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
172
173GlobalProperty pc_compat_4_1[] = {};
174const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
175
176GlobalProperty pc_compat_4_0[] = {};
177const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
178
179GlobalProperty pc_compat_3_1[] = {
180 { "intel-iommu", "dma-drain", "off" },
181 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
182 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
183 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
184 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
185 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
186 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
187 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
188 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
189 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
190 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
191 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
192 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
193 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
194 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
195 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
196 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
197 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
198 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
199 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
200 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
201};
202const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
203
204GlobalProperty pc_compat_3_0[] = {
205 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
206 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
207 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
208};
209const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
210
211GlobalProperty pc_compat_2_12[] = {
212 { TYPE_X86_CPU, "legacy-cache", "on" },
213 { TYPE_X86_CPU, "topoext", "off" },
214 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
215 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
216};
217const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
218
219GlobalProperty pc_compat_2_11[] = {
220 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
221 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
222};
223const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
224
225GlobalProperty pc_compat_2_10[] = {
226 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
227 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
228 { "q35-pcihost", "x-pci-hole64-fix", "off" },
229};
230const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
231
232GlobalProperty pc_compat_2_9[] = {
233 { "mch", "extended-tseg-mbytes", "0" },
234};
235const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
236
237GlobalProperty pc_compat_2_8[] = {
238 { TYPE_X86_CPU, "tcg-cpuid", "off" },
239 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
240 { "ICH9-LPC", "x-smi-broadcast", "off" },
241 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
242 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
243};
244const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
245
246GlobalProperty pc_compat_2_7[] = {
247 { TYPE_X86_CPU, "l3-cache", "off" },
248 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
249 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
250 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
251 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
252 { "isa-pcspk", "migrate", "off" },
253};
254const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
255
256GlobalProperty pc_compat_2_6[] = {
257 { TYPE_X86_CPU, "cpuid-0xb", "off" },
258 { "vmxnet3", "romfile", "" },
259 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
260 { "apic-common", "legacy-instance-id", "on", }
261};
262const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
263
264GlobalProperty pc_compat_2_5[] = {};
265const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
266
267GlobalProperty pc_compat_2_4[] = {
268 PC_CPU_MODEL_IDS("2.4.0")
269 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
270 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
271 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
272 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
273 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
274 { TYPE_X86_CPU, "check", "off" },
275 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
276 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
277 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
278 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
279 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
280 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
281 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
282 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
283};
284const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
285
286GlobalProperty pc_compat_2_3[] = {
287 PC_CPU_MODEL_IDS("2.3.0")
288 { TYPE_X86_CPU, "arat", "off" },
289 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
290 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
291 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
292 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
293 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
294 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
295 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
296 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
297 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
298 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
299 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
300 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
301 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
302 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
303 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
304 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
305 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
306 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
307 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
308};
309const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
310
311GlobalProperty pc_compat_2_2[] = {
312 PC_CPU_MODEL_IDS("2.2.0")
313 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
314 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
315 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
316 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
317 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
318 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
319 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
320 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
321 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
322 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
323 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
324 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
325 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
326 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
327 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
328 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
329 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
330 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
331};
332const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
333
334GlobalProperty pc_compat_2_1[] = {
335 PC_CPU_MODEL_IDS("2.1.0")
336 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
337 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
338};
339const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
340
341GlobalProperty pc_compat_2_0[] = {
342 PC_CPU_MODEL_IDS("2.0.0")
343 { "virtio-scsi-pci", "any_layout", "off" },
344 { "PIIX4_PM", "memory-hotplug-support", "off" },
345 { "apic", "version", "0x11" },
346 { "nec-usb-xhci", "superspeed-ports-first", "off" },
347 { "nec-usb-xhci", "force-pcie-endcap", "on" },
348 { "pci-serial", "prog_if", "0" },
349 { "pci-serial-2x", "prog_if", "0" },
350 { "pci-serial-4x", "prog_if", "0" },
351 { "virtio-net-pci", "guest_announce", "off" },
352 { "ICH9-LPC", "memory-hotplug-support", "off" },
353};
354const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
355
356GlobalProperty pc_compat_1_7[] = {
357 PC_CPU_MODEL_IDS("1.7.0")
358 { TYPE_USB_DEVICE, "msos-desc", "no" },
359 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
360 { "hpet", HPET_INTCAP, "4" },
361};
362const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
363
364GlobalProperty pc_compat_1_6[] = {
365 PC_CPU_MODEL_IDS("1.6.0")
366 { "e1000", "mitigation", "off" },
367 { "qemu64-" TYPE_X86_CPU, "model", "2" },
368 { "qemu32-" TYPE_X86_CPU, "model", "3" },
369 { "i440FX-pcihost", "short_root_bus", "1" },
370 { "q35-pcihost", "short_root_bus", "1" },
371};
372const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
373
374GlobalProperty pc_compat_1_5[] = {
375 PC_CPU_MODEL_IDS("1.5.0")
376 { "Conroe-" TYPE_X86_CPU, "model", "2" },
377 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
378 { "Penryn-" TYPE_X86_CPU, "model", "2" },
379 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
380 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
381 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
382 { "virtio-net-pci", "any_layout", "off" },
383 { TYPE_X86_CPU, "pmu", "on" },
384 { "i440FX-pcihost", "short_root_bus", "0" },
385 { "q35-pcihost", "short_root_bus", "0" },
386};
387const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
388
389GlobalProperty pc_compat_1_4[] = {
390 PC_CPU_MODEL_IDS("1.4.0")
391 { "scsi-hd", "discard_granularity", "0" },
392 { "scsi-cd", "discard_granularity", "0" },
393 { "ide-hd", "discard_granularity", "0" },
394 { "ide-cd", "discard_granularity", "0" },
395 { "virtio-blk-pci", "discard_granularity", "0" },
396
397 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
398 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
399 { "e1000", "romfile", "pxe-e1000.rom" },
400 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
401 { "pcnet", "romfile", "pxe-pcnet.rom" },
402 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
403 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
404 { "486-" TYPE_X86_CPU, "model", "0" },
405 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
406 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
407};
408const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
409
410GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
411{
412 GSIState *s;
413
414 s = g_new0(GSIState, 1);
415 if (kvm_ioapic_in_kernel()) {
416 kvm_pc_setup_irq_routing(pci_enabled);
417 }
418 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
419
420 return s;
421}
422
423static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
424 unsigned size)
425{
426}
427
428static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
429{
430 return 0xffffffffffffffffULL;
431}
432
433
434static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
435 unsigned size)
436{
437 if (tcg_enabled()) {
438 cpu_set_ignne();
439 }
440}
441
442static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
443{
444 return 0xffffffffffffffffULL;
445}
446
447
448
449#define REG_EQUIPMENT_BYTE 0x14
450
451static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
452 int16_t cylinders, int8_t heads, int8_t sectors)
453{
454 mc146818rtc_set_cmos_data(s, type_ofs, 47);
455 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
456 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
457 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
458 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
459 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
460 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
461 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
462 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
463 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
464}
465
466
467static int boot_device2nibble(char boot_device)
468{
469 switch(boot_device) {
470 case 'a':
471 case 'b':
472 return 0x01;
473 case 'c':
474 return 0x02;
475 case 'd':
476 return 0x03;
477 case 'n':
478 return 0x04;
479 }
480 return 0;
481}
482
483static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
484 Error **errp)
485{
486#define PC_MAX_BOOT_DEVICES 3
487 int nbds, bds[3] = { 0, };
488 int i;
489
490 nbds = strlen(boot_device);
491 if (nbds > PC_MAX_BOOT_DEVICES) {
492 error_setg(errp, "Too many boot devices for PC");
493 return;
494 }
495 for (i = 0; i < nbds; i++) {
496 bds[i] = boot_device2nibble(boot_device[i]);
497 if (bds[i] == 0) {
498 error_setg(errp, "Invalid boot device for PC: '%c'",
499 boot_device[i]);
500 return;
501 }
502 }
503 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
504 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
505}
506
507static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
508{
509 set_boot_dev(opaque, boot_device, errp);
510}
511
512static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
513{
514 int val, nb, i;
515 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
516 FLOPPY_DRIVE_TYPE_NONE };
517
518
519 if (floppy) {
520 for (i = 0; i < 2; i++) {
521 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
522 }
523 }
524 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
525 cmos_get_fd_drive_type(fd_type[1]);
526 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
527
528 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
529 nb = 0;
530 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
531 nb++;
532 }
533 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
534 nb++;
535 }
536 switch (nb) {
537 case 0:
538 break;
539 case 1:
540 val |= 0x01;
541 break;
542 case 2:
543 val |= 0x41;
544 break;
545 }
546 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
547}
548
549typedef struct pc_cmos_init_late_arg {
550 MC146818RtcState *rtc_state;
551 BusState *idebus[2];
552} pc_cmos_init_late_arg;
553
554typedef struct check_fdc_state {
555 ISADevice *floppy;
556 bool multiple;
557} CheckFdcState;
558
559static int check_fdc(Object *obj, void *opaque)
560{
561 CheckFdcState *state = opaque;
562 Object *fdc;
563 uint32_t iobase;
564 Error *local_err = NULL;
565
566 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
567 if (!fdc) {
568 return 0;
569 }
570
571 iobase = object_property_get_uint(obj, "iobase", &local_err);
572 if (local_err || iobase != 0x3f0) {
573 error_free(local_err);
574 return 0;
575 }
576
577 if (state->floppy) {
578 state->multiple = true;
579 } else {
580 state->floppy = ISA_DEVICE(obj);
581 }
582 return 0;
583}
584
585static const char * const fdc_container_path[] = {
586 "/unattached", "/peripheral", "/peripheral-anon"
587};
588
589
590
591
592
593static ISADevice *pc_find_fdc0(void)
594{
595 int i;
596 Object *container;
597 CheckFdcState state = { 0 };
598
599 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
600 container = container_get(qdev_get_machine(), fdc_container_path[i]);
601 object_child_foreach(container, check_fdc, &state);
602 }
603
604 if (state.multiple) {
605 warn_report("multiple floppy disk controllers with "
606 "iobase=0x3f0 have been found");
607 error_printf("the one being picked for CMOS setup might not reflect "
608 "your intent");
609 }
610
611 return state.floppy;
612}
613
614static void pc_cmos_init_late(void *opaque)
615{
616 pc_cmos_init_late_arg *arg = opaque;
617 MC146818RtcState *s = arg->rtc_state;
618 int16_t cylinders;
619 int8_t heads, sectors;
620 int val;
621 int i, trans;
622
623 val = 0;
624 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
625 &cylinders, &heads, §ors) >= 0) {
626 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
627 val |= 0xf0;
628 }
629 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
630 &cylinders, &heads, §ors) >= 0) {
631 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
632 val |= 0x0f;
633 }
634 mc146818rtc_set_cmos_data(s, 0x12, val);
635
636 val = 0;
637 for (i = 0; i < 4; i++) {
638
639
640
641
642 if (arg->idebus[i / 2] &&
643 ide_get_geometry(arg->idebus[i / 2], i % 2,
644 &cylinders, &heads, §ors) >= 0) {
645 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
646 assert((trans & ~3) == 0);
647 val |= trans << (i * 2);
648 }
649 }
650 mc146818rtc_set_cmos_data(s, 0x39, val);
651
652 pc_cmos_init_floppy(s, pc_find_fdc0());
653
654 qemu_unregister_reset(pc_cmos_init_late, opaque);
655}
656
657void pc_cmos_init(PCMachineState *pcms,
658 BusState *idebus0, BusState *idebus1,
659 ISADevice *rtc)
660{
661 int val;
662 static pc_cmos_init_late_arg arg;
663 X86MachineState *x86ms = X86_MACHINE(pcms);
664 MC146818RtcState *s = MC146818_RTC(rtc);
665
666
667
668
669
670 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
671 mc146818rtc_set_cmos_data(s, 0x15, val);
672 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
673
674 if (x86ms->below_4g_mem_size > 1 * MiB) {
675 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
676 } else {
677 val = 0;
678 }
679 if (val > 65535)
680 val = 65535;
681 mc146818rtc_set_cmos_data(s, 0x17, val);
682 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
683 mc146818rtc_set_cmos_data(s, 0x30, val);
684 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
685
686 if (x86ms->below_4g_mem_size > 16 * MiB) {
687 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
688 } else {
689 val = 0;
690 }
691 if (val > 65535)
692 val = 65535;
693 mc146818rtc_set_cmos_data(s, 0x34, val);
694 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
695
696 val = x86ms->above_4g_mem_size / 65536;
697 mc146818rtc_set_cmos_data(s, 0x5b, val);
698 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
699 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
700
701 object_property_add_link(OBJECT(pcms), "rtc_state",
702 TYPE_ISA_DEVICE,
703 (Object **)&x86ms->rtc,
704 object_property_allow_set_link,
705 OBJ_PROP_LINK_STRONG);
706 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
707 &error_abort);
708
709 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
710
711 val = 0;
712 val |= 0x02;
713 val |= 0x04;
714 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
715
716
717 arg.rtc_state = s;
718 arg.idebus[0] = idebus0;
719 arg.idebus[1] = idebus1;
720 qemu_register_reset(pc_cmos_init_late, &arg);
721}
722
723static void handle_a20_line_change(void *opaque, int irq, int level)
724{
725 X86CPU *cpu = opaque;
726
727
728
729 x86_cpu_set_a20(cpu, level);
730}
731
732#define NE2000_NB_MAX 6
733
734static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
735 0x280, 0x380 };
736static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
737
738static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
739{
740 static int nb_ne2k = 0;
741
742 if (nb_ne2k == NE2000_NB_MAX)
743 return;
744 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
745 ne2000_irq[nb_ne2k], nd);
746 nb_ne2k++;
747}
748
749void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
750{
751 X86CPU *cpu = opaque;
752
753 if (level) {
754 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
755 }
756}
757
758static
759void pc_machine_done(Notifier *notifier, void *data)
760{
761 PCMachineState *pcms = container_of(notifier,
762 PCMachineState, machine_done);
763 X86MachineState *x86ms = X86_MACHINE(pcms);
764
765 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
766 &error_fatal);
767
768 if (pcms->cxl_devices_state.is_enabled) {
769 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
770 }
771
772
773 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
774
775 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
776
777 acpi_setup();
778 if (x86ms->fw_cfg) {
779 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
780 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
781
782 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
783 }
784}
785
786void pc_guest_info_init(PCMachineState *pcms)
787{
788 X86MachineState *x86ms = X86_MACHINE(pcms);
789
790 x86ms->apic_xrupt_override = true;
791 pcms->machine_done.notify = pc_machine_done;
792 qemu_add_machine_init_done_notifier(&pcms->machine_done);
793}
794
795
796void pc_pci_as_mapping_init(MemoryRegion *system_memory,
797 MemoryRegion *pci_address_space)
798{
799
800 memory_region_add_subregion_overlap(system_memory, 0x0,
801 pci_address_space, -1);
802}
803
804void xen_load_linux(PCMachineState *pcms)
805{
806 int i;
807 FWCfgState *fw_cfg;
808 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
809 X86MachineState *x86ms = X86_MACHINE(pcms);
810
811 assert(MACHINE(pcms)->kernel_filename != NULL);
812
813 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
814 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
815 rom_set_fw(fw_cfg);
816
817 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
818 pcmc->pvh_enabled);
819 for (i = 0; i < nb_option_roms; i++) {
820 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
821 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
822 !strcmp(option_rom[i].name, "pvh.bin") ||
823 !strcmp(option_rom[i].name, "multiboot.bin") ||
824 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
825 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
826 }
827 x86ms->fw_cfg = fw_cfg;
828}
829
830#define PC_ROM_MIN_VGA 0xc0000
831#define PC_ROM_MIN_OPTION 0xc8000
832#define PC_ROM_MAX 0xe0000
833#define PC_ROM_ALIGN 0x800
834#define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
835
836static hwaddr pc_above_4g_end(PCMachineState *pcms)
837{
838 X86MachineState *x86ms = X86_MACHINE(pcms);
839
840 if (pcms->sgx_epc.size != 0) {
841 return sgx_epc_above_4g_end(&pcms->sgx_epc);
842 }
843
844 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
845}
846
847static void pc_get_device_memory_range(PCMachineState *pcms,
848 hwaddr *base,
849 ram_addr_t *device_mem_size)
850{
851 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
852 MachineState *machine = MACHINE(pcms);
853 ram_addr_t size;
854 hwaddr addr;
855
856 size = machine->maxram_size - machine->ram_size;
857 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
858
859 if (pcmc->enforce_aligned_dimm) {
860
861 size += (1 * GiB) * machine->ram_slots;
862 }
863
864 *base = addr;
865 *device_mem_size = size;
866}
867
868static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
869{
870 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
871 hwaddr cxl_base;
872 ram_addr_t size;
873
874 if (pcmc->has_reserved_memory) {
875 pc_get_device_memory_range(pcms, &cxl_base, &size);
876 cxl_base += size;
877 } else {
878 cxl_base = pc_above_4g_end(pcms);
879 }
880
881 return cxl_base;
882}
883
884static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
885{
886 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
887
888 if (pcms->cxl_devices_state.fixed_windows) {
889 GList *it;
890
891 start = ROUND_UP(start, 256 * MiB);
892 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
893 CXLFixedWindow *fw = it->data;
894 start += fw->size;
895 }
896 }
897
898 return start;
899}
900
901static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
902{
903 X86CPU *cpu = X86_CPU(first_cpu);
904
905
906 if (cpu->phys_bits <= 32) {
907 return ((hwaddr)1 << cpu->phys_bits) - 1;
908 }
909
910 return pc_pci_hole64_start() + pci_hole64_size - 1;
911}
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942#define AMD_HT_START 0xfd00000000UL
943#define AMD_HT_END 0xffffffffffUL
944#define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
945#define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
946
947void pc_memory_init(PCMachineState *pcms,
948 MemoryRegion *system_memory,
949 MemoryRegion *rom_memory,
950 MemoryRegion **ram_memory,
951 uint64_t pci_hole64_size)
952{
953 int linux_boot, i;
954 MemoryRegion *option_rom_mr;
955 MemoryRegion *ram_below_4g, *ram_above_4g;
956 FWCfgState *fw_cfg;
957 MachineState *machine = MACHINE(pcms);
958 MachineClass *mc = MACHINE_GET_CLASS(machine);
959 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
960 X86MachineState *x86ms = X86_MACHINE(pcms);
961 hwaddr maxphysaddr, maxusedaddr;
962 hwaddr cxl_base, cxl_resv_end = 0;
963 X86CPU *cpu = X86_CPU(first_cpu);
964
965 assert(machine->ram_size == x86ms->below_4g_mem_size +
966 x86ms->above_4g_mem_size);
967
968 linux_boot = (machine->kernel_filename != NULL);
969
970
971
972
973
974
975
976 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
977
978 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
979 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
980 }
981
982
983
984
985
986 if (cpu->phys_bits >= 40) {
987 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
988 }
989 }
990
991
992
993
994
995 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
996 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
997 if (maxphysaddr < maxusedaddr) {
998 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
999 " phys-bits too low (%u)",
1000 maxphysaddr, maxusedaddr, cpu->phys_bits);
1001 exit(EXIT_FAILURE);
1002 }
1003
1004
1005
1006
1007
1008 *ram_memory = machine->ram;
1009 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1010 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
1011 0, x86ms->below_4g_mem_size);
1012 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1013 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
1014 if (x86ms->above_4g_mem_size > 0) {
1015 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1016 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
1017 machine->ram,
1018 x86ms->below_4g_mem_size,
1019 x86ms->above_4g_mem_size);
1020 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
1021 ram_above_4g);
1022 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
1023 E820_RAM);
1024 }
1025
1026 if (pcms->sgx_epc.size != 0) {
1027 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
1028 }
1029
1030 if (!pcmc->has_reserved_memory &&
1031 (machine->ram_slots ||
1032 (machine->maxram_size > machine->ram_size))) {
1033
1034 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1035 mc->name);
1036 exit(EXIT_FAILURE);
1037 }
1038
1039
1040 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1041
1042
1043 if (pcmc->has_reserved_memory &&
1044 (machine->ram_size < machine->maxram_size)) {
1045 ram_addr_t device_mem_size;
1046
1047 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1048 error_report("unsupported amount of memory slots: %"PRIu64,
1049 machine->ram_slots);
1050 exit(EXIT_FAILURE);
1051 }
1052
1053 if (QEMU_ALIGN_UP(machine->maxram_size,
1054 TARGET_PAGE_SIZE) != machine->maxram_size) {
1055 error_report("maximum memory size must by aligned to multiple of "
1056 "%d bytes", TARGET_PAGE_SIZE);
1057 exit(EXIT_FAILURE);
1058 }
1059
1060 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size);
1061
1062 if ((machine->device_memory->base + device_mem_size) <
1063 device_mem_size) {
1064 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1065 machine->maxram_size);
1066 exit(EXIT_FAILURE);
1067 }
1068
1069 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1070 "device-memory", device_mem_size);
1071 memory_region_add_subregion(system_memory, machine->device_memory->base,
1072 &machine->device_memory->mr);
1073 }
1074
1075 if (pcms->cxl_devices_state.is_enabled) {
1076 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1077 hwaddr cxl_size = MiB;
1078
1079 cxl_base = pc_get_cxl_range_start(pcms);
1080 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1081 memory_region_add_subregion(system_memory, cxl_base, mr);
1082 cxl_resv_end = cxl_base + cxl_size;
1083 if (pcms->cxl_devices_state.fixed_windows) {
1084 hwaddr cxl_fmw_base;
1085 GList *it;
1086
1087 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1088 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1089 CXLFixedWindow *fw = it->data;
1090
1091 fw->base = cxl_fmw_base;
1092 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1093 "cxl-fixed-memory-region", fw->size);
1094 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1095 cxl_fmw_base += fw->size;
1096 cxl_resv_end = cxl_fmw_base;
1097 }
1098 }
1099 }
1100
1101
1102 pc_system_firmware_init(pcms, rom_memory);
1103
1104 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1105 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1106 &error_fatal);
1107 if (pcmc->pci_enabled) {
1108 memory_region_set_readonly(option_rom_mr, true);
1109 }
1110 memory_region_add_subregion_overlap(rom_memory,
1111 PC_ROM_MIN_VGA,
1112 option_rom_mr,
1113 1);
1114
1115 fw_cfg = fw_cfg_arch_create(machine,
1116 x86ms->boot_cpus, x86ms->apic_id_limit);
1117
1118 rom_set_fw(fw_cfg);
1119
1120 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1121 uint64_t *val = g_malloc(sizeof(*val));
1122 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1123 uint64_t res_mem_end = machine->device_memory->base;
1124
1125 if (!pcmc->broken_reserved_end) {
1126 res_mem_end += memory_region_size(&machine->device_memory->mr);
1127 }
1128
1129 if (pcms->cxl_devices_state.is_enabled) {
1130 res_mem_end = cxl_resv_end;
1131 }
1132 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1133 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1134 }
1135
1136 if (linux_boot) {
1137 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1138 pcmc->pvh_enabled);
1139 }
1140
1141 for (i = 0; i < nb_option_roms; i++) {
1142 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1143 }
1144 x86ms->fw_cfg = fw_cfg;
1145
1146
1147 x86ms->ioapic_as = &address_space_memory;
1148
1149
1150 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1151}
1152
1153
1154
1155
1156
1157uint64_t pc_pci_hole64_start(void)
1158{
1159 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1160 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1161 MachineState *ms = MACHINE(pcms);
1162 uint64_t hole64_start = 0;
1163 ram_addr_t size = 0;
1164
1165 if (pcms->cxl_devices_state.is_enabled) {
1166 hole64_start = pc_get_cxl_range_end(pcms);
1167 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1168 pc_get_device_memory_range(pcms, &hole64_start, &size);
1169 if (!pcmc->broken_reserved_end) {
1170 hole64_start += size;
1171 }
1172 } else {
1173 hole64_start = pc_above_4g_end(pcms);
1174 }
1175
1176 return ROUND_UP(hole64_start, 1 * GiB);
1177}
1178
1179DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1180{
1181 DeviceState *dev = NULL;
1182
1183 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1184 if (pci_bus) {
1185 PCIDevice *pcidev = pci_vga_init(pci_bus);
1186 dev = pcidev ? &pcidev->qdev : NULL;
1187 } else if (isa_bus) {
1188 ISADevice *isadev = isa_vga_init(isa_bus);
1189 dev = isadev ? DEVICE(isadev) : NULL;
1190 }
1191 rom_reset_order_override();
1192 return dev;
1193}
1194
1195static const MemoryRegionOps ioport80_io_ops = {
1196 .write = ioport80_write,
1197 .read = ioport80_read,
1198 .endianness = DEVICE_NATIVE_ENDIAN,
1199 .impl = {
1200 .min_access_size = 1,
1201 .max_access_size = 1,
1202 },
1203};
1204
1205static const MemoryRegionOps ioportF0_io_ops = {
1206 .write = ioportF0_write,
1207 .read = ioportF0_read,
1208 .endianness = DEVICE_NATIVE_ENDIAN,
1209 .impl = {
1210 .min_access_size = 1,
1211 .max_access_size = 1,
1212 },
1213};
1214
1215static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1216 bool create_i8042, bool no_vmport)
1217{
1218 int i;
1219 DriveInfo *fd[MAX_FD];
1220 qemu_irq *a20_line;
1221 ISADevice *fdc, *i8042, *port92, *vmmouse;
1222
1223 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1224 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1225
1226 for (i = 0; i < MAX_FD; i++) {
1227 fd[i] = drive_get(IF_FLOPPY, 0, i);
1228 create_fdctrl |= !!fd[i];
1229 }
1230 if (create_fdctrl) {
1231 fdc = isa_new(TYPE_ISA_FDC);
1232 if (fdc) {
1233 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1234 isa_fdc_init_drives(fdc, fd);
1235 }
1236 }
1237
1238 if (!create_i8042) {
1239 return;
1240 }
1241
1242 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1243 if (!no_vmport) {
1244 isa_create_simple(isa_bus, TYPE_VMPORT);
1245 vmmouse = isa_try_new("vmmouse");
1246 } else {
1247 vmmouse = NULL;
1248 }
1249 if (vmmouse) {
1250 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1251 &error_abort);
1252 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1253 }
1254 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1255
1256 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1257 i8042_setup_a20_line(i8042, a20_line[0]);
1258 qdev_connect_gpio_out_named(DEVICE(port92),
1259 PORT92_A20_LINE, 0, a20_line[1]);
1260 g_free(a20_line);
1261}
1262
1263void pc_basic_device_init(struct PCMachineState *pcms,
1264 ISABus *isa_bus, qemu_irq *gsi,
1265 ISADevice **rtc_state,
1266 bool create_fdctrl,
1267 uint32_t hpet_irqs)
1268{
1269 int i;
1270 DeviceState *hpet = NULL;
1271 int pit_isa_irq = 0;
1272 qemu_irq pit_alt_irq = NULL;
1273 qemu_irq rtc_irq = NULL;
1274 ISADevice *pit = NULL;
1275 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1276 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1277 X86MachineState *x86ms = X86_MACHINE(pcms);
1278
1279 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1280 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1281
1282 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1283 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1284
1285
1286
1287
1288
1289
1290
1291 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1292 kvm_has_pit_state2())) {
1293 hpet = qdev_try_new(TYPE_HPET);
1294 if (!hpet) {
1295 error_report("couldn't create HPET device");
1296 exit(1);
1297 }
1298
1299
1300
1301
1302
1303 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1304 HPET_INTCAP, NULL);
1305 if (!compat) {
1306 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1307 }
1308 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1309 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1310
1311 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1312 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1313 }
1314 pit_isa_irq = -1;
1315 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1316 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1317 }
1318 *rtc_state = ISA_DEVICE(mc146818_rtc_init(isa_bus, 2000, rtc_irq));
1319
1320#ifdef CONFIG_XEN_EMU
1321 if (xen_mode == XEN_EMULATE) {
1322 xen_evtchn_connect_gsis(gsi);
1323 if (pcms->bus) {
1324 pci_create_simple(pcms->bus, -1, "xen-platform");
1325 }
1326 xen_bus_init();
1327 xen_be_init();
1328 }
1329#endif
1330
1331 qemu_register_boot_set(pc_boot_set, *rtc_state);
1332
1333 if (!xen_enabled() &&
1334 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1335 if (kvm_pit_in_kernel()) {
1336 pit = kvm_pit_init(isa_bus, 0x40);
1337 } else {
1338 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1339 }
1340 if (hpet) {
1341
1342 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1343 }
1344 pcspk_init(pcms->pcspk, isa_bus, pit);
1345 }
1346
1347
1348 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1349 pcms->vmport != ON_OFF_AUTO_ON);
1350}
1351
1352void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1353{
1354 int i;
1355
1356 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1357 for (i = 0; i < nb_nics; i++) {
1358 NICInfo *nd = &nd_table[i];
1359 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1360
1361 if (g_str_equal(model, "ne2k_isa")) {
1362 pc_init_ne2k_isa(isa_bus, nd);
1363 } else {
1364 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1365 }
1366 }
1367 rom_reset_order_override();
1368}
1369
1370void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1371{
1372 qemu_irq *i8259;
1373
1374 if (kvm_pic_in_kernel()) {
1375 i8259 = kvm_i8259_init(isa_bus);
1376 } else if (xen_enabled()) {
1377 i8259 = xen_interrupt_controller_init();
1378 } else {
1379 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1380 }
1381
1382 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1383 i8259_irqs[i] = i8259[i];
1384 }
1385
1386 g_free(i8259);
1387}
1388
1389static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1390 Error **errp)
1391{
1392 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1393 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1394 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1395 const MachineState *ms = MACHINE(hotplug_dev);
1396 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1397 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1398 Error *local_err = NULL;
1399
1400
1401
1402
1403
1404
1405 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1406 error_setg(errp,
1407 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1408 return;
1409 }
1410
1411 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1412 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1413 return;
1414 }
1415
1416 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1417 if (local_err) {
1418 error_propagate(errp, local_err);
1419 return;
1420 }
1421
1422 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1423 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1424}
1425
1426static void pc_memory_plug(HotplugHandler *hotplug_dev,
1427 DeviceState *dev, Error **errp)
1428{
1429 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1430 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1431 MachineState *ms = MACHINE(hotplug_dev);
1432 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1433
1434 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1435
1436 if (is_nvdimm) {
1437 nvdimm_plug(ms->nvdimms_state);
1438 }
1439
1440 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1441}
1442
1443static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1444 DeviceState *dev, Error **errp)
1445{
1446 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1447
1448
1449
1450
1451
1452
1453 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1454 error_setg(errp,
1455 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1456 return;
1457 }
1458
1459 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1460 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1461 return;
1462 }
1463
1464 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1465 errp);
1466}
1467
1468static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1469 DeviceState *dev, Error **errp)
1470{
1471 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1472 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1473 Error *local_err = NULL;
1474
1475 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1476 if (local_err) {
1477 goto out;
1478 }
1479
1480 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1481 qdev_unrealize(dev);
1482 out:
1483 error_propagate(errp, local_err);
1484}
1485
1486static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1487 DeviceState *dev, Error **errp)
1488{
1489 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1490 Error *local_err = NULL;
1491
1492 if (!hotplug_dev2 && dev->hotplugged) {
1493
1494
1495
1496
1497
1498 error_setg(errp, "hotplug of virtio based memory devices not supported"
1499 " on this bus.");
1500 return;
1501 }
1502
1503
1504
1505
1506 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1507 &local_err);
1508 if (!local_err && hotplug_dev2) {
1509 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1510 }
1511 error_propagate(errp, local_err);
1512}
1513
1514static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1515 DeviceState *dev, Error **errp)
1516{
1517 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1518 Error *local_err = NULL;
1519
1520
1521
1522
1523
1524
1525 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1526 if (hotplug_dev2) {
1527 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1528 if (local_err) {
1529 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1530 }
1531 }
1532 error_propagate(errp, local_err);
1533}
1534
1535static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1536 DeviceState *dev, Error **errp)
1537{
1538
1539 error_setg(errp, "virtio based memory devices cannot be unplugged.");
1540}
1541
1542static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1543 DeviceState *dev, Error **errp)
1544{
1545
1546}
1547
1548static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1549 DeviceState *dev, Error **errp)
1550{
1551 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1552 pc_memory_pre_plug(hotplug_dev, dev, errp);
1553 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1554 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1555 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1556 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1557 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1558 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1559
1560 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1561 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1562
1563 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1564 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1565 resv_prop_str, errp);
1566 g_free(resv_prop_str);
1567 }
1568
1569 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1570 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1571 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1572
1573 if (pcms->iommu) {
1574 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1575 "for x86 yet.");
1576 return;
1577 }
1578 pcms->iommu = dev;
1579 }
1580}
1581
1582static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1583 DeviceState *dev, Error **errp)
1584{
1585 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1586 pc_memory_plug(hotplug_dev, dev, errp);
1587 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1588 x86_cpu_plug(hotplug_dev, dev, errp);
1589 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1590 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1591 pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1592 }
1593}
1594
1595static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1596 DeviceState *dev, Error **errp)
1597{
1598 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1599 pc_memory_unplug_request(hotplug_dev, dev, errp);
1600 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1601 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1602 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1603 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1604 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1605 } else {
1606 error_setg(errp, "acpi: device unplug request for not supported device"
1607 " type: %s", object_get_typename(OBJECT(dev)));
1608 }
1609}
1610
1611static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1612 DeviceState *dev, Error **errp)
1613{
1614 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1615 pc_memory_unplug(hotplug_dev, dev, errp);
1616 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1617 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1618 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1619 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1620 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1621 } else {
1622 error_setg(errp, "acpi: device unplug for not supported device"
1623 " type: %s", object_get_typename(OBJECT(dev)));
1624 }
1625}
1626
1627static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1628 DeviceState *dev)
1629{
1630 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1631 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1632 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1633 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
1634 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1635 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1636 return HOTPLUG_HANDLER(machine);
1637 }
1638
1639 return NULL;
1640}
1641
1642static void
1643pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1644 const char *name, void *opaque,
1645 Error **errp)
1646{
1647 MachineState *ms = MACHINE(obj);
1648 int64_t value = 0;
1649
1650 if (ms->device_memory) {
1651 value = memory_region_size(&ms->device_memory->mr);
1652 }
1653
1654 visit_type_int(v, name, &value, errp);
1655}
1656
1657static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1658 void *opaque, Error **errp)
1659{
1660 PCMachineState *pcms = PC_MACHINE(obj);
1661 OnOffAuto vmport = pcms->vmport;
1662
1663 visit_type_OnOffAuto(v, name, &vmport, errp);
1664}
1665
1666static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1667 void *opaque, Error **errp)
1668{
1669 PCMachineState *pcms = PC_MACHINE(obj);
1670
1671 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1672}
1673
1674static bool pc_machine_get_smbus(Object *obj, Error **errp)
1675{
1676 PCMachineState *pcms = PC_MACHINE(obj);
1677
1678 return pcms->smbus_enabled;
1679}
1680
1681static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1682{
1683 PCMachineState *pcms = PC_MACHINE(obj);
1684
1685 pcms->smbus_enabled = value;
1686}
1687
1688static bool pc_machine_get_sata(Object *obj, Error **errp)
1689{
1690 PCMachineState *pcms = PC_MACHINE(obj);
1691
1692 return pcms->sata_enabled;
1693}
1694
1695static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1696{
1697 PCMachineState *pcms = PC_MACHINE(obj);
1698
1699 pcms->sata_enabled = value;
1700}
1701
1702static bool pc_machine_get_hpet(Object *obj, Error **errp)
1703{
1704 PCMachineState *pcms = PC_MACHINE(obj);
1705
1706 return pcms->hpet_enabled;
1707}
1708
1709static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1710{
1711 PCMachineState *pcms = PC_MACHINE(obj);
1712
1713 pcms->hpet_enabled = value;
1714}
1715
1716static bool pc_machine_get_i8042(Object *obj, Error **errp)
1717{
1718 PCMachineState *pcms = PC_MACHINE(obj);
1719
1720 return pcms->i8042_enabled;
1721}
1722
1723static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1724{
1725 PCMachineState *pcms = PC_MACHINE(obj);
1726
1727 pcms->i8042_enabled = value;
1728}
1729
1730static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1731{
1732 PCMachineState *pcms = PC_MACHINE(obj);
1733
1734 return pcms->default_bus_bypass_iommu;
1735}
1736
1737static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1738 Error **errp)
1739{
1740 PCMachineState *pcms = PC_MACHINE(obj);
1741
1742 pcms->default_bus_bypass_iommu = value;
1743}
1744
1745static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1746 void *opaque, Error **errp)
1747{
1748 PCMachineState *pcms = PC_MACHINE(obj);
1749 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1750
1751 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1752}
1753
1754static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1755 void *opaque, Error **errp)
1756{
1757 PCMachineState *pcms = PC_MACHINE(obj);
1758
1759 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1760}
1761
1762static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1763 const char *name, void *opaque,
1764 Error **errp)
1765{
1766 PCMachineState *pcms = PC_MACHINE(obj);
1767 uint64_t value = pcms->max_ram_below_4g;
1768
1769 visit_type_size(v, name, &value, errp);
1770}
1771
1772static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1773 const char *name, void *opaque,
1774 Error **errp)
1775{
1776 PCMachineState *pcms = PC_MACHINE(obj);
1777 uint64_t value;
1778
1779 if (!visit_type_size(v, name, &value, errp)) {
1780 return;
1781 }
1782 if (value > 4 * GiB) {
1783 error_setg(errp,
1784 "Machine option 'max-ram-below-4g=%"PRIu64
1785 "' expects size less than or equal to 4G", value);
1786 return;
1787 }
1788
1789 if (value < 1 * MiB) {
1790 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1791 "BIOS may not work with less than 1MiB", value);
1792 }
1793
1794 pcms->max_ram_below_4g = value;
1795}
1796
1797static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1798 const char *name, void *opaque,
1799 Error **errp)
1800{
1801 PCMachineState *pcms = PC_MACHINE(obj);
1802 uint64_t value = pcms->max_fw_size;
1803
1804 visit_type_size(v, name, &value, errp);
1805}
1806
1807static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1808 const char *name, void *opaque,
1809 Error **errp)
1810{
1811 PCMachineState *pcms = PC_MACHINE(obj);
1812 uint64_t value;
1813
1814 if (!visit_type_size(v, name, &value, errp)) {
1815 return;
1816 }
1817
1818
1819
1820
1821
1822
1823
1824
1825 if (value > 16 * MiB) {
1826 error_setg(errp,
1827 "User specified max allowed firmware size %" PRIu64 " is "
1828 "greater than 16MiB. If combined firwmare size exceeds "
1829 "16MiB the system may not boot, or experience intermittent"
1830 "stability issues.",
1831 value);
1832 return;
1833 }
1834
1835 pcms->max_fw_size = value;
1836}
1837
1838
1839static void pc_machine_initfn(Object *obj)
1840{
1841 PCMachineState *pcms = PC_MACHINE(obj);
1842
1843#ifdef CONFIG_VMPORT
1844 pcms->vmport = ON_OFF_AUTO_AUTO;
1845#else
1846 pcms->vmport = ON_OFF_AUTO_OFF;
1847#endif
1848 pcms->max_ram_below_4g = 0;
1849 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1850
1851
1852 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1853 pcms->smbus_enabled = true;
1854 pcms->sata_enabled = true;
1855 pcms->i8042_enabled = true;
1856 pcms->max_fw_size = 8 * MiB;
1857#ifdef CONFIG_HPET
1858 pcms->hpet_enabled = true;
1859#endif
1860 pcms->default_bus_bypass_iommu = false;
1861
1862 pc_system_flash_create(pcms);
1863 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1864 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1865 OBJECT(pcms->pcspk), "audiodev");
1866 cxl_machine_init(obj, &pcms->cxl_devices_state);
1867}
1868
1869int pc_machine_kvm_type(MachineState *machine, const char *kvm_type)
1870{
1871#ifdef CONFIG_XEN_EMU
1872 if (xen_mode == XEN_EMULATE) {
1873 xen_overlay_create();
1874 xen_evtchn_create();
1875 xen_gnttab_create();
1876 xen_xenstore_create();
1877 }
1878#endif
1879 return 0;
1880}
1881
1882static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1883{
1884 CPUState *cs;
1885 X86CPU *cpu;
1886
1887 qemu_devices_reset(reason);
1888
1889
1890
1891
1892 CPU_FOREACH(cs) {
1893 cpu = X86_CPU(cs);
1894
1895 x86_cpu_after_reset(cpu);
1896 }
1897}
1898
1899static void pc_machine_wakeup(MachineState *machine)
1900{
1901 cpu_synchronize_all_states();
1902 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1903 cpu_synchronize_all_post_reset();
1904}
1905
1906static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1907{
1908 X86IOMMUState *iommu = x86_iommu_get_default();
1909 IntelIOMMUState *intel_iommu;
1910
1911 if (iommu &&
1912 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1913 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1914 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1915 if (!intel_iommu->caching_mode) {
1916 error_setg(errp, "Device assignment is not allowed without "
1917 "enabling caching-mode=on for Intel IOMMU.");
1918 return false;
1919 }
1920 }
1921
1922 return true;
1923}
1924
1925static void pc_machine_class_init(ObjectClass *oc, void *data)
1926{
1927 MachineClass *mc = MACHINE_CLASS(oc);
1928 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1929 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1930
1931 pcmc->pci_enabled = true;
1932 pcmc->has_acpi_build = true;
1933 pcmc->rsdp_in_ram = true;
1934 pcmc->smbios_defaults = true;
1935 pcmc->smbios_uuid_encoded = true;
1936 pcmc->gigabyte_align = true;
1937 pcmc->has_reserved_memory = true;
1938 pcmc->kvmclock_enabled = true;
1939 pcmc->enforce_aligned_dimm = true;
1940 pcmc->enforce_amd_1tb_hole = true;
1941
1942
1943 pcmc->acpi_data_size = 0x20000 + 0x8000;
1944 pcmc->pvh_enabled = true;
1945 pcmc->kvmclock_create_always = true;
1946 assert(!mc->get_hotplug_handler);
1947 mc->get_hotplug_handler = pc_get_hotplug_handler;
1948 mc->hotplug_allowed = pc_hotplug_allowed;
1949 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1950 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1951 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1952 mc->auto_enable_numa_with_memhp = true;
1953 mc->auto_enable_numa_with_memdev = true;
1954 mc->has_hotpluggable_cpus = true;
1955 mc->default_boot_order = "cad";
1956 mc->block_default_type = IF_IDE;
1957 mc->max_cpus = 255;
1958 mc->reset = pc_machine_reset;
1959 mc->wakeup = pc_machine_wakeup;
1960 hc->pre_plug = pc_machine_device_pre_plug_cb;
1961 hc->plug = pc_machine_device_plug_cb;
1962 hc->unplug_request = pc_machine_device_unplug_request_cb;
1963 hc->unplug = pc_machine_device_unplug_cb;
1964 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1965 mc->nvdimm_supported = true;
1966 mc->smp_props.dies_supported = true;
1967 mc->default_ram_id = "pc.ram";
1968
1969 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1970 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1971 NULL, NULL);
1972 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1973 "Maximum ram below the 4G boundary (32bit boundary)");
1974
1975 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1976 pc_machine_get_device_memory_region_size, NULL,
1977 NULL, NULL);
1978
1979 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1980 pc_machine_get_vmport, pc_machine_set_vmport,
1981 NULL, NULL);
1982 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1983 "Enable vmport (pc & q35)");
1984
1985 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1986 pc_machine_get_smbus, pc_machine_set_smbus);
1987 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1988 "Enable/disable system management bus");
1989
1990 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1991 pc_machine_get_sata, pc_machine_set_sata);
1992 object_class_property_set_description(oc, PC_MACHINE_SATA,
1993 "Enable/disable Serial ATA bus");
1994
1995 object_class_property_add_bool(oc, "hpet",
1996 pc_machine_get_hpet, pc_machine_set_hpet);
1997 object_class_property_set_description(oc, "hpet",
1998 "Enable/disable high precision event timer emulation");
1999
2000 object_class_property_add_bool(oc, PC_MACHINE_I8042,
2001 pc_machine_get_i8042, pc_machine_set_i8042);
2002
2003 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
2004 pc_machine_get_default_bus_bypass_iommu,
2005 pc_machine_set_default_bus_bypass_iommu);
2006
2007 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
2008 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
2009 NULL, NULL);
2010 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
2011 "Maximum combined firmware size");
2012
2013 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
2014 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
2015 NULL, NULL);
2016 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
2017 "SMBIOS Entry Point type [32, 64]");
2018}
2019
2020static const TypeInfo pc_machine_info = {
2021 .name = TYPE_PC_MACHINE,
2022 .parent = TYPE_X86_MACHINE,
2023 .abstract = true,
2024 .instance_size = sizeof(PCMachineState),
2025 .instance_init = pc_machine_initfn,
2026 .class_size = sizeof(PCMachineClass),
2027 .class_init = pc_machine_class_init,
2028 .interfaces = (InterfaceInfo[]) {
2029 { TYPE_HOTPLUG_HANDLER },
2030 { }
2031 },
2032};
2033
2034static void pc_machine_register_types(void)
2035{
2036 type_register_static(&pc_machine_info);
2037}
2038
2039type_init(pc_machine_register_types)
2040
