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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "qemu/module.h"
23#include "hw/mips/cps.h"
24#include "hw/mips/mips.h"
25#include "hw/qdev-clock.h"
26#include "hw/qdev-properties.h"
27#include "hw/mips/cpudevs.h"
28#include "sysemu/kvm.h"
29#include "sysemu/reset.h"
30
31qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
32{
33 assert(pin_number < s->num_irq);
34 return s->gic.irq_state[pin_number].irq;
35}
36
37static void mips_cps_init(Object *obj)
38{
39 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
40 MIPSCPSState *s = MIPS_CPS(obj);
41
42 s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0);
43
44
45
46
47 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
48 sysbus_init_mmio(sbd, &s->container);
49}
50
51static void main_cpu_reset(void *opaque)
52{
53 MIPSCPU *cpu = opaque;
54 CPUState *cs = CPU(cpu);
55
56 cpu_reset(cs);
57}
58
59static bool cpu_mips_itu_supported(CPUMIPSState *env)
60{
61 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env);
62
63 return is_mt && !kvm_enabled();
64}
65
66static void mips_cps_realize(DeviceState *dev, Error **errp)
67{
68 MIPSCPSState *s = MIPS_CPS(dev);
69 target_ulong gcr_base;
70 bool itu_present = false;
71
72 if (!clock_get(s->clock)) {
73 error_setg(errp, "CPS input clock is not connected to an output clock");
74 return;
75 }
76
77 for (int i = 0; i < s->num_vp; i++) {
78 MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));
79 CPUMIPSState *env = &cpu->env;
80
81
82 if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
83 errp)) {
84 return;
85 }
86
87 qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock);
88
89 if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
90 return;
91 }
92
93
94 cpu_mips_irq_init_cpu(cpu);
95 cpu_mips_clock_init(cpu);
96
97 if (cpu_mips_itu_supported(env)) {
98 itu_present = true;
99
100 env->itc_tag = mips_itu_get_tag_region(&s->itu);
101 env->itu = &s->itu;
102 }
103 qemu_register_reset(main_cpu_reset, cpu);
104 }
105
106
107 if (itu_present) {
108 object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
109 object_property_set_link(OBJECT(&s->itu), "cpu[0]",
110 OBJECT(first_cpu), &error_abort);
111 object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16,
112 &error_abort);
113 object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16,
114 &error_abort);
115 if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
116 return;
117 }
118
119 memory_region_add_subregion(&s->container, 0,
120 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
121 }
122
123
124 object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
125 object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp,
126 &error_abort);
127 object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
128 &error_abort);
129 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
130 return;
131 }
132
133 memory_region_add_subregion(&s->container, 0,
134 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
135
136
137 object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
138 object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp,
139 &error_abort);
140 object_property_set_uint(OBJECT(&s->gic), "num-irq", 128,
141 &error_abort);
142 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
143 return;
144 }
145
146 memory_region_add_subregion(&s->container, 0,
147 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
148
149
150 gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;
151
152 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
153 object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp,
154 &error_abort);
155 object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
156 &error_abort);
157 object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
158 &error_abort);
159 object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
160 &error_abort);
161 object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
162 &error_abort);
163 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
164 return;
165 }
166
167 memory_region_add_subregion(&s->container, gcr_base,
168 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
169}
170
171static Property mips_cps_properties[] = {
172 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
173 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
174 DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
175 DEFINE_PROP_END_OF_LIST()
176};
177
178static void mips_cps_class_init(ObjectClass *klass, void *data)
179{
180 DeviceClass *dc = DEVICE_CLASS(klass);
181
182 dc->realize = mips_cps_realize;
183 device_class_set_props(dc, mips_cps_properties);
184}
185
186static const TypeInfo mips_cps_info = {
187 .name = TYPE_MIPS_CPS,
188 .parent = TYPE_SYS_BUS_DEVICE,
189 .instance_size = sizeof(MIPSCPSState),
190 .instance_init = mips_cps_init,
191 .class_init = mips_cps_class_init,
192};
193
194static void mips_cps_register_types(void)
195{
196 type_register_static(&mips_cps_info);
197}
198
199type_init(mips_cps_register_types)
200
