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18#include "qemu/osdep.h"
19#include "migration/vmstate.h"
20#include "hw/sysbus.h"
21#include "hw/irq.h"
22#include "qemu/timer.h"
23#include "hw/misc/mac_via.h"
24#include "hw/misc/mos6522.h"
25#include "hw/input/adb.h"
26#include "sysemu/runstate.h"
27#include "qapi/error.h"
28#include "qemu/cutils.h"
29#include "hw/qdev-properties.h"
30#include "hw/qdev-properties-system.h"
31#include "sysemu/block-backend.h"
32#include "sysemu/rtc.h"
33#include "trace.h"
34#include "qemu/log.h"
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53#define VIA1A_vSccWrReq 0x80
54
55
56
57
58
59
60
61#define VIA1A_vRev8 0x40
62
63
64
65
66
67
68
69
70
71
72#define VIA1A_vHeadSel 0x20
73
74
75
76
77
78#define VIA1A_vOverlay 0x10
79
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91
92
93#define VIA1A_vSync 0x08
94
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106
107
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109
110
111
112#define VIA1A_vVolume 0x07
113#define VIA1A_CPUID0 0x02
114#define VIA1A_CPUID1 0x04
115#define VIA1A_CPUID2 0x10
116#define VIA1A_CPUID3 0x40
117
118
119
120
121
122#define VIA1B_vSound 0x80
123
124
125
126
127
128#define VIA1B_vMystery 0x40
129
130
131
132
133
134
135
136
137
138#define VIA1B_vADBS2 0x20
139#define VIA1B_vADBS1 0x10
140#define VIA1B_vADBInt 0x08
141#define VIA1B_vRTCEnb 0x04
142#define VIA1B_vRTCClk 0x02
143#define VIA1B_vRTCData 0x01
144
145
146
147
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149
150
151
152
153
154
155#define VIA2A_vRAM1 0x80
156#define VIA2A_vRAM0 0x40
157#define VIA2A_vIRQE 0x20
158#define VIA2A_vIRQD 0x10
159#define VIA2A_vIRQC 0x08
160#define VIA2A_vIRQB 0x04
161#define VIA2A_vIRQA 0x02
162#define VIA2A_vIRQ9 0x01
163
164
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167
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171
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174
175
176
177#define VIA2B_vVBL 0x80
178
179
180
181
182
183#define VIA2B_vSndJck 0x40
184
185
186
187#define VIA2B_vTfr0 0x20
188#define VIA2B_vTfr1 0x10
189#define VIA2B_vMode32 0x08
190
191
192
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194
195
196
197
198#define VIA2B_vPower 0x04
199
200
201
202#define VIA2B_vBusLk 0x02
203
204
205
206#define VIA2B_vCDis 0x01
207
208
209
210
211
212
213
214#define IRQ_SET 0x80
215
216
217
218#define VIA_IRQ_TIMER1 0x40
219#define VIA_IRQ_TIMER2 0x20
220
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235
236
237
238#define vBufB 0x0000
239#define vBufAH 0x0200
240#define vDirB 0x0400
241#define vDirA 0x0600
242#define vT1CL 0x0800
243#define vT1CH 0x0a00
244#define vT1LL 0x0c00
245#define vT1LH 0x0e00
246#define vT2CL 0x1000
247#define vT2CH 0x1200
248#define vSR 0x1400
249#define vACR 0x1600
250#define vPCR 0x1800
251
252
253
254
255
256#define vIFR 0x1a00
257#define vIER 0x1c00
258#define vBufA 0x1e00
259
260
261
262
263
264#define VIA1ACR_vShiftCtrl 0x1c
265#define VIA1ACR_vShiftExtClk 0x0c
266#define VIA1ACR_vShiftOut 0x10
267
268
269
270
271
272
273#define ADB_STATE_NEW 0
274#define ADB_STATE_EVEN 1
275#define ADB_STATE_ODD 2
276#define ADB_STATE_IDLE 3
277
278#define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2)
279#define VIA1B_vADB_StateShift 4
280
281#define VIA_TIMER_FREQ (783360)
282#define VIA_ADB_POLL_FREQ 50
283
284
285
286
287
288#define VIA_60HZ_TIMER_PERIOD_NS 16625800
289
290
291#define RTC_OFFSET 2082844800
292
293enum {
294 REG_0,
295 REG_1,
296 REG_2,
297 REG_3,
298 REG_TEST,
299 REG_WPROTECT,
300 REG_PRAM_ADDR,
301 REG_PRAM_ADDR_LAST = REG_PRAM_ADDR + 19,
302 REG_PRAM_SECT,
303 REG_PRAM_SECT_LAST = REG_PRAM_SECT + 7,
304 REG_INVALID,
305 REG_EMPTY = 0xff,
306};
307
308static void via1_sixty_hz_update(MOS6522Q800VIA1State *v1s)
309{
310
311 v1s->next_sixty_hz = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
312 VIA_60HZ_TIMER_PERIOD_NS) /
313 VIA_60HZ_TIMER_PERIOD_NS * VIA_60HZ_TIMER_PERIOD_NS;
314 timer_mod(v1s->sixty_hz_timer, v1s->next_sixty_hz);
315}
316
317static void via1_one_second_update(MOS6522Q800VIA1State *v1s)
318{
319 v1s->next_second = (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000) /
320 1000 * 1000;
321 timer_mod(v1s->one_second_timer, v1s->next_second);
322}
323
324static void via1_sixty_hz(void *opaque)
325{
326 MOS6522Q800VIA1State *v1s = opaque;
327 MOS6522State *s = MOS6522(v1s);
328 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_60HZ_BIT);
329
330
331 qemu_irq_lower(irq);
332 qemu_irq_raise(irq);
333
334 via1_sixty_hz_update(v1s);
335}
336
337static void via1_one_second(void *opaque)
338{
339 MOS6522Q800VIA1State *v1s = opaque;
340 MOS6522State *s = MOS6522(v1s);
341 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_ONE_SECOND_BIT);
342
343
344 qemu_irq_lower(irq);
345 qemu_irq_raise(irq);
346
347 via1_one_second_update(v1s);
348}
349
350
351static void pram_update(MOS6522Q800VIA1State *v1s)
352{
353 if (v1s->blk) {
354 if (blk_pwrite(v1s->blk, 0, sizeof(v1s->PRAM), v1s->PRAM, 0) < 0) {
355 qemu_log("pram_update: cannot write to file\n");
356 }
357 }
358}
359
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377
378
379static int via1_rtc_compact_cmd(uint8_t value)
380{
381 uint8_t read = value & 0x80;
382
383 value &= 0x7f;
384
385
386 if ((value & 0x78) == 0x38) {
387
388 return read | (REG_PRAM_SECT + (value & 0x07));
389 }
390 if ((value & 0x03) == 0x01) {
391 value >>= 2;
392 if ((value & 0x1c) == 0) {
393
394 return read | (REG_0 + (value & 0x03));
395 } else if ((value == 0x0c) && !read) {
396 return REG_TEST;
397 } else if ((value == 0x0d) && !read) {
398 return REG_WPROTECT;
399 } else if ((value & 0x1c) == 0x08) {
400
401 return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03));
402 } else if ((value & 0x43) == 0x41) {
403
404 return read | (REG_PRAM_ADDR + (value & 0x0f));
405 }
406 }
407 return REG_INVALID;
408}
409
410static void via1_rtc_update(MOS6522Q800VIA1State *v1s)
411{
412 MOS6522State *s = MOS6522(v1s);
413 int cmd, sector, addr;
414 uint32_t time;
415
416 if (s->b & VIA1B_vRTCEnb) {
417 return;
418 }
419
420 if (s->dirb & VIA1B_vRTCData) {
421
422 if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) {
423 v1s->data_out <<= 1;
424 v1s->data_out |= s->b & VIA1B_vRTCData;
425 v1s->data_out_cnt++;
426 }
427 trace_via1_rtc_update_data_out(v1s->data_out_cnt, v1s->data_out);
428 } else {
429 trace_via1_rtc_update_data_in(v1s->data_in_cnt, v1s->data_in);
430
431 if ((v1s->last_b & VIA1B_vRTCClk) &&
432 !(s->b & VIA1B_vRTCClk) &&
433 v1s->data_in_cnt) {
434 s->b = (s->b & ~VIA1B_vRTCData) |
435 ((v1s->data_in >> 7) & VIA1B_vRTCData);
436 v1s->data_in <<= 1;
437 v1s->data_in_cnt--;
438 }
439 return;
440 }
441
442 if (v1s->data_out_cnt != 8) {
443 return;
444 }
445
446 v1s->data_out_cnt = 0;
447
448 trace_via1_rtc_internal_status(v1s->cmd, v1s->alt, v1s->data_out);
449
450 if (v1s->cmd == REG_EMPTY) {
451
452 cmd = via1_rtc_compact_cmd(v1s->data_out);
453 trace_via1_rtc_internal_cmd(cmd);
454
455 if (cmd == REG_INVALID) {
456 trace_via1_rtc_cmd_invalid(v1s->data_out);
457 return;
458 }
459
460 if (cmd & 0x80) {
461 switch (cmd & 0x7f) {
462 case REG_0...REG_3:
463
464
465
466
467
468 time = v1s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
469 / NANOSECONDS_PER_SECOND);
470 trace_via1_rtc_internal_time(time);
471 v1s->data_in = (time >> ((cmd & 0x03) << 3)) & 0xff;
472 v1s->data_in_cnt = 8;
473 trace_via1_rtc_cmd_seconds_read((cmd & 0x7f) - REG_0,
474 v1s->data_in);
475 break;
476 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST:
477
478 v1s->data_in = v1s->PRAM[(cmd & 0x7f) - REG_PRAM_ADDR];
479 v1s->data_in_cnt = 8;
480 trace_via1_rtc_cmd_pram_read((cmd & 0x7f) - REG_PRAM_ADDR,
481 v1s->data_in);
482 break;
483 case REG_PRAM_SECT...REG_PRAM_SECT_LAST:
484
485
486
487
488 trace_via1_rtc_internal_set_cmd(cmd);
489 v1s->cmd = cmd;
490 break;
491 default:
492 g_assert_not_reached();
493 break;
494 }
495 return;
496 }
497
498
499 if (cmd == REG_WPROTECT || !v1s->wprotect) {
500 trace_via1_rtc_internal_set_cmd(cmd);
501 v1s->cmd = cmd;
502 } else {
503 trace_via1_rtc_internal_ignore_cmd(cmd);
504 }
505 return;
506 }
507
508
509 if (v1s->alt == REG_EMPTY) {
510 switch (v1s->cmd & 0x7f) {
511 case REG_0...REG_3:
512
513 trace_via1_rtc_cmd_seconds_write(v1s->cmd - REG_0, v1s->data_out);
514 v1s->cmd = REG_EMPTY;
515 break;
516 case REG_TEST:
517
518 trace_via1_rtc_cmd_test_write(v1s->data_out);
519 v1s->cmd = REG_EMPTY;
520 break;
521 case REG_WPROTECT:
522
523 trace_via1_rtc_cmd_wprotect_write(v1s->data_out);
524 v1s->wprotect = !!(v1s->data_out & 0x80);
525 v1s->cmd = REG_EMPTY;
526 break;
527 case REG_PRAM_ADDR...REG_PRAM_ADDR_LAST:
528
529 trace_via1_rtc_cmd_pram_write(v1s->cmd - REG_PRAM_ADDR,
530 v1s->data_out);
531 v1s->PRAM[v1s->cmd - REG_PRAM_ADDR] = v1s->data_out;
532 pram_update(v1s);
533 v1s->cmd = REG_EMPTY;
534 break;
535 case REG_PRAM_SECT...REG_PRAM_SECT_LAST:
536 addr = (v1s->data_out >> 2) & 0x1f;
537 sector = (v1s->cmd & 0x7f) - REG_PRAM_SECT;
538 if (v1s->cmd & 0x80) {
539
540 v1s->data_in = v1s->PRAM[sector * 32 + addr];
541 v1s->data_in_cnt = 8;
542 trace_via1_rtc_cmd_pram_sect_read(sector, addr,
543 sector * 32 + addr,
544 v1s->data_in);
545 v1s->cmd = REG_EMPTY;
546 } else {
547
548 trace_via1_rtc_internal_set_alt(addr, sector, addr);
549 v1s->alt = addr;
550 }
551 break;
552 default:
553 g_assert_not_reached();
554 break;
555 }
556 return;
557 }
558
559
560 g_assert(REG_PRAM_SECT <= v1s->cmd && v1s->cmd <= REG_PRAM_SECT_LAST);
561 sector = v1s->cmd - REG_PRAM_SECT;
562 v1s->PRAM[sector * 32 + v1s->alt] = v1s->data_out;
563 pram_update(v1s);
564 trace_via1_rtc_cmd_pram_sect_write(sector, v1s->alt, sector * 32 + v1s->alt,
565 v1s->data_out);
566 v1s->alt = REG_EMPTY;
567 v1s->cmd = REG_EMPTY;
568}
569
570static void adb_via_poll(void *opaque)
571{
572 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque);
573 MOS6522State *s = MOS6522(v1s);
574 ADBBusState *adb_bus = &v1s->adb_bus;
575 uint8_t obuf[9];
576 uint8_t *data = &s->sr;
577 int olen;
578
579
580
581
582
583
584 adb_autopoll_block(adb_bus);
585
586 if (v1s->adb_data_in_size > 0 && v1s->adb_data_in_index == 0) {
587
588
589
590
591
592 *data = v1s->adb_data_out[0];
593 olen = v1s->adb_data_in_size;
594
595 s->b &= ~VIA1B_vADBInt;
596 qemu_irq_raise(v1s->adb_data_ready);
597 } else {
598
599
600
601 v1s->adb_data_in_index = 0;
602 v1s->adb_data_out_index = 0;
603 olen = adb_poll(adb_bus, obuf, adb_bus->autopoll_mask);
604
605 if (olen > 0) {
606
607 *data = obuf[0];
608 olen--;
609 memcpy(v1s->adb_data_in, &obuf[1], olen);
610 v1s->adb_data_in_size = olen;
611
612 s->b &= ~VIA1B_vADBInt;
613 qemu_irq_raise(v1s->adb_data_ready);
614 } else {
615 *data = v1s->adb_autopoll_cmd;
616 obuf[0] = 0xff;
617 obuf[1] = 0xff;
618 olen = 2;
619
620 memcpy(v1s->adb_data_in, obuf, olen);
621 v1s->adb_data_in_size = olen;
622
623 s->b &= ~VIA1B_vADBInt;
624 qemu_irq_raise(v1s->adb_data_ready);
625 }
626 }
627
628 trace_via1_adb_poll(*data, (s->b & VIA1B_vADBInt) ? "+" : "-",
629 adb_bus->status, v1s->adb_data_in_index, olen);
630}
631
632static int adb_via_send_len(uint8_t data)
633{
634
635 uint8_t cmd = data & 0xc;
636 uint8_t reg = data & 0x3;
637
638 switch (cmd) {
639 case 0x8:
640
641 switch (reg) {
642 case 2:
643
644 return 3;
645 case 3:
646
647
648
649
650 return 3;
651 default:
652 qemu_log_mask(LOG_UNIMP, "ADB unknown length for register %d\n",
653 reg);
654 return 1;
655 }
656 default:
657
658 return 1;
659 }
660}
661
662static void adb_via_send(MOS6522Q800VIA1State *v1s, int state, uint8_t data)
663{
664 MOS6522State *ms = MOS6522(v1s);
665 ADBBusState *adb_bus = &v1s->adb_bus;
666 uint16_t autopoll_mask;
667
668 switch (state) {
669 case ADB_STATE_NEW:
670
671
672
673
674 adb_autopoll_block(adb_bus);
675
676 if (adb_bus->status & ADB_STATUS_POLLREPLY) {
677
678 ms->b &= ~VIA1B_vADBInt;
679 } else {
680 ms->b |= VIA1B_vADBInt;
681 v1s->adb_data_out_index = 0;
682 v1s->adb_data_out[v1s->adb_data_out_index++] = data;
683 }
684
685 trace_via1_adb_send(" NEW", data, (ms->b & VIA1B_vADBInt) ? "+" : "-");
686 qemu_irq_raise(v1s->adb_data_ready);
687 break;
688
689 case ADB_STATE_EVEN:
690 case ADB_STATE_ODD:
691 ms->b |= VIA1B_vADBInt;
692 v1s->adb_data_out[v1s->adb_data_out_index++] = data;
693
694 trace_via1_adb_send(state == ADB_STATE_EVEN ? "EVEN" : " ODD",
695 data, (ms->b & VIA1B_vADBInt) ? "+" : "-");
696 qemu_irq_raise(v1s->adb_data_ready);
697 break;
698
699 case ADB_STATE_IDLE:
700 return;
701 }
702
703
704 if (v1s->adb_data_out_index == adb_via_send_len(v1s->adb_data_out[0])) {
705 v1s->adb_data_in_size = adb_request(adb_bus, v1s->adb_data_in,
706 v1s->adb_data_out,
707 v1s->adb_data_out_index);
708 v1s->adb_data_in_index = 0;
709
710 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) {
711
712
713
714
715 v1s->adb_data_in[0] = 0xff;
716 v1s->adb_data_in[1] = 0xff;
717 v1s->adb_data_in_size = 2;
718 }
719
720
721
722
723
724 if ((v1s->adb_data_out[0] & 0xc) == 0xc) {
725 v1s->adb_autopoll_cmd = v1s->adb_data_out[0];
726
727 autopoll_mask = 1 << (v1s->adb_autopoll_cmd >> 4);
728 adb_set_autopoll_mask(adb_bus, autopoll_mask);
729 }
730 }
731}
732
733static void adb_via_receive(MOS6522Q800VIA1State *v1s, int state, uint8_t *data)
734{
735 MOS6522State *ms = MOS6522(v1s);
736 ADBBusState *adb_bus = &v1s->adb_bus;
737 uint16_t pending;
738
739 switch (state) {
740 case ADB_STATE_NEW:
741 ms->b |= VIA1B_vADBInt;
742 return;
743
744 case ADB_STATE_IDLE:
745 ms->b |= VIA1B_vADBInt;
746 adb_autopoll_unblock(adb_bus);
747
748 trace_via1_adb_receive("IDLE", *data,
749 (ms->b & VIA1B_vADBInt) ? "+" : "-", adb_bus->status,
750 v1s->adb_data_in_index, v1s->adb_data_in_size);
751
752 break;
753
754 case ADB_STATE_EVEN:
755 case ADB_STATE_ODD:
756 switch (v1s->adb_data_in_index) {
757 case 0:
758
759 *data = v1s->adb_data_in[v1s->adb_data_in_index];
760 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) {
761 ms->b &= ~VIA1B_vADBInt;
762 } else {
763 ms->b |= VIA1B_vADBInt;
764 }
765
766 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD",
767 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-",
768 adb_bus->status, v1s->adb_data_in_index,
769 v1s->adb_data_in_size);
770
771 v1s->adb_data_in_index++;
772 break;
773
774 case 1:
775
776 *data = v1s->adb_data_in[v1s->adb_data_in_index];
777 pending = adb_bus->pending & ~(1 << (v1s->adb_autopoll_cmd >> 4));
778 if (pending) {
779 ms->b &= ~VIA1B_vADBInt;
780 } else {
781 ms->b |= VIA1B_vADBInt;
782 }
783
784 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD",
785 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-",
786 adb_bus->status, v1s->adb_data_in_index,
787 v1s->adb_data_in_size);
788
789 v1s->adb_data_in_index++;
790 break;
791
792 default:
793
794
795
796
797
798
799 if (v1s->adb_data_in_index < v1s->adb_data_in_size) {
800
801 *data = v1s->adb_data_in[v1s->adb_data_in_index];
802 ms->b |= VIA1B_vADBInt;
803 } else if (v1s->adb_data_in_index == v1s->adb_data_in_size) {
804 if (adb_bus->status & ADB_STATUS_BUSTIMEOUT) {
805
806 *data = 0xff;
807 } else {
808
809 *data = 0;
810 }
811 ms->b &= ~VIA1B_vADBInt;
812 } else {
813
814 *data = 0xff;
815 ms->b &= ~VIA1B_vADBInt;
816 adb_bus->status = 0;
817 adb_autopoll_unblock(adb_bus);
818 }
819
820 trace_via1_adb_receive(state == ADB_STATE_EVEN ? "EVEN" : " ODD",
821 *data, (ms->b & VIA1B_vADBInt) ? "+" : "-",
822 adb_bus->status, v1s->adb_data_in_index,
823 v1s->adb_data_in_size);
824
825 if (v1s->adb_data_in_index <= v1s->adb_data_in_size) {
826 v1s->adb_data_in_index++;
827 }
828 break;
829 }
830
831 qemu_irq_raise(v1s->adb_data_ready);
832 break;
833 }
834}
835
836static void via1_adb_update(MOS6522Q800VIA1State *v1s)
837{
838 MOS6522State *s = MOS6522(v1s);
839 int oldstate, state;
840
841 oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift;
842 state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift;
843
844 if (state != oldstate) {
845 if (s->acr & VIA1ACR_vShiftOut) {
846
847 adb_via_send(v1s, state, s->sr);
848 } else {
849
850 adb_via_receive(v1s, state, &s->sr);
851 }
852 }
853}
854
855static void via1_auxmode_update(MOS6522Q800VIA1State *v1s)
856{
857 MOS6522State *s = MOS6522(v1s);
858 int oldirq, irq;
859
860 oldirq = (v1s->last_b & VIA1B_vMystery) ? 1 : 0;
861 irq = (s->b & VIA1B_vMystery) ? 1 : 0;
862
863
864 if (irq != oldirq) {
865 trace_via1_auxmode(irq);
866 qemu_set_irq(v1s->auxmode_irq, irq);
867 }
868}
869
870static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
871{
872 MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque);
873 MOS6522State *ms = MOS6522(s);
874
875 addr = (addr >> 9) & 0xf;
876 return mos6522_read(ms, addr, size);
877}
878
879static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val,
880 unsigned size)
881{
882 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque);
883 MOS6522State *ms = MOS6522(v1s);
884
885 addr = (addr >> 9) & 0xf;
886 mos6522_write(ms, addr, val, size);
887
888 switch (addr) {
889 case VIA_REG_B:
890 via1_rtc_update(v1s);
891 via1_adb_update(v1s);
892 via1_auxmode_update(v1s);
893
894 v1s->last_b = ms->b;
895 break;
896 }
897}
898
899static const MemoryRegionOps mos6522_q800_via1_ops = {
900 .read = mos6522_q800_via1_read,
901 .write = mos6522_q800_via1_write,
902 .endianness = DEVICE_BIG_ENDIAN,
903 .valid = {
904 .min_access_size = 1,
905 .max_access_size = 4,
906 },
907};
908
909static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size)
910{
911 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque);
912 MOS6522State *ms = MOS6522(s);
913 uint64_t val;
914
915 addr = (addr >> 9) & 0xf;
916 val = mos6522_read(ms, addr, size);
917
918 switch (addr) {
919 case VIA_REG_IFR:
920
921
922
923
924
925
926
927 val &= ~VIA2_IRQ_SCSI_DATA;
928 val |= (~ms->last_irq_levels & VIA2_IRQ_SCSI_DATA);
929 break;
930 }
931
932 return val;
933}
934
935static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val,
936 unsigned size)
937{
938 MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque);
939 MOS6522State *ms = MOS6522(s);
940
941 addr = (addr >> 9) & 0xf;
942 mos6522_write(ms, addr, val, size);
943}
944
945static const MemoryRegionOps mos6522_q800_via2_ops = {
946 .read = mos6522_q800_via2_read,
947 .write = mos6522_q800_via2_write,
948 .endianness = DEVICE_BIG_ENDIAN,
949 .valid = {
950 .min_access_size = 1,
951 .max_access_size = 4,
952 },
953};
954
955static void via1_postload_update_cb(void *opaque, bool running, RunState state)
956{
957 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque);
958
959 qemu_del_vm_change_state_handler(v1s->vmstate);
960 v1s->vmstate = NULL;
961
962 pram_update(v1s);
963}
964
965static int via1_post_load(void *opaque, int version_id)
966{
967 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque);
968
969 if (v1s->blk) {
970 v1s->vmstate = qemu_add_vm_change_state_handler(
971 via1_postload_update_cb, v1s);
972 }
973
974 return 0;
975}
976
977
978static void mos6522_q800_via1_reset_hold(Object *obj)
979{
980 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj);
981 MOS6522State *ms = MOS6522(v1s);
982 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
983 ADBBusState *adb_bus = &v1s->adb_bus;
984
985 if (mdc->parent_phases.hold) {
986 mdc->parent_phases.hold(obj);
987 }
988
989 ms->timers[0].frequency = VIA_TIMER_FREQ;
990 ms->timers[1].frequency = VIA_TIMER_FREQ;
991
992 ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb;
993
994
995 adb_set_autopoll_enabled(adb_bus, true);
996 v1s->cmd = REG_EMPTY;
997 v1s->alt = REG_EMPTY;
998}
999
1000static void mos6522_q800_via1_realize(DeviceState *dev, Error **errp)
1001{
1002 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(dev);
1003 ADBBusState *adb_bus = &v1s->adb_bus;
1004 struct tm tm;
1005 int ret;
1006
1007 v1s->one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, via1_one_second,
1008 v1s);
1009 via1_one_second_update(v1s);
1010 v1s->sixty_hz_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, via1_sixty_hz,
1011 v1s);
1012 via1_sixty_hz_update(v1s);
1013
1014 qemu_get_timedate(&tm, 0);
1015 v1s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
1016
1017 adb_register_autopoll_callback(adb_bus, adb_via_poll, v1s);
1018 v1s->adb_data_ready = qdev_get_gpio_in(dev, VIA1_IRQ_ADB_READY_BIT);
1019
1020 if (v1s->blk) {
1021 int64_t len = blk_getlength(v1s->blk);
1022 if (len < 0) {
1023 error_setg_errno(errp, -len,
1024 "could not get length of backing image");
1025 return;
1026 }
1027 ret = blk_set_perm(v1s->blk,
1028 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
1029 BLK_PERM_ALL, errp);
1030 if (ret < 0) {
1031 return;
1032 }
1033
1034 ret = blk_pread(v1s->blk, 0, sizeof(v1s->PRAM), v1s->PRAM, 0);
1035 if (ret < 0) {
1036 error_setg(errp, "can't read PRAM contents");
1037 return;
1038 }
1039 }
1040}
1041
1042static void mos6522_q800_via1_init(Object *obj)
1043{
1044 MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj);
1045 SysBusDevice *sbd = SYS_BUS_DEVICE(v1s);
1046
1047 memory_region_init_io(&v1s->via_mem, obj, &mos6522_q800_via1_ops, v1s,
1048 "via1", VIA_SIZE);
1049 sysbus_init_mmio(sbd, &v1s->via_mem);
1050
1051
1052 qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
1053 TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
1054
1055
1056 qdev_init_gpio_out(DEVICE(obj), &v1s->auxmode_irq, 1);
1057}
1058
1059static const VMStateDescription vmstate_q800_via1 = {
1060 .name = "q800-via1",
1061 .version_id = 0,
1062 .minimum_version_id = 0,
1063 .post_load = via1_post_load,
1064 .fields = (VMStateField[]) {
1065 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA1State, 0, vmstate_mos6522,
1066 MOS6522State),
1067 VMSTATE_UINT8(last_b, MOS6522Q800VIA1State),
1068
1069 VMSTATE_BUFFER(PRAM, MOS6522Q800VIA1State),
1070 VMSTATE_UINT32(tick_offset, MOS6522Q800VIA1State),
1071 VMSTATE_UINT8(data_out, MOS6522Q800VIA1State),
1072 VMSTATE_INT32(data_out_cnt, MOS6522Q800VIA1State),
1073 VMSTATE_UINT8(data_in, MOS6522Q800VIA1State),
1074 VMSTATE_UINT8(data_in_cnt, MOS6522Q800VIA1State),
1075 VMSTATE_UINT8(cmd, MOS6522Q800VIA1State),
1076 VMSTATE_INT32(wprotect, MOS6522Q800VIA1State),
1077 VMSTATE_INT32(alt, MOS6522Q800VIA1State),
1078
1079 VMSTATE_INT32(adb_data_in_size, MOS6522Q800VIA1State),
1080 VMSTATE_INT32(adb_data_in_index, MOS6522Q800VIA1State),
1081 VMSTATE_INT32(adb_data_out_index, MOS6522Q800VIA1State),
1082 VMSTATE_BUFFER(adb_data_in, MOS6522Q800VIA1State),
1083 VMSTATE_BUFFER(adb_data_out, MOS6522Q800VIA1State),
1084 VMSTATE_UINT8(adb_autopoll_cmd, MOS6522Q800VIA1State),
1085
1086 VMSTATE_TIMER_PTR(one_second_timer, MOS6522Q800VIA1State),
1087 VMSTATE_INT64(next_second, MOS6522Q800VIA1State),
1088 VMSTATE_TIMER_PTR(sixty_hz_timer, MOS6522Q800VIA1State),
1089 VMSTATE_INT64(next_sixty_hz, MOS6522Q800VIA1State),
1090 VMSTATE_END_OF_LIST()
1091 }
1092};
1093
1094static Property mos6522_q800_via1_properties[] = {
1095 DEFINE_PROP_DRIVE("drive", MOS6522Q800VIA1State, blk),
1096 DEFINE_PROP_END_OF_LIST(),
1097};
1098
1099static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data)
1100{
1101 DeviceClass *dc = DEVICE_CLASS(oc);
1102 ResettableClass *rc = RESETTABLE_CLASS(oc);
1103 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
1104
1105 dc->realize = mos6522_q800_via1_realize;
1106 resettable_class_set_parent_phases(rc, NULL, mos6522_q800_via1_reset_hold,
1107 NULL, &mdc->parent_phases);
1108 dc->vmsd = &vmstate_q800_via1;
1109 device_class_set_props(dc, mos6522_q800_via1_properties);
1110}
1111
1112static const TypeInfo mos6522_q800_via1_type_info = {
1113 .name = TYPE_MOS6522_Q800_VIA1,
1114 .parent = TYPE_MOS6522,
1115 .instance_size = sizeof(MOS6522Q800VIA1State),
1116 .instance_init = mos6522_q800_via1_init,
1117 .class_init = mos6522_q800_via1_class_init,
1118};
1119
1120
1121static void mos6522_q800_via2_portB_write(MOS6522State *s)
1122{
1123 if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) {
1124
1125 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
1126 }
1127}
1128
1129static void mos6522_q800_via2_reset_hold(Object *obj)
1130{
1131 MOS6522State *ms = MOS6522(obj);
1132 MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
1133
1134 if (mdc->parent_phases.hold) {
1135 mdc->parent_phases.hold(obj);
1136 }
1137
1138 ms->timers[0].frequency = VIA_TIMER_FREQ;
1139 ms->timers[1].frequency = VIA_TIMER_FREQ;
1140
1141 ms->dirb = 0;
1142 ms->b = 0;
1143 ms->dira = 0;
1144 ms->a = 0x7f;
1145}
1146
1147static void via2_nubus_irq_request(void *opaque, int n, int level)
1148{
1149 MOS6522Q800VIA2State *v2s = opaque;
1150 MOS6522State *s = MOS6522(v2s);
1151 qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA2_IRQ_NUBUS_BIT);
1152
1153 if (level) {
1154
1155 s->a &= ~(1 << n);
1156 } else {
1157 s->a |= (1 << n);
1158 }
1159
1160
1161 qemu_set_irq(irq, !level);
1162}
1163
1164static void mos6522_q800_via2_init(Object *obj)
1165{
1166 MOS6522Q800VIA2State *v2s = MOS6522_Q800_VIA2(obj);
1167 SysBusDevice *sbd = SYS_BUS_DEVICE(v2s);
1168
1169 memory_region_init_io(&v2s->via_mem, obj, &mos6522_q800_via2_ops, v2s,
1170 "via2", VIA_SIZE);
1171 sysbus_init_mmio(sbd, &v2s->via_mem);
1172
1173 qdev_init_gpio_in_named(DEVICE(obj), via2_nubus_irq_request, "nubus-irq",
1174 VIA2_NUBUS_IRQ_NB);
1175}
1176
1177static const VMStateDescription vmstate_q800_via2 = {
1178 .name = "q800-via2",
1179 .version_id = 0,
1180 .minimum_version_id = 0,
1181 .fields = (VMStateField[]) {
1182 VMSTATE_STRUCT(parent_obj, MOS6522Q800VIA2State, 0, vmstate_mos6522,
1183 MOS6522State),
1184 VMSTATE_END_OF_LIST()
1185 }
1186};
1187
1188static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data)
1189{
1190 DeviceClass *dc = DEVICE_CLASS(oc);
1191 ResettableClass *rc = RESETTABLE_CLASS(oc);
1192 MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
1193
1194 resettable_class_set_parent_phases(rc, NULL, mos6522_q800_via2_reset_hold,
1195 NULL, &mdc->parent_phases);
1196 dc->vmsd = &vmstate_q800_via2;
1197 mdc->portB_write = mos6522_q800_via2_portB_write;
1198}
1199
1200static const TypeInfo mos6522_q800_via2_type_info = {
1201 .name = TYPE_MOS6522_Q800_VIA2,
1202 .parent = TYPE_MOS6522,
1203 .instance_size = sizeof(MOS6522Q800VIA2State),
1204 .instance_init = mos6522_q800_via2_init,
1205 .class_init = mos6522_q800_via2_class_init,
1206};
1207
1208static void mac_via_register_types(void)
1209{
1210 type_register_static(&mos6522_q800_via1_type_info);
1211 type_register_static(&mos6522_q800_via2_type_info);
1212}
1213
1214type_init(mac_via_register_types);
1215