LXR qemu/include/hw/pci-host/designware.h

   1/*
   2 * Copyright (c) 2017, Impinj, Inc.
   3 *
   4 * Designware PCIe IP block emulation
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef DESIGNWARE_H
  22#define DESIGNWARE_H
  23
  24#include "hw/sysbus.h"
  25#include "hw/pci/pci_bridge.h"
  26#include "qom/object.h"
  27
  28#define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
  29OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST)
  30
  31#define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
  32OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT)
  33
  34struct DesignwarePCIERoot;
  35
  36typedef struct DesignwarePCIEViewport {
  37    DesignwarePCIERoot *root;
  38
  39    MemoryRegion cfg;
  40    MemoryRegion mem;
  41
  42    uint64_t base;
  43    uint64_t target;
  44    uint32_t limit;
  45    uint32_t cr[2];
  46
  47    bool inbound;
  48} DesignwarePCIEViewport;
  49
  50typedef struct DesignwarePCIEMSIBank {
  51    uint32_t enable;
  52    uint32_t mask;
  53    uint32_t status;
  54} DesignwarePCIEMSIBank;
  55
  56typedef struct DesignwarePCIEMSI {
  57    uint64_t     base;
  58    MemoryRegion iomem;
  59
  60#define DESIGNWARE_PCIE_NUM_MSI_BANKS        1
  61
  62    DesignwarePCIEMSIBank intr[DESIGNWARE_PCIE_NUM_MSI_BANKS];
  63} DesignwarePCIEMSI;
  64
  65struct DesignwarePCIERoot {
  66    PCIBridge parent_obj;
  67
  68    uint32_t atu_viewport;
  69
  70#define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND    0
  71#define DESIGNWARE_PCIE_VIEWPORT_INBOUND     1
  72#define DESIGNWARE_PCIE_NUM_VIEWPORTS        4
  73
  74    DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS];
  75    DesignwarePCIEMSI msi;
  76};
  77
  78struct DesignwarePCIEHost {
  79    PCIHostState parent_obj;
  80
  81    DesignwarePCIERoot root;
  82
  83    struct {
  84        AddressSpace address_space;
  85        MemoryRegion address_space_root;
  86
  87        MemoryRegion memory;
  88        MemoryRegion io;
  89
  90        qemu_irq     irqs[4];
  91    } pci;
  92
  93    MemoryRegion mmio;
  94};
  95
  96#endif /* DESIGNWARE_H */
  97