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20#include "qemu/osdep.h"
21#include "qemu/error-report.h"
22#include "qemu/log.h"
23#include "qemu/module.h"
24#include "sysemu/kvm.h"
25#include "kvm_ppc.h"
26#include "migration/vmstate.h"
27#include "sysemu/dma.h"
28#include "trace.h"
29
30#include "hw/ppc/spapr.h"
31#include "hw/ppc/spapr_vio.h"
32
33#include <libfdt.h>
34
35enum SpaprTceAccess {
36 SPAPR_TCE_FAULT = 0,
37 SPAPR_TCE_RO = 1,
38 SPAPR_TCE_WO = 2,
39 SPAPR_TCE_RW = 3,
40};
41
42#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
43#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
44
45static QLIST_HEAD(, SpaprTceTable) spapr_tce_tables;
46
47SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn)
48{
49 SpaprTceTable *tcet;
50
51 if (liobn & 0xFFFFFFFF00000000ULL) {
52 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
53 liobn);
54 return NULL;
55 }
56
57 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
58 if (tcet->liobn == (uint32_t)liobn) {
59 return tcet;
60 }
61 }
62
63 return NULL;
64}
65
66static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
67{
68 switch (tce & SPAPR_TCE_RW) {
69 case SPAPR_TCE_FAULT:
70 return IOMMU_NONE;
71 case SPAPR_TCE_RO:
72 return IOMMU_RO;
73 case SPAPR_TCE_WO:
74 return IOMMU_WO;
75 default:
76 return IOMMU_RW;
77 }
78}
79
80static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
81 uint32_t page_shift,
82 uint64_t bus_offset,
83 uint32_t nb_table,
84 int *fd,
85 bool need_vfio)
86{
87 uint64_t *table = NULL;
88
89 if (kvm_enabled()) {
90 table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
91 fd, need_vfio);
92 }
93
94 if (!table) {
95 *fd = -1;
96 table = g_new0(uint64_t, nb_table);
97 }
98
99 trace_spapr_iommu_new_table(liobn, table, *fd);
100
101 return table;
102}
103
104static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
105{
106 if (!kvm_enabled() ||
107 (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
108 g_free(table);
109 }
110}
111
112
113static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
114 hwaddr addr,
115 IOMMUAccessFlags flag,
116 int iommu_idx)
117{
118 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
119 uint64_t tce;
120 IOMMUTLBEntry ret = {
121 .target_as = &address_space_memory,
122 .iova = 0,
123 .translated_addr = 0,
124 .addr_mask = ~(hwaddr)0,
125 .perm = IOMMU_NONE,
126 };
127
128 if ((addr >> tcet->page_shift) < tcet->nb_table) {
129
130 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
131
132 tce = tcet->table[addr >> tcet->page_shift];
133 ret.iova = addr & page_mask;
134 ret.translated_addr = tce & page_mask;
135 ret.addr_mask = ~page_mask;
136 ret.perm = spapr_tce_iommu_access_flags(tce);
137 }
138 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.translated_addr, ret.perm,
139 ret.addr_mask);
140
141 return ret;
142}
143
144static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
145{
146 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
147 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
148 hwaddr addr, granularity;
149 IOMMUTLBEntry iotlb;
150 SpaprTceTable *tcet = container_of(iommu_mr, SpaprTceTable, iommu);
151
152 if (tcet->skipping_replay) {
153 return;
154 }
155
156 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
157
158 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
159 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
160 if (iotlb.perm != IOMMU_NONE) {
161 n->notify(n, &iotlb);
162 }
163
164
165
166
167
168 if ((addr + granularity) < addr) {
169 break;
170 }
171 }
172}
173
174static int spapr_tce_table_pre_save(void *opaque)
175{
176 SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
177
178 tcet->mig_table = tcet->table;
179 tcet->mig_nb_table = tcet->nb_table;
180
181 trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
182 tcet->bus_offset, tcet->page_shift);
183
184 return 0;
185}
186
187static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu)
188{
189 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
190
191 return 1ULL << tcet->page_shift;
192}
193
194static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu,
195 enum IOMMUMemoryRegionAttr attr, void *data)
196{
197 SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
198
199 if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) {
200 *(int *) data = tcet->fd;
201 return 0;
202 }
203
204 return -EINVAL;
205}
206
207static int spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu,
208 IOMMUNotifierFlag old,
209 IOMMUNotifierFlag new,
210 Error **errp)
211{
212 struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu);
213
214 if (new & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) {
215 error_setg(errp, "spart_tce does not support dev-iotlb yet");
216 return -EINVAL;
217 }
218
219 if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
220 spapr_tce_set_need_vfio(tbl, true);
221 } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
222 spapr_tce_set_need_vfio(tbl, false);
223 }
224 return 0;
225}
226
227static int spapr_tce_table_post_load(void *opaque, int version_id)
228{
229 SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
230 uint32_t old_nb_table = tcet->nb_table;
231 uint64_t old_bus_offset = tcet->bus_offset;
232 uint32_t old_page_shift = tcet->page_shift;
233
234 if (tcet->vdev) {
235 spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
236 }
237
238 if (tcet->mig_nb_table != tcet->nb_table) {
239 spapr_tce_table_disable(tcet);
240 }
241
242 if (tcet->mig_nb_table) {
243 if (!tcet->nb_table) {
244 spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
245 tcet->mig_nb_table);
246 }
247
248 memcpy(tcet->table, tcet->mig_table,
249 tcet->nb_table * sizeof(tcet->table[0]));
250
251 free(tcet->mig_table);
252 tcet->mig_table = NULL;
253 }
254
255 trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
256 tcet->bus_offset, tcet->page_shift);
257
258 return 0;
259}
260
261static bool spapr_tce_table_ex_needed(void *opaque)
262{
263 SpaprTceTable *tcet = opaque;
264
265 return tcet->bus_offset || tcet->page_shift != 0xC;
266}
267
268static const VMStateDescription vmstate_spapr_tce_table_ex = {
269 .name = "spapr_iommu_ex",
270 .version_id = 1,
271 .minimum_version_id = 1,
272 .needed = spapr_tce_table_ex_needed,
273 .fields = (VMStateField[]) {
274 VMSTATE_UINT64(bus_offset, SpaprTceTable),
275 VMSTATE_UINT32(page_shift, SpaprTceTable),
276 VMSTATE_END_OF_LIST()
277 },
278};
279
280static const VMStateDescription vmstate_spapr_tce_table = {
281 .name = "spapr_iommu",
282 .version_id = 3,
283 .minimum_version_id = 2,
284 .pre_save = spapr_tce_table_pre_save,
285 .post_load = spapr_tce_table_post_load,
286 .fields = (VMStateField []) {
287
288 VMSTATE_UINT32_EQUAL(liobn, SpaprTceTable, NULL),
289
290
291 VMSTATE_UINT32(mig_nb_table, SpaprTceTable),
292 VMSTATE_BOOL(bypass, SpaprTceTable),
293 VMSTATE_VARRAY_UINT32_ALLOC(mig_table, SpaprTceTable, mig_nb_table, 0,
294 vmstate_info_uint64, uint64_t),
295 VMSTATE_BOOL_V(def_win, SpaprTceTable, 3),
296
297 VMSTATE_END_OF_LIST()
298 },
299 .subsections = (const VMStateDescription*[]) {
300 &vmstate_spapr_tce_table_ex,
301 NULL
302 }
303};
304
305static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
306{
307 SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
308 Object *tcetobj = OBJECT(tcet);
309 gchar *tmp;
310
311 tcet->fd = -1;
312 tcet->need_vfio = false;
313 tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
314 memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
315 g_free(tmp);
316
317 tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
318 memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
319 TYPE_SPAPR_IOMMU_MEMORY_REGION,
320 tcetobj, tmp, 0);
321 g_free(tmp);
322
323 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
324
325 vmstate_register(VMSTATE_IF(tcet), tcet->liobn, &vmstate_spapr_tce_table,
326 tcet);
327}
328
329void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio)
330{
331 size_t table_size = tcet->nb_table * sizeof(uint64_t);
332 uint64_t *oldtable;
333 int newfd = -1;
334
335 g_assert(need_vfio != tcet->need_vfio);
336
337 tcet->need_vfio = need_vfio;
338
339 if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) {
340 return;
341 }
342
343 oldtable = tcet->table;
344
345 tcet->table = spapr_tce_alloc_table(tcet->liobn,
346 tcet->page_shift,
347 tcet->bus_offset,
348 tcet->nb_table,
349 &newfd,
350 need_vfio);
351 memcpy(tcet->table, oldtable, table_size);
352
353 spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
354
355 tcet->fd = newfd;
356}
357
358SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
359{
360 SpaprTceTable *tcet;
361 gchar *tmp;
362
363 if (spapr_tce_find_by_liobn(liobn)) {
364 error_report("Attempted to create TCE table with duplicate"
365 " LIOBN 0x%x", liobn);
366 return NULL;
367 }
368
369 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
370 tcet->liobn = liobn;
371
372 tmp = g_strdup_printf("tce-table-%x", liobn);
373 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet));
374 g_free(tmp);
375 object_unref(OBJECT(tcet));
376
377 qdev_realize(DEVICE(tcet), NULL, NULL);
378
379 return tcet;
380}
381
382void spapr_tce_table_enable(SpaprTceTable *tcet,
383 uint32_t page_shift, uint64_t bus_offset,
384 uint32_t nb_table)
385{
386 if (tcet->nb_table) {
387 warn_report("trying to enable already enabled TCE table");
388 return;
389 }
390
391 tcet->bus_offset = bus_offset;
392 tcet->page_shift = page_shift;
393 tcet->nb_table = nb_table;
394 tcet->table = spapr_tce_alloc_table(tcet->liobn,
395 tcet->page_shift,
396 tcet->bus_offset,
397 tcet->nb_table,
398 &tcet->fd,
399 tcet->need_vfio);
400
401 memory_region_set_size(MEMORY_REGION(&tcet->iommu),
402 (uint64_t)tcet->nb_table << tcet->page_shift);
403 memory_region_add_subregion(&tcet->root, tcet->bus_offset,
404 MEMORY_REGION(&tcet->iommu));
405}
406
407void spapr_tce_table_disable(SpaprTceTable *tcet)
408{
409 if (!tcet->nb_table) {
410 return;
411 }
412
413 memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu));
414 memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0);
415
416 spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
417 tcet->fd = -1;
418 tcet->table = NULL;
419 tcet->bus_offset = 0;
420 tcet->page_shift = 0;
421 tcet->nb_table = 0;
422}
423
424static void spapr_tce_table_unrealize(DeviceState *dev)
425{
426 SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
427
428 vmstate_unregister(VMSTATE_IF(tcet), &vmstate_spapr_tce_table, tcet);
429
430 QLIST_REMOVE(tcet, list);
431
432 spapr_tce_table_disable(tcet);
433}
434
435MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet)
436{
437 return &tcet->root;
438}
439
440static void spapr_tce_reset(DeviceState *dev)
441{
442 SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
443 size_t table_size = tcet->nb_table * sizeof(uint64_t);
444
445 if (tcet->nb_table) {
446 memset(tcet->table, 0, table_size);
447 }
448}
449
450static target_ulong put_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
451 target_ulong tce)
452{
453 IOMMUTLBEvent event;
454 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
455 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
456
457 if (index >= tcet->nb_table) {
458 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
459 TARGET_FMT_lx "\n", ioba);
460 return H_PARAMETER;
461 }
462
463 tcet->table[index] = tce;
464
465 event.entry.target_as = &address_space_memory,
466 event.entry.iova = (ioba - tcet->bus_offset) & page_mask;
467 event.entry.translated_addr = tce & page_mask;
468 event.entry.addr_mask = ~page_mask;
469 event.entry.perm = spapr_tce_iommu_access_flags(tce);
470 event.type = event.entry.perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP;
471 memory_region_notify_iommu(&tcet->iommu, 0, event);
472
473 return H_SUCCESS;
474}
475
476static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
477 SpaprMachineState *spapr,
478 target_ulong opcode, target_ulong *args)
479{
480 int i;
481 target_ulong liobn = args[0];
482 target_ulong ioba = args[1];
483 target_ulong ioba1 = ioba;
484 target_ulong tce_list = args[2];
485 target_ulong npages = args[3];
486 target_ulong ret = H_PARAMETER, tce = 0;
487 SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
488 CPUState *cs = CPU(cpu);
489 hwaddr page_mask, page_size;
490
491 if (!tcet) {
492 return H_PARAMETER;
493 }
494
495 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
496 return H_PARAMETER;
497 }
498
499 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
500 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
501 ioba &= page_mask;
502
503 for (i = 0; i < npages; ++i, ioba += page_size) {
504 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
505
506 ret = put_tce_emu(tcet, ioba, tce);
507 if (ret) {
508 break;
509 }
510 }
511
512
513 i = i ? (i - 1) : 0;
514 if (SPAPR_IS_PCI_LIOBN(liobn)) {
515 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
516 } else {
517 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
518 }
519 return ret;
520}
521
522static target_ulong h_stuff_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
523 target_ulong opcode, target_ulong *args)
524{
525 int i;
526 target_ulong liobn = args[0];
527 target_ulong ioba = args[1];
528 target_ulong tce_value = args[2];
529 target_ulong npages = args[3];
530 target_ulong ret = H_PARAMETER;
531 SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
532 hwaddr page_mask, page_size;
533
534 if (!tcet) {
535 return H_PARAMETER;
536 }
537
538 if (npages > tcet->nb_table) {
539 return H_PARAMETER;
540 }
541
542 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
543 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
544 ioba &= page_mask;
545
546 for (i = 0; i < npages; ++i, ioba += page_size) {
547 ret = put_tce_emu(tcet, ioba, tce_value);
548 if (ret) {
549 break;
550 }
551 }
552 if (SPAPR_IS_PCI_LIOBN(liobn)) {
553 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
554 } else {
555 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
556 }
557
558 return ret;
559}
560
561static target_ulong h_put_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
562 target_ulong opcode, target_ulong *args)
563{
564 target_ulong liobn = args[0];
565 target_ulong ioba = args[1];
566 target_ulong tce = args[2];
567 target_ulong ret = H_PARAMETER;
568 SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
569
570 if (tcet) {
571 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
572
573 ioba &= page_mask;
574
575 ret = put_tce_emu(tcet, ioba, tce);
576 }
577 if (SPAPR_IS_PCI_LIOBN(liobn)) {
578 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
579 } else {
580 trace_spapr_iommu_put(liobn, ioba, tce, ret);
581 }
582
583 return ret;
584}
585
586static target_ulong get_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
587 target_ulong *tce)
588{
589 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
590
591 if (index >= tcet->nb_table) {
592 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
593 TARGET_FMT_lx "\n", ioba);
594 return H_PARAMETER;
595 }
596
597 *tce = tcet->table[index];
598
599 return H_SUCCESS;
600}
601
602static target_ulong h_get_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
603 target_ulong opcode, target_ulong *args)
604{
605 target_ulong liobn = args[0];
606 target_ulong ioba = args[1];
607 target_ulong tce = 0;
608 target_ulong ret = H_PARAMETER;
609 SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
610
611 if (tcet) {
612 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
613
614 ioba &= page_mask;
615
616 ret = get_tce_emu(tcet, ioba, &tce);
617 if (!ret) {
618 args[0] = tce;
619 }
620 }
621 if (SPAPR_IS_PCI_LIOBN(liobn)) {
622 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
623 } else {
624 trace_spapr_iommu_get(liobn, ioba, ret, tce);
625 }
626
627 return ret;
628}
629
630int spapr_dma_dt(void *fdt, int node_off, const char *propname,
631 uint32_t liobn, uint64_t window, uint32_t size)
632{
633 uint32_t dma_prop[5];
634 int ret;
635
636 dma_prop[0] = cpu_to_be32(liobn);
637 dma_prop[1] = cpu_to_be32(window >> 32);
638 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
639 dma_prop[3] = 0;
640 dma_prop[4] = cpu_to_be32(size);
641
642 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
643 if (ret < 0) {
644 return ret;
645 }
646
647 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
648 if (ret < 0) {
649 return ret;
650 }
651
652 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
653 if (ret < 0) {
654 return ret;
655 }
656
657 return 0;
658}
659
660int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
661 SpaprTceTable *tcet)
662{
663 if (!tcet) {
664 return 0;
665 }
666
667 return spapr_dma_dt(fdt, node_off, propname,
668 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
669}
670
671static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
672{
673 DeviceClass *dc = DEVICE_CLASS(klass);
674 dc->realize = spapr_tce_table_realize;
675 dc->reset = spapr_tce_reset;
676 dc->unrealize = spapr_tce_table_unrealize;
677
678 dc->user_creatable = false;
679
680 QLIST_INIT(&spapr_tce_tables);
681
682
683 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
684 spapr_register_hypercall(H_GET_TCE, h_get_tce);
685 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
686 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
687}
688
689static const TypeInfo spapr_tce_table_info = {
690 .name = TYPE_SPAPR_TCE_TABLE,
691 .parent = TYPE_DEVICE,
692 .instance_size = sizeof(SpaprTceTable),
693 .class_init = spapr_tce_table_class_init,
694};
695
696static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data)
697{
698 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
699
700 imrc->translate = spapr_tce_translate_iommu;
701 imrc->replay = spapr_tce_replay;
702 imrc->get_min_page_size = spapr_tce_get_min_page_size;
703 imrc->notify_flag_changed = spapr_tce_notify_flag_changed;
704 imrc->get_attr = spapr_tce_get_attr;
705}
706
707static const TypeInfo spapr_iommu_memory_region_info = {
708 .parent = TYPE_IOMMU_MEMORY_REGION,
709 .name = TYPE_SPAPR_IOMMU_MEMORY_REGION,
710 .class_init = spapr_iommu_memory_region_class_init,
711};
712
713static void register_types(void)
714{
715 type_register_static(&spapr_tce_table_info);
716 type_register_static(&spapr_iommu_memory_region_info);
717}
718
719type_init(register_types);
720
