1#ifndef CPU_COMMON_H
2#define CPU_COMMON_H
3
4
5
6#ifndef CONFIG_USER_ONLY
7#include "exec/hwaddr.h"
8#endif
9
10
11
12
13
14typedef uint64_t vaddr;
15#define VADDR_PRId PRId64
16#define VADDR_PRIu PRIu64
17#define VADDR_PRIo PRIo64
18#define VADDR_PRIx PRIx64
19#define VADDR_PRIX PRIX64
20#define VADDR_MAX UINT64_MAX
21
22void cpu_exec_init_all(void);
23void cpu_exec_step_atomic(CPUState *cpu);
24
25
26
27
28extern uintptr_t qemu_host_page_size;
29extern intptr_t qemu_host_page_mask;
30
31#define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
32#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size())
33
34
35extern QemuMutex qemu_cpu_list_lock;
36void qemu_init_cpu_list(void);
37void cpu_list_lock(void);
38void cpu_list_unlock(void);
39unsigned int cpu_list_generation_id_get(void);
40
41void tcg_flush_softmmu_tlb(CPUState *cs);
42void tcg_flush_jmp_cache(CPUState *cs);
43
44void tcg_iommu_init_notifier_list(CPUState *cpu);
45void tcg_iommu_free_notifier_list(CPUState *cpu);
46
47#if !defined(CONFIG_USER_ONLY)
48
49enum device_endian {
50 DEVICE_NATIVE_ENDIAN,
51 DEVICE_BIG_ENDIAN,
52 DEVICE_LITTLE_ENDIAN,
53};
54
55#if HOST_BIG_ENDIAN
56#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
57#else
58#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
59#endif
60
61
62#if defined(CONFIG_XEN_BACKEND)
63typedef uint64_t ram_addr_t;
64# define RAM_ADDR_MAX UINT64_MAX
65# define RAM_ADDR_FMT "%" PRIx64
66#else
67typedef uintptr_t ram_addr_t;
68# define RAM_ADDR_MAX UINTPTR_MAX
69# define RAM_ADDR_FMT "%" PRIxPTR
70#endif
71
72
73
74void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
75
76ram_addr_t qemu_ram_addr_from_host(void *ptr);
77ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
78RAMBlock *qemu_ram_block_by_name(const char *name);
79RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
80 ram_addr_t *offset);
81ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
82void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
83void qemu_ram_unset_idstr(RAMBlock *block);
84const char *qemu_ram_get_idstr(RAMBlock *rb);
85void *qemu_ram_get_host_addr(RAMBlock *rb);
86ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
87ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
88ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
89bool qemu_ram_is_shared(RAMBlock *rb);
90bool qemu_ram_is_noreserve(RAMBlock *rb);
91bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
92void qemu_ram_set_uf_zeroable(RAMBlock *rb);
93bool qemu_ram_is_migratable(RAMBlock *rb);
94void qemu_ram_set_migratable(RAMBlock *rb);
95void qemu_ram_unset_migratable(RAMBlock *rb);
96bool qemu_ram_is_named_file(RAMBlock *rb);
97int qemu_ram_get_fd(RAMBlock *rb);
98
99size_t qemu_ram_pagesize(RAMBlock *block);
100size_t qemu_ram_pagesize_largest(void);
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119
120
121void cpu_address_space_init(CPUState *cpu, int asidx,
122 const char *prefix, MemoryRegion *mr);
123
124void cpu_physical_memory_rw(hwaddr addr, void *buf,
125 hwaddr len, bool is_write);
126static inline void cpu_physical_memory_read(hwaddr addr,
127 void *buf, hwaddr len)
128{
129 cpu_physical_memory_rw(addr, buf, len, false);
130}
131static inline void cpu_physical_memory_write(hwaddr addr,
132 const void *buf, hwaddr len)
133{
134 cpu_physical_memory_rw(addr, (void *)buf, len, true);
135}
136void cpu_reloading_memory_map(void);
137void *cpu_physical_memory_map(hwaddr addr,
138 hwaddr *plen,
139 bool is_write);
140void cpu_physical_memory_unmap(void *buffer, hwaddr len,
141 bool is_write, hwaddr access_len);
142void cpu_register_map_client(QEMUBH *bh);
143void cpu_unregister_map_client(QEMUBH *bh);
144
145bool cpu_physical_memory_is_io(hwaddr phys_addr);
146
147
148
149
150
151
152void qemu_flush_coalesced_mmio_buffer(void);
153
154void cpu_flush_icache_range(hwaddr start, hwaddr len);
155
156typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
157
158int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
159int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
160
161#endif
162
163
164int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
165 void *ptr, size_t len, bool is_write);
166
167
168void list_cpus(void);
169
170#endif
171