1/* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11#ifndef ASPEED_SCU_H 12#define ASPEED_SCU_H 13 14#include "hw/sysbus.h" 15#include "qom/object.h" 16 17#define TYPE_ASPEED_SCU "aspeed.scu" 18OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU) 19#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" 20#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" 21#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" 22#define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030" 23 24#define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 25#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) 26 27struct AspeedSCUState { 28 /*< private >*/ 29 SysBusDevice parent_obj; 30 31 /*< public >*/ 32 MemoryRegion iomem; 33 34 uint32_t regs[ASPEED_AST2600_SCU_NR_REGS]; 35 uint32_t silicon_rev; 36 uint32_t hw_strap1; 37 uint32_t hw_strap2; 38 uint32_t hw_prot_key; 39}; 40 41#define AST2400_A0_SILICON_REV 0x02000303U 42#define AST2400_A1_SILICON_REV 0x02010303U 43#define AST2500_A0_SILICON_REV 0x04000303U 44#define AST2500_A1_SILICON_REV 0x04010303U 45#define AST2600_A0_SILICON_REV 0x05000303U 46#define AST2600_A1_SILICON_REV 0x05010303U 47#define AST2600_A2_SILICON_REV 0x05020303U 48#define AST2600_A3_SILICON_REV 0x05030303U 49#define AST1030_A0_SILICON_REV 0x80000000U 50#define AST1030_A1_SILICON_REV 0x80010000U 51 52#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) 53 54extern bool is_supported_silicon_rev(uint32_t silicon_rev); 55 56 57struct AspeedSCUClass { 58 SysBusDeviceClass parent_class; 59 60 const uint32_t *resets; 61 uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); 62 uint32_t (*get_apb)(AspeedSCUState *s); 63 uint32_t apb_divider; 64 uint32_t nr_regs; 65 bool clkin_25Mhz; 66 const MemoryRegionOps *ops; 67}; 68 69#define ASPEED_SCU_PROT_KEY 0x1688A8A8 70 71uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); 72 73/* 74 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 75 * were added. 76 * 77 * Original header file : 78 * arch/arm/mach-aspeed/include/mach/regs-scu.h 79 * 80 * Copyright (C) 2012-2020 ASPEED Technology Inc. 81 * 82 * This program is free software; you can redistribute it and/or modify 83 * it under the terms of the GNU General Public License version 2 as 84 * published by the Free Software Foundation. 85 * 86 * History : 87 * 1. 2012/12/29 Ryan Chen Create 88 */ 89 90/* SCU08 Clock Selection Register 91 * 92 * 31 Enable Video Engine clock dynamic slow down 93 * 30:28 Video Engine clock slow down setting 94 * 27 2D Engine GCLK clock source selection 95 * 26 2D Engine GCLK clock throttling enable 96 * 25:23 APB PCLK divider selection 97 * 22:20 LPC Host LHCLK divider selection 98 * 19 LPC Host LHCLK clock generation/output enable control 99 * 18:16 MAC AHB bus clock divider selection 100 * 15 SD/SDIO clock running enable 101 * 14:12 SD/SDIO divider selection 102 * 11 Reserved 103 * 10:8 Video port output clock delay control bit 104 * 7 ARM CPU/AHB clock slow down enable 105 * 6:4 ARM CPU/AHB clock slow down setting 106 * 3:2 ECLK clock source selection 107 * 1 CPU/AHB clock slow down idle timer 108 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) 109 */ 110#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) 111 112/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) 113 * 114 * 18 H-PLL parameter selection 115 * 0: Select H-PLL by strapping resistors 116 * 1: Select H-PLL by the programmed registers (SCU24[17:0]) 117 * 17 Enable H-PLL bypass mode 118 * 16 Turn off H-PLL 119 * 10:5 H-PLL Numerator 120 * 4 H-PLL Output Divider 121 * 3:0 H-PLL Denumerator 122 * 123 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] 124 */ 125 126#define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) 127#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) 128#define SCU_AST2400_H_PLL_OFF (0x1 << 16) 129 130/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) 131 * 132 * 21 Enable H-PLL reset 133 * 20 Enable H-PLL bypass mode 134 * 19 Turn off H-PLL 135 * 18:13 H-PLL Post Divider 136 * 12:5 H-PLL Numerator (M) 137 * 4:0 H-PLL Denumerator (N) 138 * 139 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) 140 * 141 * The default frequency is 792Mhz when CLKIN = 24MHz 142 */ 143 144#define SCU_H_PLL_BYPASS_EN (0x1 << 20) 145#define SCU_H_PLL_OFF (0x1 << 19) 146 147/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) 148 * 149 * 31:29 Software defined strapping registers 150 * 28:27 DRAM size setting (for VGA driver use) 151 * 26:24 DRAM configuration setting 152 * 23 Enable 25 MHz reference clock input 153 * 22 Enable GPIOE pass-through mode 154 * 21 Enable GPIOD pass-through mode 155 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 156 * 19 Disable ACPI function 157 * 23,18 Clock source selection 158 * 17 Enable BMC 2nd boot watchdog timer 159 * 16 SuperIO configuration address selection 160 * 15 VGA Class Code selection 161 * 14 Enable LPC dedicated reset pin function 162 * 13:12 SPI mode selection 163 * 11:10 CPU/AHB clock frequency ratio selection 164 * 9:8 H-PLL default clock frequency selection 165 * 7 Define MAC#2 interface 166 * 6 Define MAC#1 interface 167 * 5 Enable VGA BIOS ROM 168 * 4 Boot flash memory extended option 169 * 3:2 VGA memory size selection 170 * 1:0 BMC CPU boot code selection 171 */ 172#define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 173#define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 174 175#define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 176#define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 177#define DRAM_SIZE_64MB 0 178#define DRAM_SIZE_128MB 1 179#define DRAM_SIZE_256MB 2 180#define DRAM_SIZE_512MB 3 181 182#define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 183#define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 184 185#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 186#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 187#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 188#define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 189 190/* bit 23, 18 [1,0] */ 191#define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 192 | (((x) & 0x1) << 18)) 193#define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 194 | (((x) >> 18) & 0x1)) 195#define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 196#define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) 197#define AST2400_CLK_24M_IN 0 198#define AST2400_CLK_48M_IN 1 199#define AST2400_CLK_25M_IN_24M_USB_CKI 2 200#define AST2400_CLK_25M_IN_48M_USB_CKI 3 201 202#define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) 203#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 204#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 205#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 206#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 207 208#define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 209#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 210#define SCU_HW_STRAP_SPI_DIS 0 211#define SCU_HW_STRAP_SPI_MASTER 1 212#define SCU_HW_STRAP_SPI_M_S_EN 2 213#define SCU_HW_STRAP_SPI_PASS_THROUGH 3 214 215#define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 216#define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 217#define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 218#define AST2400_CPU_AHB_RATIO_1_1 0 219#define AST2400_CPU_AHB_RATIO_2_1 1 220#define AST2400_CPU_AHB_RATIO_4_1 2 221#define AST2400_CPU_AHB_RATIO_3_1 3 222 223#define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 224#define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 225#define AST2400_CPU_384MHZ 0 226#define AST2400_CPU_360MHZ 1 227#define AST2400_CPU_336MHZ 2 228#define AST2400_CPU_408MHZ 3 229 230#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 231#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 232#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 233#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 234 235#define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 236#define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 237#define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 238#define VGA_8M_DRAM 0 239#define VGA_16M_DRAM 1 240#define VGA_32M_DRAM 2 241#define VGA_64M_DRAM 3 242 243#define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 244#define AST2400_NOR_BOOT 0 245#define AST2400_NAND_BOOT 1 246#define AST2400_SPI_BOOT 2 247#define AST2400_DIS_BOOT 3 248 249/* 250 * SCU70 Hardware strapping register definition (for Aspeed AST2500 251 * SoC and higher) 252 * 253 * 31 Enable SPI Flash Strap Auto Fetch Mode 254 * 30 Enable GPIO Strap Mode 255 * 29 Select UART Debug Port 256 * 28 Reserved (1) 257 * 27 Enable fast reset mode for ARM ICE debugger 258 * 26 Enable eSPI flash mode 259 * 25 Enable eSPI mode 260 * 24 Select DDR4 SDRAM 261 * 23 Select 25 MHz reference clock input mode 262 * 22 Enable GPIOE pass-through mode 263 * 21 Enable GPIOD pass-through mode 264 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 265 * 19 Enable ACPI function 266 * 18 Select USBCKI input frequency 267 * 17 Enable BMC 2nd boot watchdog timer 268 * 16 SuperIO configuration address selection 269 * 15 VGA Class Code selection 270 * 14 Select dedicated LPC reset input 271 * 13:12 SPI mode selection 272 * 11:9 AXI/AHB clock frequency ratio selection 273 * 8 Reserved (0) 274 * 7 Define MAC#2 interface 275 * 6 Define MAC#1 interface 276 * 5 Enable dedicated VGA BIOS ROM 277 * 4 Reserved (0) 278 * 3:2 VGA memory size selection 279 * 1 Reserved (1) 280 * 0 Disable CPU boot 281 */ 282#define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 283#define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 284#define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 285#define UART_DEBUG_UART1 0 286#define UART_DEBUG_UART5 1 287#define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 288 289#define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 290#define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 291#define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 292#define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 293#define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23) 294 295#define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 296#define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 297#define USBCKI_FREQ_24MHZ 0 298#define USBCKI_FREQ_28MHZ 1 299 300#define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 301#define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 302#define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 303#define AXI_AHB_RATIO_UNDEFINED 0 304#define AXI_AHB_RATIO_2_1 1 305#define AXI_AHB_RATIO_3_1 2 306#define AXI_AHB_RATIO_4_1 3 307#define AXI_AHB_RATIO_5_1 4 308#define AXI_AHB_RATIO_6_1 5 309#define AXI_AHB_RATIO_7_1 6 310#define AXI_AHB_RATIO_8_1 7 311 312#define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 313#define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 314 315#define AST2500_HW_STRAP1_DEFAULTS ( \ 316 SCU_AST2500_HW_STRAP_RESERVED28 | \ 317 SCU_HW_STRAP_2ND_BOOT_WDT | \ 318 SCU_HW_STRAP_VGA_CLASS_CODE | \ 319 SCU_HW_STRAP_LPC_RESET_PIN | \ 320 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 321 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 322 SCU_AST2500_HW_STRAP_RESERVED1) 323 324/* 325 * SCU200 H-PLL Parameter Register (for Aspeed AST2600 SOC) 326 * 327 * 28:26 H-PLL Parameters 328 * 25 Enable H-PLL reset 329 * 24 Enable H-PLL bypass mode 330 * 23 Turn off H-PLL 331 * 22:19 H-PLL Post Divider (P) 332 * 18:13 H-PLL Numerator (M) 333 * 12:0 H-PLL Denumerator (N) 334 * 335 * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1) 336 * 337 * The default frequency is 1200Mhz when CLKIN = 25MHz 338 */ 339#define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24) 340#define SCU_AST2600_H_PLL_OFF (0x1 << 23) 341 342/* 343 * SCU310 Clock Selection Register Set 4 (for Aspeed AST1030 SOC) 344 * 345 * 31 I3C Clock Source selection 346 * 30:28 I3C clock divider selection 347 * 26:24 MAC AHB clock divider selection 348 * 22:20 RGMII 125MHz clock divider ration 349 * 19:16 RGMII 50MHz clock divider ration 350 * 15 LHCLK clock generation/output enable control 351 * 14:12 LHCLK divider selection 352 * 11:8 APB Bus PCLK divider selection 353 * 7 Select PECI clock source 354 * 6 Select UART debug port clock source 355 * 5 Select UART6 clock source 356 * 4 Select UART5 clock source 357 * 3 Select UART4 clock source 358 * 2 Select UART3 clock source 359 * 1 Select UART2 clock source 360 * 0 Select UART1 clock source 361 */ 362#define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf) 363 364#endif /* ASPEED_SCU_H */ 365