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31#include "qemu/osdep.h"
32#include "qemu/datadir.h"
33#include "qemu/units.h"
34#include "qemu/option.h"
35#include "monitor/qdev.h"
36#include "hw/sysbus.h"
37#include "hw/arm/boot.h"
38#include "hw/arm/primecell.h"
39#include "hw/arm/virt.h"
40#include "hw/block/flash.h"
41#include "hw/vfio/vfio-calxeda-xgmac.h"
42#include "hw/vfio/vfio-amd-xgbe.h"
43#include "hw/display/ramfb.h"
44#include "net/net.h"
45#include "sysemu/device_tree.h"
46#include "sysemu/numa.h"
47#include "sysemu/runstate.h"
48#include "sysemu/tpm.h"
49#include "sysemu/tcg.h"
50#include "sysemu/kvm.h"
51#include "sysemu/hvf.h"
52#include "sysemu/qtest.h"
53#include "hw/loader.h"
54#include "qapi/error.h"
55#include "qemu/bitops.h"
56#include "qemu/error-report.h"
57#include "qemu/module.h"
58#include "hw/pci-host/gpex.h"
59#include "hw/virtio/virtio-pci.h"
60#include "hw/core/sysbus-fdt.h"
61#include "hw/platform-bus.h"
62#include "hw/qdev-properties.h"
63#include "hw/arm/fdt.h"
64#include "hw/intc/arm_gic.h"
65#include "hw/intc/arm_gicv3_common.h"
66#include "hw/intc/arm_gicv3_its_common.h"
67#include "hw/irq.h"
68#include "kvm_arm.h"
69#include "hw/firmware/smbios.h"
70#include "qapi/visitor.h"
71#include "qapi/qapi-visit-common.h"
72#include "standard-headers/linux/input.h"
73#include "hw/arm/smmuv3.h"
74#include "hw/acpi/acpi.h"
75#include "target/arm/internals.h"
76#include "hw/mem/pc-dimm.h"
77#include "hw/mem/nvdimm.h"
78#include "hw/acpi/generic_event_device.h"
79#include "hw/virtio/virtio-md-pci.h"
80#include "hw/virtio/virtio-iommu.h"
81#include "hw/char/pl011.h"
82#include "qemu/guest-random.h"
83
84#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
85 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
86 void *data) \
87 { \
88 MachineClass *mc = MACHINE_CLASS(oc); \
89 virt_machine_##major##_##minor##_options(mc); \
90 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
91 if (latest) { \
92 mc->alias = "virt"; \
93 } \
94 } \
95 static const TypeInfo machvirt_##major##_##minor##_info = { \
96 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
97 .parent = TYPE_VIRT_MACHINE, \
98 .class_init = virt_##major##_##minor##_class_init, \
99 }; \
100 static void machvirt_machine_##major##_##minor##_init(void) \
101 { \
102 type_register_static(&machvirt_##major##_##minor##_info); \
103 } \
104 type_init(machvirt_machine_##major##_##minor##_init);
105
106#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
107 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
108#define DEFINE_VIRT_MACHINE(major, minor) \
109 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
110
111
112
113#define NUM_IRQS 256
114
115#define PLATFORM_BUS_NUM_IRQS 64
116
117
118#define LEGACY_RAMLIMIT_GB 255
119#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
120
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132
133static const MemMapEntry base_memmap[] = {
134
135 [VIRT_FLASH] = { 0, 0x08000000 },
136 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
137
138 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
139 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
140 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
141 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
142 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
143
144 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
145
146 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
147 [VIRT_UART] = { 0x09000000, 0x00001000 },
148 [VIRT_RTC] = { 0x09010000, 0x00001000 },
149 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
150 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
151 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
152 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
153 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
154 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
155 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
156 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
157 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
158 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
159
160 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
161 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
162 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
163 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
164 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
165
166 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
167};
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184
185static MemMapEntry extended_memmap[] = {
186
187 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
188 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
189
190 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
191};
192
193static const int a15irqmap[] = {
194 [VIRT_UART] = 1,
195 [VIRT_RTC] = 2,
196 [VIRT_PCIE] = 3,
197 [VIRT_GPIO] = 7,
198 [VIRT_SECURE_UART] = 8,
199 [VIRT_ACPI_GED] = 9,
200 [VIRT_MMIO] = 16,
201 [VIRT_GIC_V2M] = 48,
202 [VIRT_SMMU] = 74,
203 [VIRT_PLATFORM_BUS] = 112,
204};
205
206static const char *valid_cpus[] = {
207#ifdef CONFIG_TCG
208 ARM_CPU_TYPE_NAME("cortex-a7"),
209 ARM_CPU_TYPE_NAME("cortex-a15"),
210 ARM_CPU_TYPE_NAME("cortex-a35"),
211 ARM_CPU_TYPE_NAME("cortex-a55"),
212 ARM_CPU_TYPE_NAME("cortex-a72"),
213 ARM_CPU_TYPE_NAME("cortex-a76"),
214 ARM_CPU_TYPE_NAME("a64fx"),
215 ARM_CPU_TYPE_NAME("neoverse-n1"),
216 ARM_CPU_TYPE_NAME("neoverse-v1"),
217#endif
218 ARM_CPU_TYPE_NAME("cortex-a53"),
219 ARM_CPU_TYPE_NAME("cortex-a57"),
220 ARM_CPU_TYPE_NAME("host"),
221 ARM_CPU_TYPE_NAME("max"),
222};
223
224static bool cpu_type_valid(const char *cpu)
225{
226 int i;
227
228 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
229 if (strcmp(cpu, valid_cpus[i]) == 0) {
230 return true;
231 }
232 }
233 return false;
234}
235
236static void create_randomness(MachineState *ms, const char *node)
237{
238 struct {
239 uint64_t kaslr;
240 uint8_t rng[32];
241 } seed;
242
243 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
244 return;
245 }
246 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
247 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
248}
249
250static void create_fdt(VirtMachineState *vms)
251{
252 MachineState *ms = MACHINE(vms);
253 int nb_numa_nodes = ms->numa_state->num_nodes;
254 void *fdt = create_device_tree(&vms->fdt_size);
255
256 if (!fdt) {
257 error_report("create_device_tree() failed");
258 exit(1);
259 }
260
261 ms->fdt = fdt;
262
263
264 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
265 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
266 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
267 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
268
269
270 qemu_fdt_add_subnode(fdt, "/chosen");
271 if (vms->dtb_randomness) {
272 create_randomness(ms, "/chosen");
273 }
274
275 if (vms->secure) {
276 qemu_fdt_add_subnode(fdt, "/secure-chosen");
277 if (vms->dtb_randomness) {
278 create_randomness(ms, "/secure-chosen");
279 }
280 }
281
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286
287 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
288 qemu_fdt_add_subnode(fdt, "/apb-pclk");
289 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
290 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
291 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
292 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
293 "clk24mhz");
294 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
295
296 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
297 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
298 uint32_t *matrix = g_malloc0(size);
299 int idx, i, j;
300
301 for (i = 0; i < nb_numa_nodes; i++) {
302 for (j = 0; j < nb_numa_nodes; j++) {
303 idx = (i * nb_numa_nodes + j) * 3;
304 matrix[idx + 0] = cpu_to_be32(i);
305 matrix[idx + 1] = cpu_to_be32(j);
306 matrix[idx + 2] =
307 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
308 }
309 }
310
311 qemu_fdt_add_subnode(fdt, "/distance-map");
312 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
313 "numa-distance-map-v1");
314 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
315 matrix, size);
316 g_free(matrix);
317 }
318}
319
320static void fdt_add_timer_nodes(const VirtMachineState *vms)
321{
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339
340 ARMCPU *armcpu;
341 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
342 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
343 MachineState *ms = MACHINE(vms);
344
345 if (vmc->claim_edge_triggered_timers) {
346 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
347 }
348
349 if (vms->gic_version == VIRT_GIC_VERSION_2) {
350 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
351 GIC_FDT_IRQ_PPI_CPU_WIDTH,
352 (1 << MACHINE(vms)->smp.cpus) - 1);
353 }
354
355 qemu_fdt_add_subnode(ms->fdt, "/timer");
356
357 armcpu = ARM_CPU(qemu_get_cpu(0));
358 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
359 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
360 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
361 compat, sizeof(compat));
362 } else {
363 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
364 "arm,armv7-timer");
365 }
366 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
367 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
368 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
369 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
370 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
371 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
372}
373
374static void fdt_add_cpu_nodes(const VirtMachineState *vms)
375{
376 int cpu;
377 int addr_cells = 1;
378 const MachineState *ms = MACHINE(vms);
379 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
380 int smp_cpus = ms->smp.cpus;
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394
395 for (cpu = 0; cpu < smp_cpus; cpu++) {
396 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
397
398 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
399 addr_cells = 2;
400 break;
401 }
402 }
403
404 qemu_fdt_add_subnode(ms->fdt, "/cpus");
405 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
406 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
407
408 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
409 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
410 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
411 CPUState *cs = CPU(armcpu);
412
413 qemu_fdt_add_subnode(ms->fdt, nodename);
414 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
415 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
416 armcpu->dtb_compatible);
417
418 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
419 qemu_fdt_setprop_string(ms->fdt, nodename,
420 "enable-method", "psci");
421 }
422
423 if (addr_cells == 2) {
424 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
425 armcpu->mp_affinity);
426 } else {
427 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
428 armcpu->mp_affinity);
429 }
430
431 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
432 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
433 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
434 }
435
436 if (!vmc->no_cpu_topology) {
437 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
438 qemu_fdt_alloc_phandle(ms->fdt));
439 }
440
441 g_free(nodename);
442 }
443
444 if (!vmc->no_cpu_topology) {
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461 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
462
463 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
464 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
465 char *map_path;
466
467 if (ms->smp.threads > 1) {
468 map_path = g_strdup_printf(
469 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
470 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
471 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
472 (cpu / ms->smp.threads) % ms->smp.cores,
473 cpu % ms->smp.threads);
474 } else {
475 map_path = g_strdup_printf(
476 "/cpus/cpu-map/socket%d/cluster%d/core%d",
477 cpu / (ms->smp.clusters * ms->smp.cores),
478 (cpu / ms->smp.cores) % ms->smp.clusters,
479 cpu % ms->smp.cores);
480 }
481 qemu_fdt_add_path(ms->fdt, map_path);
482 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
483
484 g_free(map_path);
485 g_free(cpu_path);
486 }
487 }
488}
489
490static void fdt_add_its_gic_node(VirtMachineState *vms)
491{
492 char *nodename;
493 MachineState *ms = MACHINE(vms);
494
495 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
496 nodename = g_strdup_printf("/intc/its@%" PRIx64,
497 vms->memmap[VIRT_GIC_ITS].base);
498 qemu_fdt_add_subnode(ms->fdt, nodename);
499 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
500 "arm,gic-v3-its");
501 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
502 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
503 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
504 2, vms->memmap[VIRT_GIC_ITS].base,
505 2, vms->memmap[VIRT_GIC_ITS].size);
506 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
507 g_free(nodename);
508}
509
510static void fdt_add_v2m_gic_node(VirtMachineState *vms)
511{
512 MachineState *ms = MACHINE(vms);
513 char *nodename;
514
515 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
516 vms->memmap[VIRT_GIC_V2M].base);
517 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
518 qemu_fdt_add_subnode(ms->fdt, nodename);
519 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
520 "arm,gic-v2m-frame");
521 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
522 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
523 2, vms->memmap[VIRT_GIC_V2M].base,
524 2, vms->memmap[VIRT_GIC_V2M].size);
525 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
526 g_free(nodename);
527}
528
529static void fdt_add_gic_node(VirtMachineState *vms)
530{
531 MachineState *ms = MACHINE(vms);
532 char *nodename;
533
534 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
535 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
536
537 nodename = g_strdup_printf("/intc@%" PRIx64,
538 vms->memmap[VIRT_GIC_DIST].base);
539 qemu_fdt_add_subnode(ms->fdt, nodename);
540 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
541 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
542 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
543 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
544 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
545 if (vms->gic_version != VIRT_GIC_VERSION_2) {
546 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
547
548 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
549 "arm,gic-v3");
550
551 qemu_fdt_setprop_cell(ms->fdt, nodename,
552 "#redistributor-regions", nb_redist_regions);
553
554 if (nb_redist_regions == 1) {
555 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
556 2, vms->memmap[VIRT_GIC_DIST].base,
557 2, vms->memmap[VIRT_GIC_DIST].size,
558 2, vms->memmap[VIRT_GIC_REDIST].base,
559 2, vms->memmap[VIRT_GIC_REDIST].size);
560 } else {
561 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
562 2, vms->memmap[VIRT_GIC_DIST].base,
563 2, vms->memmap[VIRT_GIC_DIST].size,
564 2, vms->memmap[VIRT_GIC_REDIST].base,
565 2, vms->memmap[VIRT_GIC_REDIST].size,
566 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
567 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
568 }
569
570 if (vms->virt) {
571 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
572 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
573 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
574 }
575 } else {
576
577 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
578 "arm,cortex-a15-gic");
579 if (!vms->virt) {
580 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
581 2, vms->memmap[VIRT_GIC_DIST].base,
582 2, vms->memmap[VIRT_GIC_DIST].size,
583 2, vms->memmap[VIRT_GIC_CPU].base,
584 2, vms->memmap[VIRT_GIC_CPU].size);
585 } else {
586 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
587 2, vms->memmap[VIRT_GIC_DIST].base,
588 2, vms->memmap[VIRT_GIC_DIST].size,
589 2, vms->memmap[VIRT_GIC_CPU].base,
590 2, vms->memmap[VIRT_GIC_CPU].size,
591 2, vms->memmap[VIRT_GIC_HYP].base,
592 2, vms->memmap[VIRT_GIC_HYP].size,
593 2, vms->memmap[VIRT_GIC_VCPU].base,
594 2, vms->memmap[VIRT_GIC_VCPU].size);
595 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
596 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
597 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
598 }
599 }
600
601 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
602 g_free(nodename);
603}
604
605static void fdt_add_pmu_nodes(const VirtMachineState *vms)
606{
607 ARMCPU *armcpu = ARM_CPU(first_cpu);
608 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
609 MachineState *ms = MACHINE(vms);
610
611 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
612 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
613 return;
614 }
615
616 if (vms->gic_version == VIRT_GIC_VERSION_2) {
617 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
618 GIC_FDT_IRQ_PPI_CPU_WIDTH,
619 (1 << MACHINE(vms)->smp.cpus) - 1);
620 }
621
622 qemu_fdt_add_subnode(ms->fdt, "/pmu");
623 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
624 const char compat[] = "arm,armv8-pmuv3";
625 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
626 compat, sizeof(compat));
627 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
628 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
629 }
630}
631
632static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
633{
634 DeviceState *dev;
635 MachineState *ms = MACHINE(vms);
636 int irq = vms->irqmap[VIRT_ACPI_GED];
637 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
638
639 if (ms->ram_slots) {
640 event |= ACPI_GED_MEM_HOTPLUG_EVT;
641 }
642
643 if (ms->nvdimms_state->is_enabled) {
644 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
645 }
646
647 dev = qdev_new(TYPE_ACPI_GED);
648 qdev_prop_set_uint32(dev, "ged-event", event);
649
650 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
651 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
652 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
653
654 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
655
656 return dev;
657}
658
659static void create_its(VirtMachineState *vms)
660{
661 const char *itsclass = its_class_name();
662 DeviceState *dev;
663
664 if (!strcmp(itsclass, "arm-gicv3-its")) {
665 if (!vms->tcg_its) {
666 itsclass = NULL;
667 }
668 }
669
670 if (!itsclass) {
671
672 return;
673 }
674
675 dev = qdev_new(itsclass);
676
677 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
678 &error_abort);
679 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
680 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
681
682 fdt_add_its_gic_node(vms);
683 vms->msi_controller = VIRT_MSI_CTRL_ITS;
684}
685
686static void create_v2m(VirtMachineState *vms)
687{
688 int i;
689 int irq = vms->irqmap[VIRT_GIC_V2M];
690 DeviceState *dev;
691
692 dev = qdev_new("arm-gicv2m");
693 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
694 qdev_prop_set_uint32(dev, "base-spi", irq);
695 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
696 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
697
698 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
699 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
700 qdev_get_gpio_in(vms->gic, irq + i));
701 }
702
703 fdt_add_v2m_gic_node(vms);
704 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
705}
706
707static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
708{
709 MachineState *ms = MACHINE(vms);
710
711 SysBusDevice *gicbusdev;
712 const char *gictype;
713 int i;
714 unsigned int smp_cpus = ms->smp.cpus;
715 uint32_t nb_redist_regions = 0;
716 int revision;
717
718 if (vms->gic_version == VIRT_GIC_VERSION_2) {
719 gictype = gic_class_name();
720 } else {
721 gictype = gicv3_class_name();
722 }
723
724 switch (vms->gic_version) {
725 case VIRT_GIC_VERSION_2:
726 revision = 2;
727 break;
728 case VIRT_GIC_VERSION_3:
729 revision = 3;
730 break;
731 case VIRT_GIC_VERSION_4:
732 revision = 4;
733 break;
734 default:
735 g_assert_not_reached();
736 }
737 vms->gic = qdev_new(gictype);
738 qdev_prop_set_uint32(vms->gic, "revision", revision);
739 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
740
741
742
743 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
744 if (!kvm_irqchip_in_kernel()) {
745 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
746 }
747
748 if (vms->gic_version != VIRT_GIC_VERSION_2) {
749 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
750 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
751
752 nb_redist_regions = virt_gicv3_redist_region_count(vms);
753
754 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
755 nb_redist_regions);
756 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
757
758 if (!kvm_irqchip_in_kernel()) {
759 if (vms->tcg_its) {
760 object_property_set_link(OBJECT(vms->gic), "sysmem",
761 OBJECT(mem), &error_fatal);
762 qdev_prop_set_bit(vms->gic, "has-lpi", true);
763 }
764 }
765
766 if (nb_redist_regions == 2) {
767 uint32_t redist1_capacity =
768 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
769
770 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
771 MIN(smp_cpus - redist0_count, redist1_capacity));
772 }
773 } else {
774 if (!kvm_irqchip_in_kernel()) {
775 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
776 vms->virt);
777 }
778 }
779 gicbusdev = SYS_BUS_DEVICE(vms->gic);
780 sysbus_realize_and_unref(gicbusdev, &error_fatal);
781 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
782 if (vms->gic_version != VIRT_GIC_VERSION_2) {
783 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
784 if (nb_redist_regions == 2) {
785 sysbus_mmio_map(gicbusdev, 2,
786 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
787 }
788 } else {
789 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
790 if (vms->virt) {
791 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
792 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
793 }
794 }
795
796
797
798
799
800 for (i = 0; i < smp_cpus; i++) {
801 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
802 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
803 int irq;
804
805
806
807 const int timer_irq[] = {
808 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
809 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
810 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
811 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
812 };
813
814 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
815 qdev_connect_gpio_out(cpudev, irq,
816 qdev_get_gpio_in(vms->gic,
817 ppibase + timer_irq[irq]));
818 }
819
820 if (vms->gic_version != VIRT_GIC_VERSION_2) {
821 qemu_irq irq = qdev_get_gpio_in(vms->gic,
822 ppibase + ARCH_GIC_MAINT_IRQ);
823 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
824 0, irq);
825 } else if (vms->virt) {
826 qemu_irq irq = qdev_get_gpio_in(vms->gic,
827 ppibase + ARCH_GIC_MAINT_IRQ);
828 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
829 }
830
831 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
832 qdev_get_gpio_in(vms->gic, ppibase
833 + VIRTUAL_PMU_IRQ));
834
835 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
836 sysbus_connect_irq(gicbusdev, i + smp_cpus,
837 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
838 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
839 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
840 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
841 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
842 }
843
844 fdt_add_gic_node(vms);
845
846 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
847 create_its(vms);
848 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
849 create_v2m(vms);
850 }
851}
852
853static void create_uart(const VirtMachineState *vms, int uart,
854 MemoryRegion *mem, Chardev *chr)
855{
856 char *nodename;
857 hwaddr base = vms->memmap[uart].base;
858 hwaddr size = vms->memmap[uart].size;
859 int irq = vms->irqmap[uart];
860 const char compat[] = "arm,pl011\0arm,primecell";
861 const char clocknames[] = "uartclk\0apb_pclk";
862 DeviceState *dev = qdev_new(TYPE_PL011);
863 SysBusDevice *s = SYS_BUS_DEVICE(dev);
864 MachineState *ms = MACHINE(vms);
865
866 qdev_prop_set_chr(dev, "chardev", chr);
867 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
868 memory_region_add_subregion(mem, base,
869 sysbus_mmio_get_region(s, 0));
870 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
871
872 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
873 qemu_fdt_add_subnode(ms->fdt, nodename);
874
875 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
876 compat, sizeof(compat));
877 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
878 2, base, 2, size);
879 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
880 GIC_FDT_IRQ_TYPE_SPI, irq,
881 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
882 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
883 vms->clock_phandle, vms->clock_phandle);
884 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
885 clocknames, sizeof(clocknames));
886
887 if (uart == VIRT_UART) {
888 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
889 } else {
890
891 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
892 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
893
894 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
895 nodename);
896 }
897
898 g_free(nodename);
899}
900
901static void create_rtc(const VirtMachineState *vms)
902{
903 char *nodename;
904 hwaddr base = vms->memmap[VIRT_RTC].base;
905 hwaddr size = vms->memmap[VIRT_RTC].size;
906 int irq = vms->irqmap[VIRT_RTC];
907 const char compat[] = "arm,pl031\0arm,primecell";
908 MachineState *ms = MACHINE(vms);
909
910 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
911
912 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
913 qemu_fdt_add_subnode(ms->fdt, nodename);
914 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
915 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
916 2, base, 2, size);
917 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
918 GIC_FDT_IRQ_TYPE_SPI, irq,
919 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
920 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
921 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
922 g_free(nodename);
923}
924
925static DeviceState *gpio_key_dev;
926static void virt_powerdown_req(Notifier *n, void *opaque)
927{
928 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
929
930 if (s->acpi_dev) {
931 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
932 } else {
933
934 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
935 }
936}
937
938static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
939 uint32_t phandle)
940{
941 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
942 qdev_get_gpio_in(pl061_dev, 3));
943
944 qemu_fdt_add_subnode(fdt, "/gpio-keys");
945 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
946
947 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
948 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
949 "label", "GPIO Key Poweroff");
950 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
951 KEY_POWER);
952 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
953 "gpios", phandle, 3, 0);
954}
955
956#define SECURE_GPIO_POWEROFF 0
957#define SECURE_GPIO_RESET 1
958
959static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
960 uint32_t phandle)
961{
962 DeviceState *gpio_pwr_dev;
963
964
965 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
966
967
968 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
969 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
970 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
971 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
972
973 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
974 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
975 "gpio-poweroff");
976 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
977 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
978 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
979 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
980 "okay");
981
982 qemu_fdt_add_subnode(fdt, "/gpio-restart");
983 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
984 "gpio-restart");
985 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
986 "gpios", phandle, SECURE_GPIO_RESET, 0);
987 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
988 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
989 "okay");
990}
991
992static void create_gpio_devices(const VirtMachineState *vms, int gpio,
993 MemoryRegion *mem)
994{
995 char *nodename;
996 DeviceState *pl061_dev;
997 hwaddr base = vms->memmap[gpio].base;
998 hwaddr size = vms->memmap[gpio].size;
999 int irq = vms->irqmap[gpio];
1000 const char compat[] = "arm,pl061\0arm,primecell";
1001 SysBusDevice *s;
1002 MachineState *ms = MACHINE(vms);
1003
1004 pl061_dev = qdev_new("pl061");
1005
1006 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
1007 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
1008 s = SYS_BUS_DEVICE(pl061_dev);
1009 sysbus_realize_and_unref(s, &error_fatal);
1010 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1011 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1012
1013 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1014 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1015 qemu_fdt_add_subnode(ms->fdt, nodename);
1016 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1017 2, base, 2, size);
1018 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1019 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1020 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1021 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1022 GIC_FDT_IRQ_TYPE_SPI, irq,
1023 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1024 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1025 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1026 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1027
1028 if (gpio != VIRT_GPIO) {
1029
1030 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1031 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1032 }
1033 g_free(nodename);
1034
1035
1036 if (gpio == VIRT_GPIO) {
1037 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1038 } else {
1039 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1040 }
1041}
1042
1043static void create_virtio_devices(const VirtMachineState *vms)
1044{
1045 int i;
1046 hwaddr size = vms->memmap[VIRT_MMIO].size;
1047 MachineState *ms = MACHINE(vms);
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1077 int irq = vms->irqmap[VIRT_MMIO] + i;
1078 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1079
1080 sysbus_create_simple("virtio-mmio", base,
1081 qdev_get_gpio_in(vms->gic, irq));
1082 }
1083
1084
1085
1086
1087
1088
1089
1090
1091 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1092 char *nodename;
1093 int irq = vms->irqmap[VIRT_MMIO] + i;
1094 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1095
1096 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1097 qemu_fdt_add_subnode(ms->fdt, nodename);
1098 qemu_fdt_setprop_string(ms->fdt, nodename,
1099 "compatible", "virtio,mmio");
1100 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1101 2, base, 2, size);
1102 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1103 GIC_FDT_IRQ_TYPE_SPI, irq,
1104 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1105 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1106 g_free(nodename);
1107 }
1108}
1109
1110#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1111
1112static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1113 const char *name,
1114 const char *alias_prop_name)
1115{
1116
1117
1118
1119
1120 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1121
1122 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1123 qdev_prop_set_uint8(dev, "width", 4);
1124 qdev_prop_set_uint8(dev, "device-width", 2);
1125 qdev_prop_set_bit(dev, "big-endian", false);
1126 qdev_prop_set_uint16(dev, "id0", 0x89);
1127 qdev_prop_set_uint16(dev, "id1", 0x18);
1128 qdev_prop_set_uint16(dev, "id2", 0x00);
1129 qdev_prop_set_uint16(dev, "id3", 0x00);
1130 qdev_prop_set_string(dev, "name", name);
1131 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1132 object_property_add_alias(OBJECT(vms), alias_prop_name,
1133 OBJECT(dev), "drive");
1134 return PFLASH_CFI01(dev);
1135}
1136
1137static void virt_flash_create(VirtMachineState *vms)
1138{
1139 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1140 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1141}
1142
1143static void virt_flash_map1(PFlashCFI01 *flash,
1144 hwaddr base, hwaddr size,
1145 MemoryRegion *sysmem)
1146{
1147 DeviceState *dev = DEVICE(flash);
1148
1149 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1150 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1151 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1152 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1153
1154 memory_region_add_subregion(sysmem, base,
1155 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1156 0));
1157}
1158
1159static void virt_flash_map(VirtMachineState *vms,
1160 MemoryRegion *sysmem,
1161 MemoryRegion *secure_sysmem)
1162{
1163
1164
1165
1166
1167
1168
1169
1170
1171 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1172 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1173
1174 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1175 secure_sysmem);
1176 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1177 sysmem);
1178}
1179
1180static void virt_flash_fdt(VirtMachineState *vms,
1181 MemoryRegion *sysmem,
1182 MemoryRegion *secure_sysmem)
1183{
1184 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1185 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1186 MachineState *ms = MACHINE(vms);
1187 char *nodename;
1188
1189 if (sysmem == secure_sysmem) {
1190
1191 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1192 qemu_fdt_add_subnode(ms->fdt, nodename);
1193 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1194 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1195 2, flashbase, 2, flashsize,
1196 2, flashbase + flashsize, 2, flashsize);
1197 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1198 g_free(nodename);
1199 } else {
1200
1201
1202
1203
1204 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1205 qemu_fdt_add_subnode(ms->fdt, nodename);
1206 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1207 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1208 2, flashbase, 2, flashsize);
1209 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1210 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1211 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1212 g_free(nodename);
1213
1214 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1215 qemu_fdt_add_subnode(ms->fdt, nodename);
1216 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1217 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1218 2, flashbase + flashsize, 2, flashsize);
1219 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1220 g_free(nodename);
1221 }
1222}
1223
1224static bool virt_firmware_init(VirtMachineState *vms,
1225 MemoryRegion *sysmem,
1226 MemoryRegion *secure_sysmem)
1227{
1228 int i;
1229 const char *bios_name;
1230 BlockBackend *pflash_blk0;
1231
1232
1233 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1234 pflash_cfi01_legacy_drive(vms->flash[i],
1235 drive_get(IF_PFLASH, 0, i));
1236 }
1237
1238 virt_flash_map(vms, sysmem, secure_sysmem);
1239
1240 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1241
1242 bios_name = MACHINE(vms)->firmware;
1243 if (bios_name) {
1244 char *fname;
1245 MemoryRegion *mr;
1246 int image_size;
1247
1248 if (pflash_blk0) {
1249 error_report("The contents of the first flash device may be "
1250 "specified with -bios or with -drive if=pflash... "
1251 "but you cannot use both options at once");
1252 exit(1);
1253 }
1254
1255
1256
1257 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1258 if (!fname) {
1259 error_report("Could not find ROM image '%s'", bios_name);
1260 exit(1);
1261 }
1262 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1263 image_size = load_image_mr(fname, mr);
1264 g_free(fname);
1265 if (image_size < 0) {
1266 error_report("Could not load ROM image '%s'", bios_name);
1267 exit(1);
1268 }
1269 }
1270
1271 return pflash_blk0 || bios_name;
1272}
1273
1274static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1275{
1276 MachineState *ms = MACHINE(vms);
1277 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1278 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1279 FWCfgState *fw_cfg;
1280 char *nodename;
1281
1282 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1283 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1284
1285 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1286 qemu_fdt_add_subnode(ms->fdt, nodename);
1287 qemu_fdt_setprop_string(ms->fdt, nodename,
1288 "compatible", "qemu,fw-cfg-mmio");
1289 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1290 2, base, 2, size);
1291 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1292 g_free(nodename);
1293 return fw_cfg;
1294}
1295
1296static void create_pcie_irq_map(const MachineState *ms,
1297 uint32_t gic_phandle,
1298 int first_irq, const char *nodename)
1299{
1300 int devfn, pin;
1301 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1302 uint32_t *irq_map = full_irq_map;
1303
1304 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1305 for (pin = 0; pin < 4; pin++) {
1306 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1307 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1308 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1309 int i;
1310
1311 uint32_t map[] = {
1312 devfn << 8, 0, 0,
1313 pin + 1,
1314 gic_phandle, 0, 0, irq_type, irq_nr, irq_level };
1315
1316
1317 for (i = 0; i < 10; i++) {
1318 irq_map[i] = cpu_to_be32(map[i]);
1319 }
1320 irq_map += 10;
1321 }
1322 }
1323
1324 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1325 full_irq_map, sizeof(full_irq_map));
1326
1327 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1328 cpu_to_be16(PCI_DEVFN(3, 0)),
1329 0, 0,
1330 0x7 );
1331}
1332
1333static void create_smmu(const VirtMachineState *vms,
1334 PCIBus *bus)
1335{
1336 char *node;
1337 const char compat[] = "arm,smmu-v3";
1338 int irq = vms->irqmap[VIRT_SMMU];
1339 int i;
1340 hwaddr base = vms->memmap[VIRT_SMMU].base;
1341 hwaddr size = vms->memmap[VIRT_SMMU].size;
1342 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1343 DeviceState *dev;
1344 MachineState *ms = MACHINE(vms);
1345
1346 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1347 return;
1348 }
1349
1350 dev = qdev_new(TYPE_ARM_SMMUV3);
1351
1352 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1353 &error_abort);
1354 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1355 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1357 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1358 qdev_get_gpio_in(vms->gic, irq + i));
1359 }
1360
1361 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1362 qemu_fdt_add_subnode(ms->fdt, node);
1363 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1364 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1365
1366 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1367 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1368 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1369 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1370 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1371
1372 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1373 sizeof(irq_names));
1374
1375 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1376
1377 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1378
1379 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1380 g_free(node);
1381}
1382
1383static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1384{
1385 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1386 uint16_t bdf = vms->virtio_iommu_bdf;
1387 MachineState *ms = MACHINE(vms);
1388 char *node;
1389
1390 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1391
1392 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1393 PCI_SLOT(bdf), PCI_FUNC(bdf));
1394 qemu_fdt_add_subnode(ms->fdt, node);
1395 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1396 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1397 1, bdf << 8, 1, 0, 1, 0,
1398 1, 0, 1, 0);
1399
1400 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1401 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1402 g_free(node);
1403
1404 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1405 0x0, vms->iommu_phandle, 0x0, bdf,
1406 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1407}
1408
1409static void create_pcie(VirtMachineState *vms)
1410{
1411 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1412 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1413 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1414 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1415 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1416 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1417 hwaddr base_ecam, size_ecam;
1418 hwaddr base = base_mmio;
1419 int nr_pcie_buses;
1420 int irq = vms->irqmap[VIRT_PCIE];
1421 MemoryRegion *mmio_alias;
1422 MemoryRegion *mmio_reg;
1423 MemoryRegion *ecam_alias;
1424 MemoryRegion *ecam_reg;
1425 DeviceState *dev;
1426 char *nodename;
1427 int i, ecam_id;
1428 PCIHostState *pci;
1429 MachineState *ms = MACHINE(vms);
1430 MachineClass *mc = MACHINE_GET_CLASS(ms);
1431
1432 dev = qdev_new(TYPE_GPEX_HOST);
1433 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1434
1435 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1436 base_ecam = vms->memmap[ecam_id].base;
1437 size_ecam = vms->memmap[ecam_id].size;
1438 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1439
1440 ecam_alias = g_new0(MemoryRegion, 1);
1441 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1442 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1443 ecam_reg, 0, size_ecam);
1444 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1445
1446
1447
1448
1449
1450
1451 mmio_alias = g_new0(MemoryRegion, 1);
1452 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1453 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1454 mmio_reg, base_mmio, size_mmio);
1455 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1456
1457 if (vms->highmem_mmio) {
1458
1459 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1460
1461 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1462 mmio_reg, base_mmio_high, size_mmio_high);
1463 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1464 high_mmio_alias);
1465 }
1466
1467
1468 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1469
1470 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1471 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1472 qdev_get_gpio_in(vms->gic, irq + i));
1473 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1474 }
1475
1476 pci = PCI_HOST_BRIDGE(dev);
1477 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1478 vms->bus = pci->bus;
1479 if (vms->bus) {
1480 for (i = 0; i < nb_nics; i++) {
1481 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL);
1482 }
1483 }
1484
1485 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1486 qemu_fdt_add_subnode(ms->fdt, nodename);
1487 qemu_fdt_setprop_string(ms->fdt, nodename,
1488 "compatible", "pci-host-ecam-generic");
1489 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1490 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1491 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1492 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1493 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1494 nr_pcie_buses - 1);
1495 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1496
1497 if (vms->msi_phandle) {
1498 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1499 0, vms->msi_phandle, 0, 0x10000);
1500 }
1501
1502 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1503 2, base_ecam, 2, size_ecam);
1504
1505 if (vms->highmem_mmio) {
1506 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1507 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1508 2, base_pio, 2, size_pio,
1509 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1510 2, base_mmio, 2, size_mmio,
1511 1, FDT_PCI_RANGE_MMIO_64BIT,
1512 2, base_mmio_high,
1513 2, base_mmio_high, 2, size_mmio_high);
1514 } else {
1515 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1516 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1517 2, base_pio, 2, size_pio,
1518 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1519 2, base_mmio, 2, size_mmio);
1520 }
1521
1522 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1523 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1524
1525 if (vms->iommu) {
1526 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1527
1528 switch (vms->iommu) {
1529 case VIRT_IOMMU_SMMUV3:
1530 create_smmu(vms, vms->bus);
1531 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1532 0x0, vms->iommu_phandle, 0x0, 0x10000);
1533 break;
1534 default:
1535 g_assert_not_reached();
1536 }
1537 }
1538}
1539
1540static void create_platform_bus(VirtMachineState *vms)
1541{
1542 DeviceState *dev;
1543 SysBusDevice *s;
1544 int i;
1545 MemoryRegion *sysmem = get_system_memory();
1546
1547 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1548 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1549 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1550 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1551 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1552 vms->platform_bus_dev = dev;
1553
1554 s = SYS_BUS_DEVICE(dev);
1555 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1556 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1557 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1558 }
1559
1560 memory_region_add_subregion(sysmem,
1561 vms->memmap[VIRT_PLATFORM_BUS].base,
1562 sysbus_mmio_get_region(s, 0));
1563}
1564
1565static void create_tag_ram(MemoryRegion *tag_sysmem,
1566 hwaddr base, hwaddr size,
1567 const char *name)
1568{
1569 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1570
1571 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1572 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1573}
1574
1575static void create_secure_ram(VirtMachineState *vms,
1576 MemoryRegion *secure_sysmem,
1577 MemoryRegion *secure_tag_sysmem)
1578{
1579 MemoryRegion *secram = g_new(MemoryRegion, 1);
1580 char *nodename;
1581 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1582 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1583 MachineState *ms = MACHINE(vms);
1584
1585 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1586 &error_fatal);
1587 memory_region_add_subregion(secure_sysmem, base, secram);
1588
1589 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1590 qemu_fdt_add_subnode(ms->fdt, nodename);
1591 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1592 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1593 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1594 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1595
1596 if (secure_tag_sysmem) {
1597 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1598 }
1599
1600 g_free(nodename);
1601}
1602
1603static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1604{
1605 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1606 bootinfo);
1607 MachineState *ms = MACHINE(board);
1608
1609
1610 *fdt_size = board->fdt_size;
1611 return ms->fdt;
1612}
1613
1614static void virt_build_smbios(VirtMachineState *vms)
1615{
1616 MachineClass *mc = MACHINE_GET_CLASS(vms);
1617 MachineState *ms = MACHINE(vms);
1618 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1619 uint8_t *smbios_tables, *smbios_anchor;
1620 size_t smbios_tables_len, smbios_anchor_len;
1621 struct smbios_phys_mem_area mem_array;
1622 const char *product = "QEMU Virtual Machine";
1623
1624 if (kvm_enabled()) {
1625 product = "KVM Virtual Machine";
1626 }
1627
1628 smbios_set_defaults("QEMU", product,
1629 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1630 true, SMBIOS_ENTRY_POINT_TYPE_64);
1631
1632
1633 mem_array.address = vms->memmap[VIRT_MEM].base;
1634 mem_array.length = ms->ram_size;
1635
1636 smbios_get_tables(ms, &mem_array, 1,
1637 &smbios_tables, &smbios_tables_len,
1638 &smbios_anchor, &smbios_anchor_len,
1639 &error_fatal);
1640
1641 if (smbios_anchor) {
1642 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1643 smbios_tables, smbios_tables_len);
1644 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1645 smbios_anchor, smbios_anchor_len);
1646 }
1647}
1648
1649static
1650void virt_machine_done(Notifier *notifier, void *data)
1651{
1652 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1653 machine_done);
1654 MachineState *ms = MACHINE(vms);
1655 ARMCPU *cpu = ARM_CPU(first_cpu);
1656 struct arm_boot_info *info = &vms->bootinfo;
1657 AddressSpace *as = arm_boot_address_space(cpu, info);
1658
1659
1660
1661
1662
1663
1664
1665
1666 if (info->dtb_filename == NULL) {
1667 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1668 vms->memmap[VIRT_PLATFORM_BUS].base,
1669 vms->memmap[VIRT_PLATFORM_BUS].size,
1670 vms->irqmap[VIRT_PLATFORM_BUS]);
1671 }
1672 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1673 exit(1);
1674 }
1675
1676 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1677
1678 virt_acpi_setup(vms);
1679 virt_build_smbios(vms);
1680}
1681
1682static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1683{
1684 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1685 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1686
1687 if (!vmc->disallow_affinity_adjustment) {
1688
1689
1690
1691
1692
1693
1694
1695
1696 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1697 clustersz = GIC_TARGETLIST_BITS;
1698 } else {
1699 clustersz = GICV3_TARGETLIST_BITS;
1700 }
1701 }
1702 return arm_cpu_mp_affinity(idx, clustersz);
1703}
1704
1705static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
1706 int index)
1707{
1708 bool *enabled_array[] = {
1709 &vms->highmem_redists,
1710 &vms->highmem_ecam,
1711 &vms->highmem_mmio,
1712 };
1713
1714 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1715 ARRAY_SIZE(enabled_array));
1716 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1717
1718 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1719}
1720
1721static void virt_set_high_memmap(VirtMachineState *vms,
1722 hwaddr base, int pa_bits)
1723{
1724 hwaddr region_base, region_size;
1725 bool *region_enabled, fits;
1726 int i;
1727
1728 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1729 region_enabled = virt_get_high_memmap_enabled(vms, i);
1730 region_base = ROUND_UP(base, extended_memmap[i].size);
1731 region_size = extended_memmap[i].size;
1732
1733 vms->memmap[i].base = region_base;
1734 vms->memmap[i].size = region_size;
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744 fits = (region_base + region_size) <= BIT_ULL(pa_bits);
1745 *region_enabled &= fits;
1746 if (vms->highmem_compact && !*region_enabled) {
1747 continue;
1748 }
1749
1750 base = region_base + region_size;
1751 if (fits) {
1752 vms->highest_gpa = base - 1;
1753 }
1754 }
1755}
1756
1757static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1758{
1759 MachineState *ms = MACHINE(vms);
1760 hwaddr base, device_memory_base, device_memory_size, memtop;
1761 int i;
1762
1763 vms->memmap = extended_memmap;
1764
1765 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1766 vms->memmap[i] = base_memmap[i];
1767 }
1768
1769 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1770 error_report("unsupported number of memory slots: %"PRIu64,
1771 ms->ram_slots);
1772 exit(EXIT_FAILURE);
1773 }
1774
1775
1776
1777
1778
1779 if (!vms->highmem) {
1780 pa_bits = 32;
1781 }
1782
1783
1784
1785
1786
1787
1788
1789
1790 device_memory_base =
1791 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1792 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1793
1794
1795 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1796 if (memtop > BIT_ULL(pa_bits)) {
1797 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1798 pa_bits, memtop - BIT_ULL(pa_bits));
1799 exit(EXIT_FAILURE);
1800 }
1801 if (base < device_memory_base) {
1802 error_report("maxmem/slots too huge");
1803 exit(EXIT_FAILURE);
1804 }
1805 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1806 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1807 }
1808
1809
1810 vms->highest_gpa = memtop - 1;
1811
1812 virt_set_high_memmap(vms, base, pa_bits);
1813
1814 if (device_memory_size > 0) {
1815 machine_memory_devices_init(ms, device_memory_base, device_memory_size);
1816 }
1817}
1818
1819static VirtGICType finalize_gic_version_do(const char *accel_name,
1820 VirtGICType gic_version,
1821 int gics_supported,
1822 unsigned int max_cpus)
1823{
1824
1825 switch (gic_version) {
1826 case VIRT_GIC_VERSION_HOST:
1827 if (!kvm_enabled()) {
1828 error_report("gic-version=host requires KVM");
1829 exit(1);
1830 }
1831
1832
1833 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
1834 gics_supported, max_cpus);
1835 case VIRT_GIC_VERSION_MAX:
1836 if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
1837 gic_version = VIRT_GIC_VERSION_4;
1838 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1839 gic_version = VIRT_GIC_VERSION_3;
1840 } else {
1841 gic_version = VIRT_GIC_VERSION_2;
1842 }
1843 break;
1844 case VIRT_GIC_VERSION_NOSEL:
1845 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
1846 max_cpus <= GIC_NCPU) {
1847 gic_version = VIRT_GIC_VERSION_2;
1848 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1849
1850
1851
1852
1853
1854 gic_version = VIRT_GIC_VERSION_3;
1855 } else if (max_cpus > GIC_NCPU) {
1856 error_report("%s only supports GICv2 emulation but more than 8 "
1857 "vcpus are requested", accel_name);
1858 exit(1);
1859 }
1860 break;
1861 case VIRT_GIC_VERSION_2:
1862 case VIRT_GIC_VERSION_3:
1863 case VIRT_GIC_VERSION_4:
1864 break;
1865 }
1866
1867
1868 switch (gic_version) {
1869 case VIRT_GIC_VERSION_2:
1870 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
1871 error_report("%s does not support GICv2 emulation", accel_name);
1872 exit(1);
1873 }
1874 break;
1875 case VIRT_GIC_VERSION_3:
1876 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
1877 error_report("%s does not support GICv3 emulation", accel_name);
1878 exit(1);
1879 }
1880 break;
1881 case VIRT_GIC_VERSION_4:
1882 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
1883 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1884 accel_name);
1885 exit(1);
1886 }
1887 break;
1888 default:
1889 error_report("logic error in finalize_gic_version");
1890 exit(1);
1891 break;
1892 }
1893
1894 return gic_version;
1895}
1896
1897
1898
1899
1900
1901
1902
1903static void finalize_gic_version(VirtMachineState *vms)
1904{
1905 const char *accel_name = current_accel_name();
1906 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1907 int gics_supported = 0;
1908
1909
1910 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1911 int probe_bitmap = kvm_arm_vgic_probe();
1912
1913 if (!probe_bitmap) {
1914 error_report("Unable to determine GIC version supported by host");
1915 exit(1);
1916 }
1917
1918 if (probe_bitmap & KVM_ARM_VGIC_V2) {
1919 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1920 }
1921 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1922 gics_supported |= VIRT_GIC_VERSION_3_MASK;
1923 }
1924 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1925
1926 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1927 accel_name = "KVM with kernel-irqchip=off";
1928 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
1929 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1930 if (module_object_class_by_name("arm-gicv3")) {
1931 gics_supported |= VIRT_GIC_VERSION_3_MASK;
1932 if (vms->virt) {
1933
1934 gics_supported |= VIRT_GIC_VERSION_4_MASK;
1935 }
1936 }
1937 } else {
1938 error_report("Unsupported accelerator, can not determine GIC support");
1939 exit(1);
1940 }
1941
1942
1943
1944
1945
1946 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
1947 gics_supported, max_cpus);
1948}
1949
1950
1951
1952
1953
1954static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1955{
1956 int max_cpus = MACHINE(vms)->smp.max_cpus;
1957 bool aarch64, pmu, steal_time;
1958 CPUState *cpu;
1959
1960 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1961 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1962 steal_time = object_property_get_bool(OBJECT(first_cpu),
1963 "kvm-steal-time", NULL);
1964
1965 if (kvm_enabled()) {
1966 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1967 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1968
1969 if (steal_time) {
1970 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1971 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1972
1973
1974 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1975
1976 if (pvtime_size > pvtime_reg_size) {
1977 error_report("pvtime requires a %" HWADDR_PRId
1978 " byte memory region for %d CPUs,"
1979 " but only %" HWADDR_PRId " has been reserved",
1980 pvtime_size, max_cpus, pvtime_reg_size);
1981 exit(1);
1982 }
1983
1984 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1985 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1986 }
1987
1988 CPU_FOREACH(cpu) {
1989 if (pmu) {
1990 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1991 if (kvm_irqchip_in_kernel()) {
1992 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1993 }
1994 kvm_arm_pmu_init(cpu);
1995 }
1996 if (steal_time) {
1997 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1998 cpu->cpu_index * PVTIME_SIZE_PER_CPU);
1999 }
2000 }
2001 } else {
2002 if (aarch64 && vms->highmem) {
2003 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2004 int pamax = arm_pamax(ARM_CPU(first_cpu));
2005
2006 if (pamax < requested_pa_size) {
2007 error_report("VCPU supports less PA bits (%d) than "
2008 "requested by the memory map (%d)",
2009 pamax, requested_pa_size);
2010 exit(1);
2011 }
2012 }
2013 }
2014}
2015
2016static void machvirt_init(MachineState *machine)
2017{
2018 VirtMachineState *vms = VIRT_MACHINE(machine);
2019 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2020 MachineClass *mc = MACHINE_GET_CLASS(machine);
2021 const CPUArchIdList *possible_cpus;
2022 MemoryRegion *sysmem = get_system_memory();
2023 MemoryRegion *secure_sysmem = NULL;
2024 MemoryRegion *tag_sysmem = NULL;
2025 MemoryRegion *secure_tag_sysmem = NULL;
2026 int n, virt_max_cpus;
2027 bool firmware_loaded;
2028 bool aarch64 = true;
2029 bool has_ged = !vmc->no_ged;
2030 unsigned int smp_cpus = machine->smp.cpus;
2031 unsigned int max_cpus = machine->smp.max_cpus;
2032
2033 if (!cpu_type_valid(machine->cpu_type)) {
2034 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
2035 exit(1);
2036 }
2037
2038 possible_cpus = mc->possible_cpu_arch_ids(machine);
2039
2040
2041
2042
2043
2044 if (!vms->memmap) {
2045 Object *cpuobj;
2046 ARMCPU *armcpu;
2047 int pa_bits;
2048
2049
2050
2051
2052
2053
2054 cpuobj = object_new(possible_cpus->cpus[0].type);
2055 armcpu = ARM_CPU(cpuobj);
2056
2057 pa_bits = arm_pamax(armcpu);
2058
2059 object_unref(cpuobj);
2060
2061 virt_set_memmap(vms, pa_bits);
2062 }
2063
2064
2065
2066
2067 finalize_gic_version(vms);
2068
2069 if (vms->secure) {
2070
2071
2072
2073
2074
2075
2076 secure_sysmem = g_new(MemoryRegion, 1);
2077 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2078 UINT64_MAX);
2079 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2080 }
2081
2082 firmware_loaded = virt_firmware_init(vms, sysmem,
2083 secure_sysmem ?: sysmem);
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095 if (vms->secure && firmware_loaded) {
2096 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2097 } else if (vms->virt) {
2098 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2099 } else {
2100 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2101 }
2102
2103
2104
2105
2106
2107
2108 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2109 virt_max_cpus = GIC_NCPU;
2110 } else {
2111 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2112 if (vms->highmem_redists) {
2113 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2114 }
2115 }
2116
2117 if (max_cpus > virt_max_cpus) {
2118 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2119 "supported by machine 'mach-virt' (%d)",
2120 max_cpus, virt_max_cpus);
2121 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2122 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2123 }
2124
2125 exit(1);
2126 }
2127
2128 if (vms->secure && (kvm_enabled() || hvf_enabled())) {
2129 error_report("mach-virt: %s does not support providing "
2130 "Security extensions (TrustZone) to the guest CPU",
2131 current_accel_name());
2132 exit(1);
2133 }
2134
2135 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
2136 error_report("mach-virt: %s does not support providing "
2137 "Virtualization extensions to the guest CPU",
2138 current_accel_name());
2139 exit(1);
2140 }
2141
2142 if (vms->mte && (kvm_enabled() || hvf_enabled())) {
2143 error_report("mach-virt: %s does not support providing "
2144 "MTE to the guest CPU",
2145 current_accel_name());
2146 exit(1);
2147 }
2148
2149 create_fdt(vms);
2150
2151 assert(possible_cpus->len == max_cpus);
2152 for (n = 0; n < possible_cpus->len; n++) {
2153 Object *cpuobj;
2154 CPUState *cs;
2155
2156 if (n >= smp_cpus) {
2157 break;
2158 }
2159
2160 cpuobj = object_new(possible_cpus->cpus[n].type);
2161 object_property_set_int(cpuobj, "mp-affinity",
2162 possible_cpus->cpus[n].arch_id, NULL);
2163
2164 cs = CPU(cpuobj);
2165 cs->cpu_index = n;
2166
2167 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2168 &error_fatal);
2169
2170 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2171
2172 if (!vms->secure) {
2173 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2174 }
2175
2176 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2177 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2178 }
2179
2180 if (vmc->kvm_no_adjvtime &&
2181 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2182 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2183 }
2184
2185 if (vmc->no_kvm_steal_time &&
2186 object_property_find(cpuobj, "kvm-steal-time")) {
2187 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2188 }
2189
2190 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2191 object_property_set_bool(cpuobj, "pmu", false, NULL);
2192 }
2193
2194 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2195 object_property_set_bool(cpuobj, "lpa2", false, NULL);
2196 }
2197
2198 if (object_property_find(cpuobj, "reset-cbar")) {
2199 object_property_set_int(cpuobj, "reset-cbar",
2200 vms->memmap[VIRT_CPUPERIPHS].base,
2201 &error_abort);
2202 }
2203
2204 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2205 &error_abort);
2206 if (vms->secure) {
2207 object_property_set_link(cpuobj, "secure-memory",
2208 OBJECT(secure_sysmem), &error_abort);
2209 }
2210
2211 if (vms->mte) {
2212
2213 if (!tag_sysmem) {
2214
2215
2216
2217
2218 if (!object_property_find(cpuobj, "tag-memory")) {
2219 error_report("MTE requested, but not supported "
2220 "by the guest CPU");
2221 exit(1);
2222 }
2223
2224 tag_sysmem = g_new(MemoryRegion, 1);
2225 memory_region_init(tag_sysmem, OBJECT(machine),
2226 "tag-memory", UINT64_MAX / 32);
2227
2228 if (vms->secure) {
2229 secure_tag_sysmem = g_new(MemoryRegion, 1);
2230 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2231 "secure-tag-memory", UINT64_MAX / 32);
2232
2233
2234 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2235 tag_sysmem, -1);
2236 }
2237 }
2238
2239 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2240 &error_abort);
2241 if (vms->secure) {
2242 object_property_set_link(cpuobj, "secure-tag-memory",
2243 OBJECT(secure_tag_sysmem),
2244 &error_abort);
2245 }
2246 }
2247
2248 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2249 object_unref(cpuobj);
2250 }
2251 fdt_add_timer_nodes(vms);
2252 fdt_add_cpu_nodes(vms);
2253
2254 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2255 machine->ram);
2256
2257 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2258
2259 create_gic(vms, sysmem);
2260
2261 virt_cpu_post_init(vms, sysmem);
2262
2263 fdt_add_pmu_nodes(vms);
2264
2265 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2266
2267 if (vms->secure) {
2268 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2269 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2270 }
2271
2272 if (tag_sysmem) {
2273 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2274 machine->ram_size, "mach-virt.tag");
2275 }
2276
2277 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2278
2279 create_rtc(vms);
2280
2281 create_pcie(vms);
2282
2283 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2284 vms->acpi_dev = create_acpi_ged(vms);
2285 } else {
2286 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2287 }
2288
2289 if (vms->secure && !vmc->no_secure_gpio) {
2290 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2291 }
2292
2293
2294 vms->powerdown_notifier.notify = virt_powerdown_req;
2295 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2296
2297
2298
2299
2300
2301 create_virtio_devices(vms);
2302
2303 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2304 rom_set_fw(vms->fw_cfg);
2305
2306 create_platform_bus(vms);
2307
2308 if (machine->nvdimms_state->is_enabled) {
2309 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2310 .space_id = AML_AS_SYSTEM_MEMORY,
2311 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2312 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2313 };
2314
2315 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2316 arm_virt_nvdimm_acpi_dsmio,
2317 vms->fw_cfg, OBJECT(vms));
2318 }
2319
2320 vms->bootinfo.ram_size = machine->ram_size;
2321 vms->bootinfo.board_id = -1;
2322 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2323 vms->bootinfo.get_dtb = machvirt_dtb;
2324 vms->bootinfo.skip_dtb_autoload = true;
2325 vms->bootinfo.firmware_loaded = firmware_loaded;
2326 vms->bootinfo.psci_conduit = vms->psci_conduit;
2327 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2328
2329 vms->machine_done.notify = virt_machine_done;
2330 qemu_add_machine_init_done_notifier(&vms->machine_done);
2331}
2332
2333static bool virt_get_secure(Object *obj, Error **errp)
2334{
2335 VirtMachineState *vms = VIRT_MACHINE(obj);
2336
2337 return vms->secure;
2338}
2339
2340static void virt_set_secure(Object *obj, bool value, Error **errp)
2341{
2342 VirtMachineState *vms = VIRT_MACHINE(obj);
2343
2344 vms->secure = value;
2345}
2346
2347static bool virt_get_virt(Object *obj, Error **errp)
2348{
2349 VirtMachineState *vms = VIRT_MACHINE(obj);
2350
2351 return vms->virt;
2352}
2353
2354static void virt_set_virt(Object *obj, bool value, Error **errp)
2355{
2356 VirtMachineState *vms = VIRT_MACHINE(obj);
2357
2358 vms->virt = value;
2359}
2360
2361static bool virt_get_highmem(Object *obj, Error **errp)
2362{
2363 VirtMachineState *vms = VIRT_MACHINE(obj);
2364
2365 return vms->highmem;
2366}
2367
2368static void virt_set_highmem(Object *obj, bool value, Error **errp)
2369{
2370 VirtMachineState *vms = VIRT_MACHINE(obj);
2371
2372 vms->highmem = value;
2373}
2374
2375static bool virt_get_compact_highmem(Object *obj, Error **errp)
2376{
2377 VirtMachineState *vms = VIRT_MACHINE(obj);
2378
2379 return vms->highmem_compact;
2380}
2381
2382static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
2383{
2384 VirtMachineState *vms = VIRT_MACHINE(obj);
2385
2386 vms->highmem_compact = value;
2387}
2388
2389static bool virt_get_highmem_redists(Object *obj, Error **errp)
2390{
2391 VirtMachineState *vms = VIRT_MACHINE(obj);
2392
2393 return vms->highmem_redists;
2394}
2395
2396static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
2397{
2398 VirtMachineState *vms = VIRT_MACHINE(obj);
2399
2400 vms->highmem_redists = value;
2401}
2402
2403static bool virt_get_highmem_ecam(Object *obj, Error **errp)
2404{
2405 VirtMachineState *vms = VIRT_MACHINE(obj);
2406
2407 return vms->highmem_ecam;
2408}
2409
2410static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
2411{
2412 VirtMachineState *vms = VIRT_MACHINE(obj);
2413
2414 vms->highmem_ecam = value;
2415}
2416
2417static bool virt_get_highmem_mmio(Object *obj, Error **errp)
2418{
2419 VirtMachineState *vms = VIRT_MACHINE(obj);
2420
2421 return vms->highmem_mmio;
2422}
2423
2424static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
2425{
2426 VirtMachineState *vms = VIRT_MACHINE(obj);
2427
2428 vms->highmem_mmio = value;
2429}
2430
2431
2432static bool virt_get_its(Object *obj, Error **errp)
2433{
2434 VirtMachineState *vms = VIRT_MACHINE(obj);
2435
2436 return vms->its;
2437}
2438
2439static void virt_set_its(Object *obj, bool value, Error **errp)
2440{
2441 VirtMachineState *vms = VIRT_MACHINE(obj);
2442
2443 vms->its = value;
2444}
2445
2446static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2447{
2448 VirtMachineState *vms = VIRT_MACHINE(obj);
2449
2450 return vms->dtb_randomness;
2451}
2452
2453static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2454{
2455 VirtMachineState *vms = VIRT_MACHINE(obj);
2456
2457 vms->dtb_randomness = value;
2458}
2459
2460static char *virt_get_oem_id(Object *obj, Error **errp)
2461{
2462 VirtMachineState *vms = VIRT_MACHINE(obj);
2463
2464 return g_strdup(vms->oem_id);
2465}
2466
2467static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2468{
2469 VirtMachineState *vms = VIRT_MACHINE(obj);
2470 size_t len = strlen(value);
2471
2472 if (len > 6) {
2473 error_setg(errp,
2474 "User specified oem-id value is bigger than 6 bytes in size");
2475 return;
2476 }
2477
2478 strncpy(vms->oem_id, value, 6);
2479}
2480
2481static char *virt_get_oem_table_id(Object *obj, Error **errp)
2482{
2483 VirtMachineState *vms = VIRT_MACHINE(obj);
2484
2485 return g_strdup(vms->oem_table_id);
2486}
2487
2488static void virt_set_oem_table_id(Object *obj, const char *value,
2489 Error **errp)
2490{
2491 VirtMachineState *vms = VIRT_MACHINE(obj);
2492 size_t len = strlen(value);
2493
2494 if (len > 8) {
2495 error_setg(errp,
2496 "User specified oem-table-id value is bigger than 8 bytes in size");
2497 return;
2498 }
2499 strncpy(vms->oem_table_id, value, 8);
2500}
2501
2502
2503bool virt_is_acpi_enabled(VirtMachineState *vms)
2504{
2505 if (vms->acpi == ON_OFF_AUTO_OFF) {
2506 return false;
2507 }
2508 return true;
2509}
2510
2511static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2512 void *opaque, Error **errp)
2513{
2514 VirtMachineState *vms = VIRT_MACHINE(obj);
2515 OnOffAuto acpi = vms->acpi;
2516
2517 visit_type_OnOffAuto(v, name, &acpi, errp);
2518}
2519
2520static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2521 void *opaque, Error **errp)
2522{
2523 VirtMachineState *vms = VIRT_MACHINE(obj);
2524
2525 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2526}
2527
2528static bool virt_get_ras(Object *obj, Error **errp)
2529{
2530 VirtMachineState *vms = VIRT_MACHINE(obj);
2531
2532 return vms->ras;
2533}
2534
2535static void virt_set_ras(Object *obj, bool value, Error **errp)
2536{
2537 VirtMachineState *vms = VIRT_MACHINE(obj);
2538
2539 vms->ras = value;
2540}
2541
2542static bool virt_get_mte(Object *obj, Error **errp)
2543{
2544 VirtMachineState *vms = VIRT_MACHINE(obj);
2545
2546 return vms->mte;
2547}
2548
2549static void virt_set_mte(Object *obj, bool value, Error **errp)
2550{
2551 VirtMachineState *vms = VIRT_MACHINE(obj);
2552
2553 vms->mte = value;
2554}
2555
2556static char *virt_get_gic_version(Object *obj, Error **errp)
2557{
2558 VirtMachineState *vms = VIRT_MACHINE(obj);
2559 const char *val;
2560
2561 switch (vms->gic_version) {
2562 case VIRT_GIC_VERSION_4:
2563 val = "4";
2564 break;
2565 case VIRT_GIC_VERSION_3:
2566 val = "3";
2567 break;
2568 default:
2569 val = "2";
2570 break;
2571 }
2572 return g_strdup(val);
2573}
2574
2575static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2576{
2577 VirtMachineState *vms = VIRT_MACHINE(obj);
2578
2579 if (!strcmp(value, "4")) {
2580 vms->gic_version = VIRT_GIC_VERSION_4;
2581 } else if (!strcmp(value, "3")) {
2582 vms->gic_version = VIRT_GIC_VERSION_3;
2583 } else if (!strcmp(value, "2")) {
2584 vms->gic_version = VIRT_GIC_VERSION_2;
2585 } else if (!strcmp(value, "host")) {
2586 vms->gic_version = VIRT_GIC_VERSION_HOST;
2587 } else if (!strcmp(value, "max")) {
2588 vms->gic_version = VIRT_GIC_VERSION_MAX;
2589 } else {
2590 error_setg(errp, "Invalid gic-version value");
2591 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2592 }
2593}
2594
2595static char *virt_get_iommu(Object *obj, Error **errp)
2596{
2597 VirtMachineState *vms = VIRT_MACHINE(obj);
2598
2599 switch (vms->iommu) {
2600 case VIRT_IOMMU_NONE:
2601 return g_strdup("none");
2602 case VIRT_IOMMU_SMMUV3:
2603 return g_strdup("smmuv3");
2604 default:
2605 g_assert_not_reached();
2606 }
2607}
2608
2609static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2610{
2611 VirtMachineState *vms = VIRT_MACHINE(obj);
2612
2613 if (!strcmp(value, "smmuv3")) {
2614 vms->iommu = VIRT_IOMMU_SMMUV3;
2615 } else if (!strcmp(value, "none")) {
2616 vms->iommu = VIRT_IOMMU_NONE;
2617 } else {
2618 error_setg(errp, "Invalid iommu value");
2619 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2620 }
2621}
2622
2623static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2624{
2625 VirtMachineState *vms = VIRT_MACHINE(obj);
2626
2627 return vms->default_bus_bypass_iommu;
2628}
2629
2630static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2631 Error **errp)
2632{
2633 VirtMachineState *vms = VIRT_MACHINE(obj);
2634
2635 vms->default_bus_bypass_iommu = value;
2636}
2637
2638static CpuInstanceProperties
2639virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2640{
2641 MachineClass *mc = MACHINE_GET_CLASS(ms);
2642 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2643
2644 assert(cpu_index < possible_cpus->len);
2645 return possible_cpus->cpus[cpu_index].props;
2646}
2647
2648static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2649{
2650 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2651
2652 return socket_id % ms->numa_state->num_nodes;
2653}
2654
2655static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2656{
2657 int n;
2658 unsigned int max_cpus = ms->smp.max_cpus;
2659 VirtMachineState *vms = VIRT_MACHINE(ms);
2660 MachineClass *mc = MACHINE_GET_CLASS(vms);
2661
2662 if (ms->possible_cpus) {
2663 assert(ms->possible_cpus->len == max_cpus);
2664 return ms->possible_cpus;
2665 }
2666
2667 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2668 sizeof(CPUArchId) * max_cpus);
2669 ms->possible_cpus->len = max_cpus;
2670 for (n = 0; n < ms->possible_cpus->len; n++) {
2671 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2672 ms->possible_cpus->cpus[n].arch_id =
2673 virt_cpu_mp_affinity(vms, n);
2674
2675 assert(!mc->smp_props.dies_supported);
2676 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2677 ms->possible_cpus->cpus[n].props.socket_id =
2678 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2679 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2680 ms->possible_cpus->cpus[n].props.cluster_id =
2681 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2682 ms->possible_cpus->cpus[n].props.has_core_id = true;
2683 ms->possible_cpus->cpus[n].props.core_id =
2684 (n / ms->smp.threads) % ms->smp.cores;
2685 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2686 ms->possible_cpus->cpus[n].props.thread_id =
2687 n % ms->smp.threads;
2688 }
2689 return ms->possible_cpus;
2690}
2691
2692static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2693 Error **errp)
2694{
2695 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2696 const MachineState *ms = MACHINE(hotplug_dev);
2697 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2698
2699 if (!vms->acpi_dev) {
2700 error_setg(errp,
2701 "memory hotplug is not enabled: missing acpi-ged device");
2702 return;
2703 }
2704
2705 if (vms->mte) {
2706 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2707 return;
2708 }
2709
2710 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2711 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2712 return;
2713 }
2714
2715 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2716}
2717
2718static void virt_memory_plug(HotplugHandler *hotplug_dev,
2719 DeviceState *dev, Error **errp)
2720{
2721 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2722 MachineState *ms = MACHINE(hotplug_dev);
2723 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2724
2725 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2726
2727 if (is_nvdimm) {
2728 nvdimm_plug(ms->nvdimms_state);
2729 }
2730
2731 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2732 dev, &error_abort);
2733}
2734
2735static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2736 DeviceState *dev, Error **errp)
2737{
2738 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2739
2740 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2741 virt_memory_pre_plug(hotplug_dev, dev, errp);
2742 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2743 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2744 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2745 hwaddr db_start = 0, db_end = 0;
2746 char *resv_prop_str;
2747
2748 if (vms->iommu != VIRT_IOMMU_NONE) {
2749 error_setg(errp, "virt machine does not support multiple IOMMUs");
2750 return;
2751 }
2752
2753 switch (vms->msi_controller) {
2754 case VIRT_MSI_CTRL_NONE:
2755 return;
2756 case VIRT_MSI_CTRL_ITS:
2757
2758 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2759 db_end = base_memmap[VIRT_GIC_ITS].base +
2760 base_memmap[VIRT_GIC_ITS].size - 1;
2761 break;
2762 case VIRT_MSI_CTRL_GICV2M:
2763
2764 db_start = base_memmap[VIRT_GIC_V2M].base;
2765 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2766 break;
2767 }
2768 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2769 db_start, db_end,
2770 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2771
2772 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
2773 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
2774 resv_prop_str, errp);
2775 g_free(resv_prop_str);
2776 }
2777}
2778
2779static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2780 DeviceState *dev, Error **errp)
2781{
2782 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2783
2784 if (vms->platform_bus_dev) {
2785 MachineClass *mc = MACHINE_GET_CLASS(vms);
2786
2787 if (device_is_dynamic_sysbus(mc, dev)) {
2788 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2789 SYS_BUS_DEVICE(dev));
2790 }
2791 }
2792
2793 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2794 virt_memory_plug(hotplug_dev, dev, errp);
2795 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2796 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2797 }
2798
2799 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2800 PCIDevice *pdev = PCI_DEVICE(dev);
2801
2802 vms->iommu = VIRT_IOMMU_VIRTIO;
2803 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2804 create_virtio_iommu_dt_bindings(vms);
2805 }
2806}
2807
2808static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2809 DeviceState *dev, Error **errp)
2810{
2811 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2812
2813 if (!vms->acpi_dev) {
2814 error_setg(errp,
2815 "memory hotplug is not enabled: missing acpi-ged device");
2816 return;
2817 }
2818
2819 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2820 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
2821 return;
2822 }
2823
2824 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2825 errp);
2826}
2827
2828static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2829 DeviceState *dev, Error **errp)
2830{
2831 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2832 Error *local_err = NULL;
2833
2834 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2835 if (local_err) {
2836 goto out;
2837 }
2838
2839 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2840 qdev_unrealize(dev);
2841
2842out:
2843 error_propagate(errp, local_err);
2844}
2845
2846static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2847 DeviceState *dev, Error **errp)
2848{
2849 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2850 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2851 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2852 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
2853 errp);
2854 } else {
2855 error_setg(errp, "device unplug request for unsupported device"
2856 " type: %s", object_get_typename(OBJECT(dev)));
2857 }
2858}
2859
2860static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2861 DeviceState *dev, Error **errp)
2862{
2863 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2864 virt_dimm_unplug(hotplug_dev, dev, errp);
2865 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2866 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2867 } else {
2868 error_setg(errp, "virt: device unplug for unsupported device"
2869 " type: %s", object_get_typename(OBJECT(dev)));
2870 }
2871}
2872
2873static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2874 DeviceState *dev)
2875{
2876 MachineClass *mc = MACHINE_GET_CLASS(machine);
2877
2878 if (device_is_dynamic_sysbus(mc, dev) ||
2879 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2880 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
2881 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2882 return HOTPLUG_HANDLER(machine);
2883 }
2884 return NULL;
2885}
2886
2887
2888
2889
2890
2891static int virt_kvm_type(MachineState *ms, const char *type_str)
2892{
2893 VirtMachineState *vms = VIRT_MACHINE(ms);
2894 int max_vm_pa_size, requested_pa_size;
2895 bool fixed_ipa;
2896
2897 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2898
2899
2900 virt_set_memmap(vms, max_vm_pa_size);
2901
2902 requested_pa_size = 64 - clz64(vms->highest_gpa);
2903
2904
2905
2906
2907 if (requested_pa_size < 32) {
2908 requested_pa_size = 32;
2909 }
2910
2911 if (requested_pa_size > max_vm_pa_size) {
2912 error_report("-m and ,maxmem option values "
2913 "require an IPA range (%d bits) larger than "
2914 "the one supported by the host (%d bits)",
2915 requested_pa_size, max_vm_pa_size);
2916 exit(1);
2917 }
2918
2919
2920
2921
2922
2923 return fixed_ipa ? 0 : requested_pa_size;
2924}
2925
2926static void virt_machine_class_init(ObjectClass *oc, void *data)
2927{
2928 MachineClass *mc = MACHINE_CLASS(oc);
2929 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2930
2931 mc->init = machvirt_init;
2932
2933
2934
2935
2936 mc->max_cpus = 512;
2937 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2938 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2939 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2940 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2941#ifdef CONFIG_TPM
2942 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2943#endif
2944 mc->block_default_type = IF_VIRTIO;
2945 mc->no_cdrom = 1;
2946 mc->pci_allow_0_address = true;
2947
2948 mc->minimum_page_bits = 12;
2949 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2950 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2951#ifdef CONFIG_TCG
2952 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2953#else
2954 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
2955#endif
2956 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2957 mc->kvm_type = virt_kvm_type;
2958 assert(!mc->get_hotplug_handler);
2959 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2960 hc->pre_plug = virt_machine_device_pre_plug_cb;
2961 hc->plug = virt_machine_device_plug_cb;
2962 hc->unplug_request = virt_machine_device_unplug_request_cb;
2963 hc->unplug = virt_machine_device_unplug_cb;
2964 mc->nvdimm_supported = true;
2965 mc->smp_props.clusters_supported = true;
2966 mc->auto_enable_numa_with_memhp = true;
2967 mc->auto_enable_numa_with_memdev = true;
2968
2969 mc->cpu_cluster_has_numa_boundary = true;
2970 mc->default_ram_id = "mach-virt.ram";
2971 mc->default_nic = "virtio-net-pci";
2972
2973 object_class_property_add(oc, "acpi", "OnOffAuto",
2974 virt_get_acpi, virt_set_acpi,
2975 NULL, NULL);
2976 object_class_property_set_description(oc, "acpi",
2977 "Enable ACPI");
2978 object_class_property_add_bool(oc, "secure", virt_get_secure,
2979 virt_set_secure);
2980 object_class_property_set_description(oc, "secure",
2981 "Set on/off to enable/disable the ARM "
2982 "Security Extensions (TrustZone)");
2983
2984 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2985 virt_set_virt);
2986 object_class_property_set_description(oc, "virtualization",
2987 "Set on/off to enable/disable emulating a "
2988 "guest CPU which implements the ARM "
2989 "Virtualization Extensions");
2990
2991 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2992 virt_set_highmem);
2993 object_class_property_set_description(oc, "highmem",
2994 "Set on/off to enable/disable using "
2995 "physical address space above 32 bits");
2996
2997 object_class_property_add_bool(oc, "compact-highmem",
2998 virt_get_compact_highmem,
2999 virt_set_compact_highmem);
3000 object_class_property_set_description(oc, "compact-highmem",
3001 "Set on/off to enable/disable compact "
3002 "layout for high memory regions");
3003
3004 object_class_property_add_bool(oc, "highmem-redists",
3005 virt_get_highmem_redists,
3006 virt_set_highmem_redists);
3007 object_class_property_set_description(oc, "highmem-redists",
3008 "Set on/off to enable/disable high "
3009 "memory region for GICv3 or GICv4 "
3010 "redistributor");
3011
3012 object_class_property_add_bool(oc, "highmem-ecam",
3013 virt_get_highmem_ecam,
3014 virt_set_highmem_ecam);
3015 object_class_property_set_description(oc, "highmem-ecam",
3016 "Set on/off to enable/disable high "
3017 "memory region for PCI ECAM");
3018
3019 object_class_property_add_bool(oc, "highmem-mmio",
3020 virt_get_highmem_mmio,
3021 virt_set_highmem_mmio);
3022 object_class_property_set_description(oc, "highmem-mmio",
3023 "Set on/off to enable/disable high "
3024 "memory region for PCI MMIO");
3025
3026 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3027 virt_set_gic_version);
3028 object_class_property_set_description(oc, "gic-version",
3029 "Set GIC version. "
3030 "Valid values are 2, 3, 4, host and max");
3031
3032 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
3033 object_class_property_set_description(oc, "iommu",
3034 "Set the IOMMU type. "
3035 "Valid values are none and smmuv3");
3036
3037 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3038 virt_get_default_bus_bypass_iommu,
3039 virt_set_default_bus_bypass_iommu);
3040 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3041 "Set on/off to enable/disable "
3042 "bypass_iommu for default root bus");
3043
3044 object_class_property_add_bool(oc, "ras", virt_get_ras,
3045 virt_set_ras);
3046 object_class_property_set_description(oc, "ras",
3047 "Set on/off to enable/disable reporting host memory errors "
3048 "to a KVM guest using ACPI and guest external abort exceptions");
3049
3050 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
3051 object_class_property_set_description(oc, "mte",
3052 "Set on/off to enable/disable emulating a "
3053 "guest CPU which implements the ARM "
3054 "Memory Tagging Extension");
3055
3056 object_class_property_add_bool(oc, "its", virt_get_its,
3057 virt_set_its);
3058 object_class_property_set_description(oc, "its",
3059 "Set on/off to enable/disable "
3060 "ITS instantiation");
3061
3062 object_class_property_add_bool(oc, "dtb-randomness",
3063 virt_get_dtb_randomness,
3064 virt_set_dtb_randomness);
3065 object_class_property_set_description(oc, "dtb-randomness",
3066 "Set off to disable passing random or "
3067 "non-deterministic dtb nodes to guest");
3068
3069 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3070 virt_get_dtb_randomness,
3071 virt_set_dtb_randomness);
3072 object_class_property_set_description(oc, "dtb-kaslr-seed",
3073 "Deprecated synonym of dtb-randomness");
3074
3075 object_class_property_add_str(oc, "x-oem-id",
3076 virt_get_oem_id,
3077 virt_set_oem_id);
3078 object_class_property_set_description(oc, "x-oem-id",
3079 "Override the default value of field OEMID "
3080 "in ACPI table header."
3081 "The string may be up to 6 bytes in size");
3082
3083
3084 object_class_property_add_str(oc, "x-oem-table-id",
3085 virt_get_oem_table_id,
3086 virt_set_oem_table_id);
3087 object_class_property_set_description(oc, "x-oem-table-id",
3088 "Override the default value of field OEM Table ID "
3089 "in ACPI table header."
3090 "The string may be up to 8 bytes in size");
3091
3092}
3093
3094static void virt_instance_init(Object *obj)
3095{
3096 VirtMachineState *vms = VIRT_MACHINE(obj);
3097 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3098
3099
3100
3101
3102
3103 vms->secure = false;
3104
3105
3106 vms->virt = false;
3107
3108
3109 vms->highmem = true;
3110 vms->highmem_compact = !vmc->no_highmem_compact;
3111 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3112
3113 vms->highmem_ecam = !vmc->no_highmem_ecam;
3114 vms->highmem_mmio = true;
3115 vms->highmem_redists = true;
3116
3117 if (vmc->no_its) {
3118 vms->its = false;
3119 } else {
3120
3121 vms->its = true;
3122
3123 if (vmc->no_tcg_its) {
3124 vms->tcg_its = false;
3125 } else {
3126 vms->tcg_its = true;
3127 }
3128 }
3129
3130
3131 vms->iommu = VIRT_IOMMU_NONE;
3132
3133
3134 vms->default_bus_bypass_iommu = false;
3135
3136
3137 vms->ras = false;
3138
3139
3140 vms->mte = false;
3141
3142
3143 vms->dtb_randomness = true;
3144
3145 vms->irqmap = a15irqmap;
3146
3147 virt_flash_create(vms);
3148
3149 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3150 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3151}
3152
3153static const TypeInfo virt_machine_info = {
3154 .name = TYPE_VIRT_MACHINE,
3155 .parent = TYPE_MACHINE,
3156 .abstract = true,
3157 .instance_size = sizeof(VirtMachineState),
3158 .class_size = sizeof(VirtMachineClass),
3159 .class_init = virt_machine_class_init,
3160 .instance_init = virt_instance_init,
3161 .interfaces = (InterfaceInfo[]) {
3162 { TYPE_HOTPLUG_HANDLER },
3163 { }
3164 },
3165};
3166
3167static void machvirt_machine_init(void)
3168{
3169 type_register_static(&virt_machine_info);
3170}
3171type_init(machvirt_machine_init);
3172
3173static void virt_machine_8_1_options(MachineClass *mc)
3174{
3175}
3176DEFINE_VIRT_MACHINE_AS_LATEST(8, 1)
3177
3178static void virt_machine_8_0_options(MachineClass *mc)
3179{
3180 virt_machine_8_1_options(mc);
3181 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3182}
3183DEFINE_VIRT_MACHINE(8, 0)
3184
3185static void virt_machine_7_2_options(MachineClass *mc)
3186{
3187 virt_machine_8_0_options(mc);
3188 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3189}
3190DEFINE_VIRT_MACHINE(7, 2)
3191
3192static void virt_machine_7_1_options(MachineClass *mc)
3193{
3194 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3195
3196 virt_machine_7_2_options(mc);
3197 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3198
3199 vmc->no_highmem_compact = true;
3200}
3201DEFINE_VIRT_MACHINE(7, 1)
3202
3203static void virt_machine_7_0_options(MachineClass *mc)
3204{
3205 virt_machine_7_1_options(mc);
3206 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3207}
3208DEFINE_VIRT_MACHINE(7, 0)
3209
3210static void virt_machine_6_2_options(MachineClass *mc)
3211{
3212 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3213
3214 virt_machine_7_0_options(mc);
3215 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3216 vmc->no_tcg_lpa2 = true;
3217}
3218DEFINE_VIRT_MACHINE(6, 2)
3219
3220static void virt_machine_6_1_options(MachineClass *mc)
3221{
3222 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3223
3224 virt_machine_6_2_options(mc);
3225 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3226 mc->smp_props.prefer_sockets = true;
3227 vmc->no_cpu_topology = true;
3228
3229
3230 vmc->no_tcg_its = true;
3231}
3232DEFINE_VIRT_MACHINE(6, 1)
3233
3234static void virt_machine_6_0_options(MachineClass *mc)
3235{
3236 virt_machine_6_1_options(mc);
3237 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3238}
3239DEFINE_VIRT_MACHINE(6, 0)
3240
3241static void virt_machine_5_2_options(MachineClass *mc)
3242{
3243 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3244
3245 virt_machine_6_0_options(mc);
3246 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3247 vmc->no_secure_gpio = true;
3248}
3249DEFINE_VIRT_MACHINE(5, 2)
3250
3251static void virt_machine_5_1_options(MachineClass *mc)
3252{
3253 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3254
3255 virt_machine_5_2_options(mc);
3256 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3257 vmc->no_kvm_steal_time = true;
3258}
3259DEFINE_VIRT_MACHINE(5, 1)
3260
3261static void virt_machine_5_0_options(MachineClass *mc)
3262{
3263 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3264
3265 virt_machine_5_1_options(mc);
3266 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3267 mc->numa_mem_supported = true;
3268 vmc->acpi_expose_flash = true;
3269 mc->auto_enable_numa_with_memdev = false;
3270}
3271DEFINE_VIRT_MACHINE(5, 0)
3272
3273static void virt_machine_4_2_options(MachineClass *mc)
3274{
3275 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3276
3277 virt_machine_5_0_options(mc);
3278 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3279 vmc->kvm_no_adjvtime = true;
3280}
3281DEFINE_VIRT_MACHINE(4, 2)
3282
3283static void virt_machine_4_1_options(MachineClass *mc)
3284{
3285 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3286
3287 virt_machine_4_2_options(mc);
3288 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3289 vmc->no_ged = true;
3290 mc->auto_enable_numa_with_memhp = false;
3291}
3292DEFINE_VIRT_MACHINE(4, 1)
3293
3294static void virt_machine_4_0_options(MachineClass *mc)
3295{
3296 virt_machine_4_1_options(mc);
3297 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
3298}
3299DEFINE_VIRT_MACHINE(4, 0)
3300
3301static void virt_machine_3_1_options(MachineClass *mc)
3302{
3303 virt_machine_4_0_options(mc);
3304 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
3305}
3306DEFINE_VIRT_MACHINE(3, 1)
3307
3308static void virt_machine_3_0_options(MachineClass *mc)
3309{
3310 virt_machine_3_1_options(mc);
3311 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
3312}
3313DEFINE_VIRT_MACHINE(3, 0)
3314
3315static void virt_machine_2_12_options(MachineClass *mc)
3316{
3317 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3318
3319 virt_machine_3_0_options(mc);
3320 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3321 vmc->no_highmem_ecam = true;
3322 mc->max_cpus = 255;
3323}
3324DEFINE_VIRT_MACHINE(2, 12)
3325
3326static void virt_machine_2_11_options(MachineClass *mc)
3327{
3328 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3329
3330 virt_machine_2_12_options(mc);
3331 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3332 vmc->smbios_old_sys_ver = true;
3333}
3334DEFINE_VIRT_MACHINE(2, 11)
3335
3336static void virt_machine_2_10_options(MachineClass *mc)
3337{
3338 virt_machine_2_11_options(mc);
3339 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3340
3341 mc->ignore_memory_transaction_failures = true;
3342}
3343DEFINE_VIRT_MACHINE(2, 10)
3344
3345static void virt_machine_2_9_options(MachineClass *mc)
3346{
3347 virt_machine_2_10_options(mc);
3348 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3349}
3350DEFINE_VIRT_MACHINE(2, 9)
3351
3352static void virt_machine_2_8_options(MachineClass *mc)
3353{
3354 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3355
3356 virt_machine_2_9_options(mc);
3357 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3358
3359
3360
3361 vmc->claim_edge_triggered_timers = true;
3362}
3363DEFINE_VIRT_MACHINE(2, 8)
3364
3365static void virt_machine_2_7_options(MachineClass *mc)
3366{
3367 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3368
3369 virt_machine_2_8_options(mc);
3370 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3371
3372 vmc->no_its = true;
3373
3374 mc->minimum_page_bits = 0;
3375}
3376DEFINE_VIRT_MACHINE(2, 7)
3377
3378static void virt_machine_2_6_options(MachineClass *mc)
3379{
3380 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3381
3382 virt_machine_2_7_options(mc);
3383 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3384 vmc->disallow_affinity_adjustment = true;
3385
3386 vmc->no_pmu = true;
3387}
3388DEFINE_VIRT_MACHINE(2, 6)
3389