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24#include "qemu/osdep.h"
25#include "hw/sysbus.h"
26#include "migration/vmstate.h"
27#include "chardev/char-fe.h"
28#include "chardev/char-serial.h"
29#include "qemu/timer.h"
30#include "qemu/log.h"
31#include "qemu/module.h"
32#include "hw/char/cadence_uart.h"
33#include "hw/irq.h"
34#include "hw/qdev-clock.h"
35#include "hw/qdev-properties-system.h"
36#include "trace.h"
37
38#ifdef CADENCE_UART_ERR_DEBUG
39#define DB_PRINT(...) do { \
40 fprintf(stderr, ": %s: ", __func__); \
41 fprintf(stderr, ## __VA_ARGS__); \
42 } while (0)
43#else
44 #define DB_PRINT(...)
45#endif
46
47#define UART_SR_INTR_RTRIG 0x00000001
48#define UART_SR_INTR_REMPTY 0x00000002
49#define UART_SR_INTR_RFUL 0x00000004
50#define UART_SR_INTR_TEMPTY 0x00000008
51#define UART_SR_INTR_TFUL 0x00000010
52
53#define UART_SR_TTRIG 0x00002000
54#define UART_INTR_TTRIG 0x00000400
55
56
57#define UART_SR_TO_CISR_MASK 0x0000001F
58
59#define UART_INTR_ROVR 0x00000020
60#define UART_INTR_FRAME 0x00000040
61#define UART_INTR_PARE 0x00000080
62#define UART_INTR_TIMEOUT 0x00000100
63#define UART_INTR_DMSI 0x00000200
64#define UART_INTR_TOVR 0x00001000
65
66#define UART_SR_RACTIVE 0x00000400
67#define UART_SR_TACTIVE 0x00000800
68#define UART_SR_FDELT 0x00001000
69
70#define UART_CR_RXRST 0x00000001
71#define UART_CR_TXRST 0x00000002
72#define UART_CR_RX_EN 0x00000004
73#define UART_CR_RX_DIS 0x00000008
74#define UART_CR_TX_EN 0x00000010
75#define UART_CR_TX_DIS 0x00000020
76#define UART_CR_RST_TO 0x00000040
77#define UART_CR_STARTBRK 0x00000080
78#define UART_CR_STOPBRK 0x00000100
79
80#define UART_MR_CLKS 0x00000001
81#define UART_MR_CHRL 0x00000006
82#define UART_MR_CHRL_SH 1
83#define UART_MR_PAR 0x00000038
84#define UART_MR_PAR_SH 3
85#define UART_MR_NBSTOP 0x000000C0
86#define UART_MR_NBSTOP_SH 6
87#define UART_MR_CHMODE 0x00000300
88#define UART_MR_CHMODE_SH 8
89#define UART_MR_UCLKEN 0x00000400
90#define UART_MR_IRMODE 0x00000800
91
92#define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
93#define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
94#define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
95#define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
96#define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
97#define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
98#define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
99#define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
100#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
101#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
102
103#define UART_DEFAULT_REF_CLK (50 * 1000 * 1000)
104
105#define R_CR (0x00/4)
106#define R_MR (0x04/4)
107#define R_IER (0x08/4)
108#define R_IDR (0x0C/4)
109#define R_IMR (0x10/4)
110#define R_CISR (0x14/4)
111#define R_BRGR (0x18/4)
112#define R_RTOR (0x1C/4)
113#define R_RTRIG (0x20/4)
114#define R_MCR (0x24/4)
115#define R_MSR (0x28/4)
116#define R_SR (0x2C/4)
117#define R_TX_RX (0x30/4)
118#define R_BDIV (0x34/4)
119#define R_FDEL (0x38/4)
120#define R_PMIN (0x3C/4)
121#define R_PWID (0x40/4)
122#define R_TTRIG (0x44/4)
123
124
125static void uart_update_status(CadenceUARTState *s)
126{
127 s->r[R_SR] = 0;
128
129 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
130 : 0;
131 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
132 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
133
134 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
135 : 0;
136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
137 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
138
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
142}
143
144static void fifo_trigger_update(void *opaque)
145{
146 CadenceUARTState *s = opaque;
147
148 if (s->r[R_RTOR]) {
149 s->r[R_CISR] |= UART_INTR_TIMEOUT;
150 uart_update_status(s);
151 }
152}
153
154static void uart_rx_reset(CadenceUARTState *s)
155{
156 s->rx_wpos = 0;
157 s->rx_count = 0;
158 qemu_chr_fe_accept_input(&s->chr);
159}
160
161static void uart_tx_reset(CadenceUARTState *s)
162{
163 s->tx_count = 0;
164}
165
166static void uart_send_breaks(CadenceUARTState *s)
167{
168 int break_enabled = 1;
169
170 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
171 &break_enabled);
172}
173
174static void uart_parameters_setup(CadenceUARTState *s)
175{
176 QEMUSerialSetParams ssp;
177 unsigned int baud_rate, packet_size, input_clk;
178 input_clk = clock_get_hz(s->refclk);
179
180 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk;
181 baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
182 trace_cadence_uart_baudrate(baud_rate);
183
184 ssp.speed = baud_rate;
185
186 packet_size = 1;
187
188 switch (s->r[R_MR] & UART_MR_PAR) {
189 case UART_PARITY_EVEN:
190 ssp.parity = 'E';
191 packet_size++;
192 break;
193 case UART_PARITY_ODD:
194 ssp.parity = 'O';
195 packet_size++;
196 break;
197 default:
198 ssp.parity = 'N';
199 break;
200 }
201
202 switch (s->r[R_MR] & UART_MR_CHRL) {
203 case UART_DATA_BITS_6:
204 ssp.data_bits = 6;
205 break;
206 case UART_DATA_BITS_7:
207 ssp.data_bits = 7;
208 break;
209 default:
210 ssp.data_bits = 8;
211 break;
212 }
213
214 switch (s->r[R_MR] & UART_MR_NBSTOP) {
215 case UART_STOP_BITS_1:
216 ssp.stop_bits = 1;
217 break;
218 default:
219 ssp.stop_bits = 2;
220 break;
221 }
222
223 packet_size += ssp.data_bits + ssp.stop_bits;
224 if (ssp.speed == 0) {
225
226
227
228
229 ssp.speed = 1;
230 }
231 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
232 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
233}
234
235static int uart_can_receive(void *opaque)
236{
237 CadenceUARTState *s = opaque;
238 int ret;
239 uint32_t ch_mode;
240
241
242 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
243 qemu_log_mask(LOG_GUEST_ERROR, "%s: uart is unclocked or in reset\n",
244 __func__);
245 return 0;
246 }
247
248 ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
249 ch_mode = s->r[R_MR] & UART_MR_CHMODE;
250
251 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
252 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
253 }
254 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
255 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
256 }
257 return ret;
258}
259
260static void uart_ctrl_update(CadenceUARTState *s)
261{
262 if (s->r[R_CR] & UART_CR_TXRST) {
263 uart_tx_reset(s);
264 }
265
266 if (s->r[R_CR] & UART_CR_RXRST) {
267 uart_rx_reset(s);
268 }
269
270 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
271
272 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
273 uart_send_breaks(s);
274 }
275}
276
277static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
278{
279 CadenceUARTState *s = opaque;
280 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
281 int i;
282
283 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
284 return;
285 }
286
287 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
288 s->r[R_CISR] |= UART_INTR_ROVR;
289 } else {
290 for (i = 0; i < size; i++) {
291 s->rx_fifo[s->rx_wpos] = buf[i];
292 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
293 s->rx_count++;
294 }
295 timer_mod(s->fifo_trigger_handle, new_rx_time +
296 (s->char_tx_time * 4));
297 }
298 uart_update_status(s);
299}
300
301static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
302 void *opaque)
303{
304 CadenceUARTState *s = opaque;
305 int ret;
306
307
308 if (!qemu_chr_fe_backend_connected(&s->chr)) {
309 s->tx_count = 0;
310 return FALSE;
311 }
312
313 if (!s->tx_count) {
314 return FALSE;
315 }
316
317 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
318
319 if (ret >= 0) {
320 s->tx_count -= ret;
321 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
322 }
323
324 if (s->tx_count) {
325 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
326 cadence_uart_xmit, s);
327 if (!r) {
328 s->tx_count = 0;
329 return FALSE;
330 }
331 }
332
333 uart_update_status(s);
334 return FALSE;
335}
336
337static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
338 int size)
339{
340 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
341 return;
342 }
343
344 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
345 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
346
347
348
349
350
351 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
352 s->r[R_CISR] |= UART_INTR_ROVR;
353 }
354
355 memcpy(s->tx_fifo + s->tx_count, buf, size);
356 s->tx_count += size;
357
358 cadence_uart_xmit(NULL, G_IO_OUT, s);
359}
360
361static void uart_receive(void *opaque, const uint8_t *buf, int size)
362{
363 CadenceUARTState *s = opaque;
364 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
365
366 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
367 uart_write_rx_fifo(opaque, buf, size);
368 }
369 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
370 uart_write_tx_fifo(s, buf, size);
371 }
372}
373
374static void uart_event(void *opaque, QEMUChrEvent event)
375{
376 CadenceUARTState *s = opaque;
377 uint8_t buf = '\0';
378
379
380 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
381 qemu_log_mask(LOG_GUEST_ERROR, "%s: uart is unclocked or in reset\n",
382 __func__);
383 return;
384 }
385
386 if (event == CHR_EVENT_BREAK) {
387 uart_write_rx_fifo(opaque, &buf, 1);
388 }
389
390 uart_update_status(s);
391}
392
393static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
394{
395 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
396 return;
397 }
398
399 if (s->rx_count) {
400 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
401 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
402 *c = s->rx_fifo[rx_rpos];
403 s->rx_count--;
404
405 qemu_chr_fe_accept_input(&s->chr);
406 } else {
407 *c = 0;
408 }
409
410 uart_update_status(s);
411}
412
413static MemTxResult uart_write(void *opaque, hwaddr offset,
414 uint64_t value, unsigned size, MemTxAttrs attrs)
415{
416 CadenceUARTState *s = opaque;
417
418
419 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
420 qemu_log_mask(LOG_GUEST_ERROR, "%s: uart is unclocked or in reset\n",
421 __func__);
422 return MEMTX_ERROR;
423 }
424
425 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
426 offset >>= 2;
427 if (offset >= CADENCE_UART_R_MAX) {
428 return MEMTX_DECODE_ERROR;
429 }
430 switch (offset) {
431 case R_IER:
432 s->r[R_IMR] |= value;
433 break;
434 case R_IDR:
435 s->r[R_IMR] &= ~value;
436 break;
437 case R_IMR:
438 break;
439 case R_CISR:
440 s->r[R_CISR] &= ~value;
441 break;
442 case R_TX_RX:
443 switch (s->r[R_MR] & UART_MR_CHMODE) {
444 case NORMAL_MODE:
445 uart_write_tx_fifo(s, (uint8_t *) &value, 1);
446 break;
447 case LOCAL_LOOPBACK:
448 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
449 break;
450 }
451 break;
452 case R_BRGR:
453 value &= 0xffff;
454 if (value >= 0x01) {
455 s->r[offset] = value;
456 }
457 break;
458 case R_BDIV:
459 value &= 0xff;
460 if (value >= 0x04) {
461 s->r[offset] = value;
462 }
463 break;
464 default:
465 s->r[offset] = value;
466 }
467
468 switch (offset) {
469 case R_CR:
470 uart_ctrl_update(s);
471 break;
472 case R_MR:
473 uart_parameters_setup(s);
474 break;
475 }
476 uart_update_status(s);
477
478 return MEMTX_OK;
479}
480
481static MemTxResult uart_read(void *opaque, hwaddr offset,
482 uint64_t *value, unsigned size, MemTxAttrs attrs)
483{
484 CadenceUARTState *s = opaque;
485 uint32_t c = 0;
486
487
488 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
489 qemu_log_mask(LOG_GUEST_ERROR, "%s: uart is unclocked or in reset\n",
490 __func__);
491 return MEMTX_ERROR;
492 }
493
494 offset >>= 2;
495 if (offset >= CADENCE_UART_R_MAX) {
496 return MEMTX_DECODE_ERROR;
497 }
498 if (offset == R_TX_RX) {
499 uart_read_rx_fifo(s, &c);
500 } else {
501 c = s->r[offset];
502 }
503
504 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
505 *value = c;
506 return MEMTX_OK;
507}
508
509static const MemoryRegionOps uart_ops = {
510 .read_with_attrs = uart_read,
511 .write_with_attrs = uart_write,
512 .endianness = DEVICE_NATIVE_ENDIAN,
513};
514
515static void cadence_uart_reset_init(Object *obj, ResetType type)
516{
517 CadenceUARTState *s = CADENCE_UART(obj);
518
519 s->r[R_CR] = 0x00000128;
520 s->r[R_IMR] = 0;
521 s->r[R_CISR] = 0;
522 s->r[R_RTRIG] = 0x00000020;
523 s->r[R_BRGR] = 0x0000028B;
524 s->r[R_BDIV] = 0x0000000F;
525 s->r[R_TTRIG] = 0x00000020;
526}
527
528static void cadence_uart_reset_hold(Object *obj)
529{
530 CadenceUARTState *s = CADENCE_UART(obj);
531
532 uart_rx_reset(s);
533 uart_tx_reset(s);
534
535 uart_update_status(s);
536}
537
538static void cadence_uart_realize(DeviceState *dev, Error **errp)
539{
540 CadenceUARTState *s = CADENCE_UART(dev);
541
542 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
543 fifo_trigger_update, s);
544
545 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
546 uart_event, NULL, s, NULL, true);
547}
548
549static void cadence_uart_refclk_update(void *opaque, ClockEvent event)
550{
551 CadenceUARTState *s = opaque;
552
553
554 uart_parameters_setup(s);
555}
556
557static void cadence_uart_init(Object *obj)
558{
559 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
560 CadenceUARTState *s = CADENCE_UART(obj);
561
562 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
563 sysbus_init_mmio(sbd, &s->iomem);
564 sysbus_init_irq(sbd, &s->irq);
565
566 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk",
567 cadence_uart_refclk_update, s, ClockUpdate);
568
569 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
570
571 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
572}
573
574static int cadence_uart_pre_load(void *opaque)
575{
576 CadenceUARTState *s = opaque;
577
578
579 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
580 return 0;
581}
582
583static int cadence_uart_post_load(void *opaque, int version_id)
584{
585 CadenceUARTState *s = opaque;
586
587
588 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF ||
589 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) {
590
591 return 1;
592 }
593
594 uart_parameters_setup(s);
595 uart_update_status(s);
596 return 0;
597}
598
599static const VMStateDescription vmstate_cadence_uart = {
600 .name = "cadence_uart",
601 .version_id = 3,
602 .minimum_version_id = 2,
603 .pre_load = cadence_uart_pre_load,
604 .post_load = cadence_uart_post_load,
605 .fields = (VMStateField[]) {
606 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
607 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
608 CADENCE_UART_RX_FIFO_SIZE),
609 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
610 CADENCE_UART_TX_FIFO_SIZE),
611 VMSTATE_UINT32(rx_count, CadenceUARTState),
612 VMSTATE_UINT32(tx_count, CadenceUARTState),
613 VMSTATE_UINT32(rx_wpos, CadenceUARTState),
614 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
615 VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3),
616 VMSTATE_END_OF_LIST()
617 },
618};
619
620static Property cadence_uart_properties[] = {
621 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
622 DEFINE_PROP_END_OF_LIST(),
623};
624
625static void cadence_uart_class_init(ObjectClass *klass, void *data)
626{
627 DeviceClass *dc = DEVICE_CLASS(klass);
628 ResettableClass *rc = RESETTABLE_CLASS(klass);
629
630 dc->realize = cadence_uart_realize;
631 dc->vmsd = &vmstate_cadence_uart;
632 rc->phases.enter = cadence_uart_reset_init;
633 rc->phases.hold = cadence_uart_reset_hold;
634 device_class_set_props(dc, cadence_uart_properties);
635 }
636
637static const TypeInfo cadence_uart_info = {
638 .name = TYPE_CADENCE_UART,
639 .parent = TYPE_SYS_BUS_DEVICE,
640 .instance_size = sizeof(CadenceUARTState),
641 .instance_init = cadence_uart_init,
642 .class_init = cadence_uart_class_init,
643};
644
645static void cadence_uart_register_types(void)
646{
647 type_register_static(&cadence_uart_info);
648}
649
650type_init(cadence_uart_register_types)
651
