1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 Linux NICS <linux.nics@intel.com> 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28/* e1000_hw.h 29 * Structures, enums, and macros for the MAC 30 */ 31 32#ifndef HW_E1000X_REGS_H 33#define HW_E1000X_REGS_H 34 35/* PCI Device IDs */ 36#define E1000_DEV_ID_82542 0x1000 37#define E1000_DEV_ID_82543GC_FIBER 0x1001 38#define E1000_DEV_ID_82543GC_COPPER 0x1004 39#define E1000_DEV_ID_82544EI_COPPER 0x1008 40#define E1000_DEV_ID_82544EI_FIBER 0x1009 41#define E1000_DEV_ID_82544GC_COPPER 0x100C 42#define E1000_DEV_ID_82544GC_LOM 0x100D 43#define E1000_DEV_ID_82540EM 0x100E 44#define E1000_DEV_ID_82540EM_LOM 0x1015 45#define E1000_DEV_ID_82540EP_LOM 0x1016 46#define E1000_DEV_ID_82540EP 0x1017 47#define E1000_DEV_ID_82540EP_LP 0x101E 48#define E1000_DEV_ID_82545EM_COPPER 0x100F 49#define E1000_DEV_ID_82545EM_FIBER 0x1011 50#define E1000_DEV_ID_82545GM_COPPER 0x1026 51#define E1000_DEV_ID_82545GM_FIBER 0x1027 52#define E1000_DEV_ID_82545GM_SERDES 0x1028 53#define E1000_DEV_ID_82546EB_COPPER 0x1010 54#define E1000_DEV_ID_82546EB_FIBER 0x1012 55#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 56#define E1000_DEV_ID_82541EI 0x1013 57#define E1000_DEV_ID_82541EI_MOBILE 0x1018 58#define E1000_DEV_ID_82541ER_LOM 0x1014 59#define E1000_DEV_ID_82541ER 0x1078 60#define E1000_DEV_ID_82547GI 0x1075 61#define E1000_DEV_ID_82541GI 0x1076 62#define E1000_DEV_ID_82541GI_MOBILE 0x1077 63#define E1000_DEV_ID_82541GI_LF 0x107C 64#define E1000_DEV_ID_82546GB_COPPER 0x1079 65#define E1000_DEV_ID_82546GB_FIBER 0x107A 66#define E1000_DEV_ID_82546GB_SERDES 0x107B 67#define E1000_DEV_ID_82546GB_PCIE 0x108A 68#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69#define E1000_DEV_ID_82547EI 0x1019 70#define E1000_DEV_ID_82547EI_MOBILE 0x101A 71#define E1000_DEV_ID_82571EB_COPPER 0x105E 72#define E1000_DEV_ID_82571EB_FIBER 0x105F 73#define E1000_DEV_ID_82571EB_SERDES 0x1060 74#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 75#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 76#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 77#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC 78#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 79#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 80#define E1000_DEV_ID_82572EI_COPPER 0x107D 81#define E1000_DEV_ID_82572EI_FIBER 0x107E 82#define E1000_DEV_ID_82572EI_SERDES 0x107F 83#define E1000_DEV_ID_82572EI 0x10B9 84#define E1000_DEV_ID_82573E 0x108B 85#define E1000_DEV_ID_82573E_IAMT 0x108C 86#define E1000_DEV_ID_82573L 0x109A 87#define E1000_DEV_ID_82574L 0x10D3 88#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 89#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 90#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 91#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 92#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 93 94#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 95#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 96#define E1000_DEV_ID_ICH8_IGP_C 0x104B 97#define E1000_DEV_ID_ICH8_IFE 0x104C 98#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 99#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 100#define E1000_DEV_ID_ICH8_IGP_M 0x104D 101 102/* Device Specific Register Defaults */ 103#define E1000_PHY_ID2_82541x 0x380 104#define E1000_PHY_ID2_82544x 0xC30 105#define E1000_PHY_ID2_8254xx_DEFAULT 0xC20 /* 82540x, 82545x, and 82546x */ 106#define E1000_PHY_ID2_82573x 0xCC0 107#define E1000_PHY_ID2_82574x 0xCB1 108 109/* Register Set. (82543, 82544) 110 * 111 * Registers are defined to be 32 bits and should be accessed as 32 bit values. 112 * These registers are physically located on the NIC, but are mapped into the 113 * host memory address space. 114 * 115 * RW - register is both readable and writable 116 * RO - register is read only 117 * WO - register is write only 118 * R/clr - register is read only and is cleared when read 119 * A - register array 120 */ 121#define E1000_CTRL 0x00000 /* Device Control - RW */ 122#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 123#define E1000_STATUS 0x00008 /* Device Status - RO */ 124#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 125#define E1000_EERD 0x00014 /* EEPROM Read - RW */ 126#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 127#define E1000_FLA 0x0001C /* Flash Access - RW */ 128#define E1000_MDIC 0x00020 /* MDI Control - RW */ 129#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 130#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 131#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 132#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 133#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 134#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 135#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 136#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 137#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 138#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 139#define E1000_RCTL 0x00100 /* RX Control - RW */ 140#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 141#define E1000_TCTL 0x00400 /* TX Control - RW */ 142#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 143#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 144#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 145#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 146#define E1000_EEMNGDATA 0x01014 /* MNG EEPROM Read/Write data */ 147#define E1000_FLMNGCTL 0x01018 /* MNG Flash Control */ 148#define E1000_FLMNGDATA 0x0101C /* MNG FLASH Read data */ 149#define E1000_FLMNGCNT 0x01020 /* MNG FLASH Read Counter */ 150#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 151#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 152#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 153#define E1000_FCRTL_A 0x00168 /* Alias to FCRTL */ 154#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 155#define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */ 156#define E1000_RDFH_A 0x08000 /* Alias to RDFH */ 157#define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */ 158#define E1000_RDFT_A 0x08008 /* Alias to RDFT */ 159#define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */ 160#define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */ 161#define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */ 162#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 163#define E1000_TDFH_A 0x08010 /* Alias to TDFH */ 164#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 165#define E1000_TDFT_A 0x08018 /* Alias to TDFT */ 166#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 167#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 168#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 169#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 170#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 171#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 172#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 173#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 174#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 175#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 176#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 177#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 178#define E1000_COLC 0x04028 /* Collision Count - R/clr */ 179#define E1000_DC 0x04030 /* Defer Count - R/clr */ 180#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 181#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 182#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 183#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 184#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 185#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 186#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 187#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 188#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 189#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 190#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 191#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 192#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 193#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 194#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 195#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 196#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 197#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 198#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 199#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 200#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 201#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 202#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 203#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 204#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 205#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 206#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 207#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 208#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 209#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 210#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 211#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 212#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 213#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 214#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 215#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 216#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 217#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 218#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 219#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 220#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 221#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 222#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 223#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 224#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 225#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ 226#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 227#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 228#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 229#define E1000_MAVTV0 0x05010 /* Management VLAN TAG Value 0 */ 230#define E1000_MAVTV1 0x05014 /* Management VLAN TAG Value 1 */ 231#define E1000_MAVTV2 0x05018 /* Management VLAN TAG Value 2 */ 232#define E1000_MAVTV3 0x0501c /* Management VLAN TAG Value 3 */ 233#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 234#define E1000_RA 0x05400 /* Receive Address - RW Array */ 235#define E1000_RA_A 0x00040 /* Alias to RA */ 236#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 237#define E1000_VFTA_A 0x00600 /* Alias to VFTA */ 238#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 239#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 240#define E1000_WUS 0x05810 /* Wakeup Status - RO */ 241#define E1000_MANC 0x05820 /* Management Control - RW */ 242#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 243#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 244#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 245#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 246#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 247#define E1000_MFVAL 0x05824 /* Manageability Filters Valid - RW */ 248#define E1000_MDEF 0x05890 /* Manageability Decision Filters - RW Array */ 249#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 250#define E1000_FTFT 0x09400 /* Flexible TCO Filter Table - RW Array */ 251 252#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 253#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 254 255#define E1000_GCR 0x05B00 /* PCI-Ex Control */ 256#define E1000_FUNCTAG 0x05B08 /* Function-Tag Register */ 257#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 258#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 259#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 260#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 261#define E1000_GSCN_0 0x05B20 /* 3GIO Statistic Counter Register #0 */ 262#define E1000_GSCN_1 0x05B24 /* 3GIO Statistic Counter Register #1 */ 263#define E1000_GSCN_2 0x05B28 /* 3GIO Statistic Counter Register #2 */ 264#define E1000_GSCN_3 0x05B2C /* 3GIO Statistic Counter Register #3 */ 265#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 266#define E1000_SWSM 0x05B50 /* SW Semaphore */ 267#define E1000_FWSM 0x05B54 /* FW Semaphore */ 268#define E1000_PBACLR 0x05B68 /* MSI-X PBA Clear */ 269 270#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 271#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 272#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ 273#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 274#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 275#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 276#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 277#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ 278#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ 279#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ 280#define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ 281#define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ 282#define E1000_TIMADJL 0x0B60C /* Time Adjustment Offset register Low - RW */ 283#define E1000_TIMADJH 0x0B610 /* Time Adjustment Offset register High - RW */ 284 285/* RSS registers */ 286#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 287#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ 288#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ 289 290#define E1000_RETA_IDX(hash) ((hash) & (BIT(7) - 1)) 291#define E1000_RETA_VAL(reta, hash) (((uint8_t *)(reta))[E1000_RETA_IDX(hash)]) 292 293#define E1000_MRQC_EN_TCPIPV4(mrqc) ((mrqc) & BIT(16)) 294#define E1000_MRQC_EN_IPV4(mrqc) ((mrqc) & BIT(17)) 295#define E1000_MRQC_EN_TCPIPV6EX(mrqc) ((mrqc) & BIT(18)) 296#define E1000_MRQC_EN_IPV6EX(mrqc) ((mrqc) & BIT(19)) 297#define E1000_MRQC_EN_IPV6(mrqc) ((mrqc) & BIT(20)) 298 299#define E1000_MRQ_RSS_TYPE_NONE (0) 300#define E1000_MRQ_RSS_TYPE_IPV4TCP (1) 301#define E1000_MRQ_RSS_TYPE_IPV4 (2) 302#define E1000_MRQ_RSS_TYPE_IPV6TCPEX (3) 303#define E1000_MRQ_RSS_TYPE_IPV6EX (4) 304#define E1000_MRQ_RSS_TYPE_IPV6 (5) 305 306#define E1000_ICR_ASSERTED BIT(31) 307#define E1000_EIAC_MASK 0x01F00000 308 309/* RFCTL register bits */ 310#define E1000_RFCTL_ISCSI_DIS 0x00000001 311#define E1000_RFCTL_NFSW_DIS 0x00000040 312#define E1000_RFCTL_NFSR_DIS 0x00000080 313#define E1000_RFCTL_IPV6_DIS 0x00000400 314#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 315#define E1000_RFCTL_IPFRSP_DIS 0x00004000 316#define E1000_RFCTL_EXTEN 0x00008000 317#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 318#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 319 320/* TARC* parsing */ 321#define E1000_TARC_ENABLE BIT(10) 322 323/* SW Semaphore Register */ 324#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 325#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 326#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 327 328#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 329 330/* Interrupt Cause Read */ 331#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 332#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 333#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 334#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 335#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 336#define E1000_ICR_RXO 0x00000040 /* rx overrun */ 337#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 338#define E1000_ICR_RXDW 0x00000080 /* rx desc written back */ 339#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 340#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 341#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 342#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 343#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 344#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 345#define E1000_ICR_TXD_LOW 0x00008000 346#define E1000_ICR_SRPD 0x00010000 347#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 348#define E1000_ICR_MNG 0x00040000 /* Manageability event */ 349#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 350#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 351#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 352#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 353#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 354#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 355#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 356#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 357#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 358#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 359#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 360#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ 361#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 362#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 363#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 364#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 365#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 366 367#define E1000_ICR_OTHER_CAUSES (E1000_ICR_LSC | \ 368 E1000_ICR_RXO | \ 369 E1000_ICR_MDAC | \ 370 E1000_ICR_SRPD | \ 371 E1000_ICR_ACK | \ 372 E1000_ICR_MNG) 373 374/* Interrupt Cause Set */ 375#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 376#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 377#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 378#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 379#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 380#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 381#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 382#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */ 383#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 384#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 385#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 386#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 387#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 388#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 389#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 390#define E1000_ICS_SRPD E1000_ICR_SRPD 391#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 392#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 393#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 394#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 395#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 396#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 397#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 398#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 399#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 400#define E1000_ICS_DSW E1000_ICR_DSW 401#define E1000_ICS_PHYINT E1000_ICR_PHYINT 402#define E1000_ICS_EPRST E1000_ICR_EPRST 403 404/* Interrupt Mask Set */ 405#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 406#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 407#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 408#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 409#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 410#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 411#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 412#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */ 413#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 414#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 415#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 416#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 417#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 418#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 419#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 420#define E1000_IMS_SRPD E1000_ICR_SRPD 421#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 422#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 423#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 424#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 425#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 426#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 427#define E1000_IMS_OTHER E1000_ICR_OTHER 428#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 429#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 430#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 431#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 432#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 433#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 434#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 435#define E1000_IMS_DSW E1000_ICR_DSW 436#define E1000_IMS_PHYINT E1000_ICR_PHYINT 437#define E1000_IMS_EPRST E1000_ICR_EPRST 438 439/* Interrupt Mask Clear */ 440#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 441#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 442#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 443#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 444#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 445#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 446#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 447#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */ 448#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 449#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 450#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 451#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 452#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 453#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 454#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 455#define E1000_IMC_SRPD E1000_ICR_SRPD 456#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ 457#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ 458#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ 459#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 460#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 461#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 462#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 463#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 464#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 465#define E1000_IMC_DSW E1000_ICR_DSW 466#define E1000_IMC_PHYINT E1000_ICR_PHYINT 467#define E1000_IMC_EPRST E1000_ICR_EPRST 468 469/* Receive Control */ 470#define E1000_RCTL_RST 0x00000001 /* Software reset */ 471#define E1000_RCTL_EN 0x00000002 /* enable */ 472#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 473#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 474#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 475#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 476#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 477#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 478#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 479#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 480#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 481#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 482#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 483#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 484#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 485#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 486#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 487#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 488#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 489#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 490#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 491#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 492/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 493#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 494#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 495#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 496#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 497/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 498#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 499#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 500#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 501#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 502#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 503#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 504#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 505#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 506#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 507#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 508#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 509#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 510 511 512#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 513#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 514#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ 515#define E1000_EEPROM_RW_REG_DONE 0x10 /* Offset to READ/WRITE done bit */ 516#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ 517#define E1000_EEPROM_RW_ADDR_SHIFT 8 /* Shift to the address bits */ 518#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ 519#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ 520 521/* 82574 EERD/EEWR registers layout */ 522#define E1000_EERW_START BIT(0) 523#define E1000_EERW_DONE BIT(1) 524#define E1000_EERW_ADDR_SHIFT 2 525#define E1000_EERW_ADDR_MASK ((1L << 14) - 1) 526#define E1000_EERW_DATA_SHIFT 16 527#define E1000_EERW_DATA_MASK ((1L << 16) - 1) 528 529/* Register Bit Masks */ 530/* Device Control */ 531#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 532#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 533#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 534#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 535#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 536#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 537#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 538#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 539#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 540#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 541#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 542#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 543#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 544#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 545#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 546#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 547#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 548#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 549#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 550#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 551#define E1000_CTRL_SPD_SHIFT 8 /* Speed Select Shift */ 552 553#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* auto speed detection check */ 554#define E1000_CTRL_EXT_EE_RST 0x00002000 /* EEPROM reset */ 555#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ 556#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 557#define E1000_CTRL_EXT_EIAME 0x01000000 558#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 559#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 560#define E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA 0x20000000 561#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 562 563#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 564#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 565#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 566#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 567#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 568#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 569#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 570#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 571#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 572#define E1000_CTRL_RST 0x04000000 /* Global reset */ 573#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 574#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 575#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 576#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 577#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 578#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 579 580/* Device Status */ 581#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 582#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 583#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 584#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 585#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 586#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 587#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 588 589/* EEPROM/Flash Control */ 590#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 591#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 592#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 593#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 594#define E1000_EECD_FWE_MASK 0x00000030 595#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 596#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 597#define E1000_EECD_FWE_SHIFT 4 598#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 599#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 600#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 601#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 602#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 603 * (0-small, 1-large) */ 604#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 605#ifndef E1000_EEPROM_GRANT_ATTEMPTS 606#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 607#endif 608#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 609#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 610#define E1000_EECD_SIZE_EX_SHIFT 11 611#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 612#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 613#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 614#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 615#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 616#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 617#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 618 619 620#define E1000_EECD_SECVAL_SHIFT 22 621#define E1000_STM_OPCODE 0xDB00 622#define E1000_HICR_FW_RESET 0xC0 623 624#define E1000_SHADOW_RAM_WORDS 2048 625#define E1000_ICH_NVM_SIG_WORD 0x13 626#define E1000_ICH_NVM_SIG_MASK 0xC0 627 628/* MDI Control */ 629#define E1000_MDIC_DATA_MASK 0x0000FFFF 630#define E1000_MDIC_REG_MASK 0x001F0000 631#define E1000_MDIC_REG_SHIFT 16 632#define E1000_MDIC_PHY_MASK 0x03E00000 633#define E1000_MDIC_PHY_SHIFT 21 634#define E1000_MDIC_OP_WRITE 0x04000000 635#define E1000_MDIC_OP_READ 0x08000000 636#define E1000_MDIC_READY 0x10000000 637#define E1000_MDIC_INT_EN 0x20000000 638#define E1000_MDIC_ERROR 0x40000000 639 640/* Rx Interrupt Delay Timer */ 641#define E1000_RDTR_FPD BIT(31) 642 643/* Tx Interrupt Delay Timer */ 644#define E1000_TIDV_FPD BIT(31) 645 646/* Delay increments in nanoseconds for delayed interrupts registers */ 647#define E1000_INTR_DELAY_NS_RES (1024) 648 649/* Delay increments in nanoseconds for interrupt throttling registers */ 650#define E1000_INTR_THROTTLING_NS_RES (256) 651 652/* EEPROM Commands - Microwire */ 653#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 654#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 655#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 656#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 657#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 658 659/* EEPROM Word Offsets */ 660#define EEPROM_COMPAT 0x0003 661#define EEPROM_ID_LED_SETTINGS 0x0004 662#define EEPROM_VERSION 0x0005 663#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 664#define EEPROM_PHY_CLASS_WORD 0x0007 665#define EEPROM_INIT_CONTROL1_REG 0x000A 666#define EEPROM_INIT_CONTROL2_REG 0x000F 667#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 668#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 669#define EEPROM_INIT_3GIO_3 0x001A 670#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 671#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 672#define EEPROM_CFG 0x0012 673#define EEPROM_FLASH_VERSION 0x0032 674#define EEPROM_CHECKSUM_REG 0x003F 675 676#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ 677#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ 678 679/* HH Time Sync */ 680#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 681#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 682#define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 683 684#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 685#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 686 687#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 688#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 689#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 690#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 691#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 692#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 693#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 694#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 695#define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 696 697#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 698#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 699 700#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 701#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 702 703#define E1000_TIMINCA_INCPERIOD_SHIFT 24 704#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 705 706/* PCI Express Control */ 707/* 3GIO Control Register - GCR (0x05B00; RW) */ 708#define E1000_L0S_ADJUST (1 << 9) 709#define E1000_L1_ENTRY_LATENCY_MSB (1 << 23) 710#define E1000_L1_ENTRY_LATENCY_LSB (1 << 25 | 1 << 26) 711 712#define E1000_L0S_ADJUST (1 << 9) 713#define E1000_L1_ENTRY_LATENCY_MSB (1 << 23) 714#define E1000_L1_ENTRY_LATENCY_LSB (1 << 25 | 1 << 26) 715 716#define E1000_GCR_RO_BITS (1 << 23 | 1 << 25 | 1 << 26) 717 718/* MSI-X PBA Clear register */ 719#define E1000_PBACLR_VALID_MASK (BIT(5) - 1) 720 721/* Transmit Descriptor bit definitions */ 722#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 723#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 724#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 725#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 726#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 727#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 728#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 729#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 730#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 731#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 732#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 733#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 734#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 735#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 736#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 737#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 738#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 739#define E1000_TXD_CMD_SNAP 0x40000000 /* Update SNAP header */ 740#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 741#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 742 743/* Transmit Control */ 744#define E1000_TCTL_RST 0x00000001 /* software reset */ 745#define E1000_TCTL_EN 0x00000002 /* enable tx */ 746#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 747#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 748#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 749#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 750#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 751#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 752#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 753#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 754#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 755 756/* Legacy Receive Descriptor */ 757struct e1000_rx_desc { 758 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 759 uint16_t length; /* Length of data DMAed into data buffer */ 760 uint16_t csum; /* Packet checksum */ 761 uint8_t status; /* Descriptor status */ 762 uint8_t errors; /* Descriptor Errors */ 763 uint16_t special; 764}; 765 766/* Extended Receive Descriptor */ 767union e1000_rx_desc_extended { 768 struct { 769 uint64_t buffer_addr; 770 uint64_t reserved; 771 } read; 772 struct { 773 struct { 774 uint32_t mrq; /* Multiple Rx Queues */ 775 union { 776 uint32_t rss; /* RSS Hash */ 777 struct { 778 uint16_t ip_id; /* IP id */ 779 uint16_t csum; /* Packet Checksum */ 780 } csum_ip; 781 } hi_dword; 782 } lower; 783 struct { 784 uint32_t status_error; /* ext status/error */ 785 uint16_t length; 786 uint16_t vlan; /* VLAN tag */ 787 } upper; 788 } wb; /* writeback */ 789}; 790 791#define MAX_PS_BUFFERS 4 792 793/* Number of packet split data buffers (not including the header buffer) */ 794#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 795 796/* Receive Descriptor - Packet Split */ 797union e1000_rx_desc_packet_split { 798 struct { 799 /* one buffer for protocol header(s), three data buffers */ 800 uint64_t buffer_addr[MAX_PS_BUFFERS]; 801 } read; 802 struct { 803 struct { 804 uint32_t mrq; /* Multiple Rx Queues */ 805 union { 806 uint32_t rss; /* RSS Hash */ 807 struct { 808 uint16_t ip_id; /* IP id */ 809 uint16_t csum; /* Packet Checksum */ 810 } csum_ip; 811 } hi_dword; 812 } lower; 813 struct { 814 uint32_t status_error; /* ext status/error */ 815 uint16_t length0; /* length of buffer 0 */ 816 uint16_t vlan; /* VLAN tag */ 817 } middle; 818 struct { 819 uint16_t header_status; 820 /* length of buffers 1-3 */ 821 uint16_t length[PS_PAGE_BUFFERS]; 822 } upper; 823 uint64_t reserved; 824 } wb; /* writeback */ 825}; 826 827/* Receive Checksum Control bits */ 828#define E1000_RXCSUM_IPOFLD 0x100 /* IP Checksum Offload Enable */ 829#define E1000_RXCSUM_TUOFLD 0x200 /* TCP/UDP Checksum Offload Enable */ 830#define E1000_RXCSUM_PCSD 0x2000 /* Packet Checksum Disable */ 831 832#define E1000_RING_DESC_LEN (16) 833#define E1000_RING_DESC_LEN_SHIFT (4) 834 835#define E1000_MIN_RX_DESC_LEN E1000_RING_DESC_LEN 836 837/* Receive Descriptor bit definitions */ 838#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 839#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 840#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 841#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 842#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 843#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 844#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 845#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 846#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 847#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 848#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 849#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 850#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 851#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 852#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 853#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 854#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 855#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 856#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 857#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 858#define E1000_RXD_SPC_PRI_SHIFT 13 859#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 860#define E1000_RXD_SPC_CFI_SHIFT 12 861 862/* RX packet types */ 863#define E1000_RXD_PKT_MAC (0) 864#define E1000_RXD_PKT_IP4 (1) 865#define E1000_RXD_PKT_IP4_XDP (2) 866#define E1000_RXD_PKT_IP6 (5) 867#define E1000_RXD_PKT_IP6_XDP (6) 868 869#define E1000_RXD_PKT_TYPE(t) ((t) << 16) 870 871#define E1000_RXDEXT_STATERR_CE 0x01000000 872#define E1000_RXDEXT_STATERR_SE 0x02000000 873#define E1000_RXDEXT_STATERR_SEQ 0x04000000 874#define E1000_RXDEXT_STATERR_CXE 0x10000000 875#define E1000_RXDEXT_STATERR_TCPE 0x20000000 876#define E1000_RXDEXT_STATERR_IPE 0x40000000 877#define E1000_RXDEXT_STATERR_RXE 0x80000000 878 879#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 880#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 881 882/* Receive Address */ 883#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 884 885/* Offload Context Descriptor */ 886struct e1000_context_desc { 887 union { 888 uint32_t ip_config; 889 struct { 890 uint8_t ipcss; /* IP checksum start */ 891 uint8_t ipcso; /* IP checksum offset */ 892 uint16_t ipcse; /* IP checksum end */ 893 } ip_fields; 894 } lower_setup; 895 union { 896 uint32_t tcp_config; 897 struct { 898 uint8_t tucss; /* TCP checksum start */ 899 uint8_t tucso; /* TCP checksum offset */ 900 uint16_t tucse; /* TCP checksum end */ 901 } tcp_fields; 902 } upper_setup; 903 uint32_t cmd_and_length; /* */ 904 union { 905 uint32_t data; 906 struct { 907 uint8_t status; /* Descriptor status */ 908 uint8_t hdr_len; /* Header length */ 909 uint16_t mss; /* Maximum segment size */ 910 } fields; 911 } tcp_seg_setup; 912}; 913 914/* Filters */ 915#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 916#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 917#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 918 919/* Management Control */ 920#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 921#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 922#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 923#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 924#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 925#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 926#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 927#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 928#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 929#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 930 * Filtering */ 931#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 932#define E1000_MANC_DIS_IP_CHK_ARP 0x10000000 /* Disable IP address chacking */ 933 /*for ARP packets - in 82574 */ 934#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 935#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 936#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 937#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 938#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 939#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 940 * filtering */ 941#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 942 * memory */ 943#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 944 * filtering */ 945#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 946#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 947#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 948#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 949#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 950#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 951#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 952#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 953 954#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 955#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 956 957/* FACTPS Control */ 958#define E1000_FACTPS_LAN0_ON 0x00000004 /* Lan 0 enable */ 959 960/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 961#define EEPROM_SUM 0xBABA 962 963/* I/O-Mapped Access to Internal Registers, Memories, and Flash */ 964#define E1000_IOADDR 0x00 965#define E1000_IODATA 0x04 966 967#define E1000_VFTA_ENTRY_SHIFT 5 968#define E1000_VFTA_ENTRY_MASK 0x7F 969#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 970 971#endif /* HW_E1000_REGS_H */ 972