LXR qemu/include/hw/ppc/pnv

   1/*
   2 * QEMU PowerPC PowerNV XSCOM bus definitions
   3 *
   4 * Copyright (c) 2016, IBM Corporation.
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef PPC_PNV_XSCOM_H
  21#define PPC_PNV_XSCOM_H
  22
  23#include "exec/memory.h"
  24#include "hw/ppc/pnv.h"
  25
  26typedef struct PnvXScomInterface PnvXScomInterface;
  27
  28#define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface"
  29#define PNV_XSCOM_INTERFACE(obj) \
  30    INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE)
  31typedef struct PnvXScomInterfaceClass PnvXScomInterfaceClass;
  32DECLARE_CLASS_CHECKERS(PnvXScomInterfaceClass, PNV_XSCOM_INTERFACE,
  33                       TYPE_PNV_XSCOM_INTERFACE)
  34
  35struct PnvXScomInterfaceClass {
  36    InterfaceClass parent;
  37    int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset);
  38};
  39
  40/*
  41 * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
  42 *
  43 *   GPIO        0x1100xxxx
  44 *   SCOM        0x1101xxxx
  45 *   OHA         0x1102xxxx
  46 *   CLOCK CTL   0x1103xxxx
  47 *   FIR         0x1104xxxx
  48 *   THERM       0x1105xxxx
  49 *   <reserved>  0x1106xxxx
  50 *               ..
  51 *               0x110Exxxx
  52 *   PCB SLAVE   0x110Fxxxx
  53 */
  54
  55#define PNV_XSCOM_EX_CORE_BASE    0x10000000ull
  56
  57#define PNV_XSCOM_EX_BASE(core) \
  58    (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
  59#define PNV_XSCOM_EX_SIZE         0x100000
  60
  61#define PNV_XSCOM_LPC_BASE        0xb0020
  62#define PNV_XSCOM_LPC_SIZE        0x4
  63
  64#define PNV_XSCOM_PSIHB_BASE      0x2010900
  65#define PNV_XSCOM_PSIHB_SIZE      0x20
  66
  67#define PNV_XSCOM_OCC_BASE        0x0066000
  68#define PNV_XSCOM_OCC_SIZE        0x6000
  69
  70#define PNV_XSCOM_PBA_BASE        0x2013f00
  71#define PNV_XSCOM_PBA_SIZE        0x40
  72
  73#define PNV_XSCOM_PBCQ_NEST_BASE  0x2012000
  74#define PNV_XSCOM_PBCQ_NEST_SIZE  0x46
  75
  76#define PNV_XSCOM_PBCQ_PCI_BASE   0x9012000
  77#define PNV_XSCOM_PBCQ_PCI_SIZE   0x15
  78
  79#define PNV_XSCOM_PBCQ_SPCI_BASE  0x9013c00
  80#define PNV_XSCOM_PBCQ_SPCI_SIZE  0x5
  81
  82/*
  83 * Layout of the XSCOM PCB addresses (POWER 9)
  84 */
  85#define PNV9_XSCOM_EC_BASE(core) \
  86    ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
  87#define PNV9_XSCOM_EC_SIZE        0x100000
  88
  89#define PNV9_XSCOM_EQ_BASE(core) \
  90    ((uint64_t)(((core) & 0x1C) + 0x40) << 22)
  91#define PNV9_XSCOM_EQ_SIZE        0x100000
  92
  93#define PNV9_XSCOM_OCC_BASE       PNV_XSCOM_OCC_BASE
  94#define PNV9_XSCOM_OCC_SIZE       0x8000
  95
  96#define PNV9_XSCOM_SBE_CTRL_BASE  0x00050008
  97#define PNV9_XSCOM_SBE_CTRL_SIZE  0x1
  98
  99#define PNV9_XSCOM_SBE_MBOX_BASE  0x000D0050
 100#define PNV9_XSCOM_SBE_MBOX_SIZE  0x16
 101
 102#define PNV9_XSCOM_PBA_BASE       0x5012b00
 103#define PNV9_XSCOM_PBA_SIZE       0x40
 104
 105#define PNV9_XSCOM_PSIHB_BASE     0x5012900
 106#define PNV9_XSCOM_PSIHB_SIZE     0x100
 107
 108#define PNV9_XSCOM_XIVE_BASE      0x5013000
 109#define PNV9_XSCOM_XIVE_SIZE      0x300
 110
 111#define PNV9_XSCOM_PEC_NEST_BASE  0x4010c00
 112#define PNV9_XSCOM_PEC_NEST_SIZE  0x100
 113
 114#define PNV9_XSCOM_PEC_PCI_BASE   0xd010800
 115#define PNV9_XSCOM_PEC_PCI_SIZE   0x200
 116
 117/* XSCOM PCI "pass-through" window to PHB SCOM */
 118#define PNV9_XSCOM_PEC_PCI_STK0   0x100
 119#define PNV9_XSCOM_PEC_PCI_STK1   0x140
 120#define PNV9_XSCOM_PEC_PCI_STK2   0x180
 121
 122/*
 123 * Layout of the XSCOM PCB addresses (POWER 10)
 124 */
 125#define PNV10_XSCOM_EQ_CHIPLET(core)  (0x20 + ((core) >> 2))
 126#define PNV10_XSCOM_EQ(chiplet)       ((chiplet) << 24)
 127#define PNV10_XSCOM_EC(proc)                    \
 128    ((0x2 << 16) | ((1 << (3 - (proc))) << 12))
 129
 130#define PNV10_XSCOM_QME(chiplet) \
 131        (PNV10_XSCOM_EQ(chiplet) | (0xE << 16))
 132
 133/*
 134 * Make the region larger by 0x1000 (instead of starting at an offset) so the
 135 * modelled addresses start from 0
 136 */
 137#define PNV10_XSCOM_QME_BASE(core)     \
 138    ((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core)))
 139#define PNV10_XSCOM_QME_SIZE        (0x8000 + 0x1000)
 140
 141#define PNV10_XSCOM_EQ_BASE(core)     \
 142    ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
 143#define PNV10_XSCOM_EQ_SIZE        0x20000
 144
 145#define PNV10_XSCOM_EC_BASE(core) \
 146    ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
 147#define PNV10_XSCOM_EC_SIZE        0x1000
 148
 149#define PNV10_XSCOM_PSIHB_BASE     0x3011D00
 150#define PNV10_XSCOM_PSIHB_SIZE     0x100
 151
 152#define PNV10_XSCOM_OCC_BASE       PNV9_XSCOM_OCC_BASE
 153#define PNV10_XSCOM_OCC_SIZE       PNV9_XSCOM_OCC_SIZE
 154
 155#define PNV10_XSCOM_SBE_CTRL_BASE  PNV9_XSCOM_SBE_CTRL_BASE
 156#define PNV10_XSCOM_SBE_CTRL_SIZE  PNV9_XSCOM_SBE_CTRL_SIZE
 157
 158#define PNV10_XSCOM_SBE_MBOX_BASE  PNV9_XSCOM_SBE_MBOX_BASE
 159#define PNV10_XSCOM_SBE_MBOX_SIZE  PNV9_XSCOM_SBE_MBOX_SIZE
 160
 161#define PNV10_XSCOM_PBA_BASE       0x01010CDA
 162#define PNV10_XSCOM_PBA_SIZE       0x40
 163
 164#define PNV10_XSCOM_XIVE2_BASE     0x2010800
 165#define PNV10_XSCOM_XIVE2_SIZE     0x400
 166
 167#define PNV10_XSCOM_PEC_NEST_BASE  0x3011800 /* index goes downwards ... */
 168#define PNV10_XSCOM_PEC_NEST_SIZE  0x100
 169
 170#define PNV10_XSCOM_PEC_PCI_BASE   0x8010800 /* index goes upwards ... */
 171#define PNV10_XSCOM_PEC_PCI_SIZE   0x200
 172
 173void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
 174int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
 175                 uint64_t xscom_base, uint64_t xscom_size,
 176                 const char *compat, int compat_size);
 177
 178void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
 179                             MemoryRegion *mr);
 180void pnv_xscom_region_init(MemoryRegion *mr,
 181                           Object *owner,
 182                           const MemoryRegionOps *ops,
 183                           void *opaque,
 184                           const char *name,
 185                           uint64_t size);
 186
 187#endif /* PPC_PNV_XSCOM_H */
 188