LXR qemu/include/hw/riscv/riscv

   1/*
   2 * QEMU RISC-V Hart Array interface
   3 *
   4 * Copyright (c) 2017 SiFive, Inc.
   5 *
   6 * Holds the state of a heterogenous array of RISC-V harts
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms and conditions of the GNU General Public License,
  10 * version 2 or later, as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15 * more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along with
  18 * this program.  If not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef HW_RISCV_HART_H
  22#define HW_RISCV_HART_H
  23
  24#include "hw/sysbus.h"
  25#include "target/riscv/cpu.h"
  26#include "qom/object.h"
  27
  28#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
  29
  30OBJECT_DECLARE_SIMPLE_TYPE(RISCVHartArrayState, RISCV_HART_ARRAY)
  31
  32struct RISCVHartArrayState {
  33    /*< private >*/
  34    SysBusDevice parent_obj;
  35
  36    /*< public >*/
  37    uint32_t num_harts;
  38    uint32_t hartid_base;
  39    char *cpu_type;
  40    uint64_t resetvec;
  41    RISCVCPU *harts;
  42};
  43
  44#endif
  45