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20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "qemu/cpu-float.h"
25#include "hw/registerfields.h"
26#include "cpu-qom.h"
27#include "exec/cpu-defs.h"
28#include "qapi/qapi-types-common.h"
29
30
31#define TCG_GUEST_DEFAULT_MO (0)
32
33#ifdef TARGET_AARCH64
34#define KVM_HAVE_MCE_INJECTION 1
35#endif
36
37#define EXCP_UDEF 1
38#define EXCP_SWI 2
39#define EXCP_PREFETCH_ABORT 3
40#define EXCP_DATA_ABORT 4
41#define EXCP_IRQ 5
42#define EXCP_FIQ 6
43#define EXCP_BKPT 7
44#define EXCP_EXCEPTION_EXIT 8
45#define EXCP_KERNEL_TRAP 9
46#define EXCP_HVC 11
47#define EXCP_HYP_TRAP 12
48#define EXCP_SMC 13
49#define EXCP_VIRQ 14
50#define EXCP_VFIQ 15
51#define EXCP_SEMIHOST 16
52#define EXCP_NOCP 17
53#define EXCP_INVSTATE 18
54#define EXCP_STKOF 19
55#define EXCP_LAZYFP 20
56#define EXCP_LSERR 21
57#define EXCP_UNALIGNED 22
58#define EXCP_DIVBYZERO 23
59#define EXCP_VSERR 24
60#define EXCP_GPC 25
61
62
63#define ARMV7M_EXCP_RESET 1
64#define ARMV7M_EXCP_NMI 2
65#define ARMV7M_EXCP_HARD 3
66#define ARMV7M_EXCP_MEM 4
67#define ARMV7M_EXCP_BUS 5
68#define ARMV7M_EXCP_USAGE 6
69#define ARMV7M_EXCP_SECURE 7
70#define ARMV7M_EXCP_SVC 11
71#define ARMV7M_EXCP_DEBUG 12
72#define ARMV7M_EXCP_PENDSV 14
73#define ARMV7M_EXCP_SYSTICK 15
74
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83
84enum {
85 M_REG_NS = 0,
86 M_REG_S = 1,
87 M_REG_NUM_BANKS = 2,
88};
89
90
91#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
92#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
93#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
94#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
95
96
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100
101
102#if HOST_BIG_ENDIAN
103#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
104#define offsetofhigh32(S, M) offsetof(S, M)
105#else
106#define offsetoflow32(S, M) offsetof(S, M)
107#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
108#endif
109
110
111#define ARM_CPU_IRQ 0
112#define ARM_CPU_FIQ 1
113#define ARM_CPU_VIRQ 2
114#define ARM_CPU_VFIQ 3
115
116
117
118
119
120#define TARGET_INSN_START_EXTRA_WORDS 2
121
122
123
124
125
126
127#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
128#define ARM_INSN_START_WORD2_SHIFT 14
129
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146
147typedef struct DynamicGDBXMLInfo {
148 char *desc;
149 int num;
150 union {
151 struct {
152 uint32_t *keys;
153 } cpregs;
154 } data;
155} DynamicGDBXMLInfo;
156
157
158typedef struct ARMGenericTimer {
159 uint64_t cval;
160 uint64_t ctl;
161} ARMGenericTimer;
162
163#define GTIMER_PHYS 0
164#define GTIMER_VIRT 1
165#define GTIMER_HYP 2
166#define GTIMER_SEC 3
167#define GTIMER_HYPVIRT 4
168#define NUM_GTIMERS 5
169
170#define VTCR_NSW (1u << 29)
171#define VTCR_NSA (1u << 30)
172#define VSTCR_SW VTCR_NSW
173#define VSTCR_SA VTCR_NSA
174
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201#ifdef TARGET_AARCH64
202# define ARM_MAX_VQ 16
203#else
204# define ARM_MAX_VQ 1
205#endif
206
207typedef struct ARMVectorReg {
208 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
209} ARMVectorReg;
210
211#ifdef TARGET_AARCH64
212
213typedef struct ARMPredicateReg {
214 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
215} ARMPredicateReg;
216
217
218typedef struct ARMPACKey {
219 uint64_t lo, hi;
220} ARMPACKey;
221#endif
222
223
224typedef struct CPUARMTBFlags {
225 uint32_t flags;
226 target_ulong flags2;
227} CPUARMTBFlags;
228
229typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
230
231typedef struct NVICState NVICState;
232
233typedef struct CPUArchState {
234
235 uint32_t regs[16];
236
237
238
239
240
241
242 uint64_t xregs[32];
243 uint64_t pc;
244
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254
255
256
257 uint32_t pstate;
258 bool aarch64;
259 bool thumb;
260
261
262 CPUARMTBFlags hflags;
263
264
265
266
267 uint32_t uncached_cpsr;
268 uint32_t spsr;
269
270
271 uint64_t banked_spsr[8];
272 uint32_t banked_r13[8];
273 uint32_t banked_r14[8];
274
275
276 uint32_t usr_regs[5];
277 uint32_t fiq_regs[5];
278
279
280 uint32_t CF;
281 uint32_t VF;
282 uint32_t NF;
283 uint32_t ZF;
284 uint32_t QF;
285 uint32_t GE;
286 uint32_t condexec_bits;
287 uint32_t btype;
288 uint64_t daif;
289 uint64_t svcr;
290
291 uint64_t elr_el[4];
292 uint64_t sp_el[4];
293
294
295 struct {
296 uint32_t c0_cpuid;
297 union {
298 struct {
299 uint64_t _unused_csselr0;
300 uint64_t csselr_ns;
301 uint64_t _unused_csselr1;
302 uint64_t csselr_s;
303 };
304 uint64_t csselr_el[4];
305 };
306 union {
307 struct {
308 uint64_t _unused_sctlr;
309 uint64_t sctlr_ns;
310 uint64_t hsctlr;
311 uint64_t sctlr_s;
312 };
313 uint64_t sctlr_el[4];
314 };
315 uint64_t vsctlr;
316 uint64_t cpacr_el1;
317 uint64_t cptr_el[4];
318 uint32_t c1_xscaleauxcr;
319 uint64_t sder;
320 uint32_t nsacr;
321 union {
322 struct {
323 uint64_t _unused_ttbr0_0;
324 uint64_t ttbr0_ns;
325 uint64_t _unused_ttbr0_1;
326 uint64_t ttbr0_s;
327 };
328 uint64_t ttbr0_el[4];
329 };
330 union {
331 struct {
332 uint64_t _unused_ttbr1_0;
333 uint64_t ttbr1_ns;
334 uint64_t _unused_ttbr1_1;
335 uint64_t ttbr1_s;
336 };
337 uint64_t ttbr1_el[4];
338 };
339 uint64_t vttbr_el2;
340 uint64_t vsttbr_el2;
341
342 uint64_t tcr_el[4];
343 uint64_t vtcr_el2;
344 uint64_t vstcr_el2;
345 uint32_t c2_data;
346 uint32_t c2_insn;
347 union {
348
349
350 struct {
351 uint64_t dacr_ns;
352 uint64_t dacr_s;
353 };
354 struct {
355 uint64_t dacr32_el2;
356 };
357 };
358 uint32_t pmsav5_data_ap;
359 uint32_t pmsav5_insn_ap;
360 uint64_t hcr_el2;
361 uint64_t hcrx_el2;
362 uint64_t scr_el3;
363 union {
364 struct {
365 uint64_t ifsr_ns;
366 uint64_t ifsr_s;
367 };
368 struct {
369 uint64_t ifsr32_el2;
370 };
371 };
372 union {
373 struct {
374 uint64_t _unused_dfsr;
375 uint64_t dfsr_ns;
376 uint64_t hsr;
377 uint64_t dfsr_s;
378 };
379 uint64_t esr_el[4];
380 };
381 uint32_t c6_region[8];
382 union {
383 struct {
384 uint64_t _unused_far0;
385#if HOST_BIG_ENDIAN
386 uint32_t ifar_ns;
387 uint32_t dfar_ns;
388 uint32_t ifar_s;
389 uint32_t dfar_s;
390#else
391 uint32_t dfar_ns;
392 uint32_t ifar_ns;
393 uint32_t dfar_s;
394 uint32_t ifar_s;
395#endif
396 uint64_t _unused_far3;
397 };
398 uint64_t far_el[4];
399 };
400 uint64_t hpfar_el2;
401 uint64_t hstr_el2;
402 union {
403 struct {
404 uint64_t _unused_par_0;
405 uint64_t par_ns;
406 uint64_t _unused_par_1;
407 uint64_t par_s;
408 };
409 uint64_t par_el[4];
410 };
411
412 uint32_t c9_insn;
413 uint32_t c9_data;
414 uint64_t c9_pmcr;
415 uint64_t c9_pmcnten;
416 uint64_t c9_pmovsr;
417 uint64_t c9_pmuserenr;
418 uint64_t c9_pmselr;
419 uint64_t c9_pminten;
420 union {
421 struct {
422#if HOST_BIG_ENDIAN
423 uint64_t _unused_mair_0;
424 uint32_t mair1_ns;
425 uint32_t mair0_ns;
426 uint64_t _unused_mair_1;
427 uint32_t mair1_s;
428 uint32_t mair0_s;
429#else
430 uint64_t _unused_mair_0;
431 uint32_t mair0_ns;
432 uint32_t mair1_ns;
433 uint64_t _unused_mair_1;
434 uint32_t mair0_s;
435 uint32_t mair1_s;
436#endif
437 };
438 uint64_t mair_el[4];
439 };
440 union {
441 struct {
442 uint64_t _unused_vbar;
443 uint64_t vbar_ns;
444 uint64_t hvbar;
445 uint64_t vbar_s;
446 };
447 uint64_t vbar_el[4];
448 };
449 uint32_t mvbar;
450 uint64_t rvbar;
451 struct {
452 uint32_t fcseidr_ns;
453 uint32_t fcseidr_s;
454 };
455 union {
456 struct {
457 uint64_t _unused_contextidr_0;
458 uint64_t contextidr_ns;
459 uint64_t _unused_contextidr_1;
460 uint64_t contextidr_s;
461 };
462 uint64_t contextidr_el[4];
463 };
464 union {
465 struct {
466 uint64_t tpidrurw_ns;
467 uint64_t tpidrprw_ns;
468 uint64_t htpidr;
469 uint64_t _tpidr_el3;
470 };
471 uint64_t tpidr_el[4];
472 };
473 uint64_t tpidr2_el0;
474
475 uint64_t tpidrurw_s;
476 uint64_t tpidrprw_s;
477 uint64_t tpidruro_s;
478
479 union {
480 uint64_t tpidruro_ns;
481 uint64_t tpidrro_el[1];
482 };
483 uint64_t c14_cntfrq;
484 uint64_t c14_cntkctl;
485 uint64_t cnthctl_el2;
486 uint64_t cntvoff_el2;
487 ARMGenericTimer c14_timer[NUM_GTIMERS];
488 uint32_t c15_cpar;
489 uint32_t c15_ticonfig;
490 uint32_t c15_i_max;
491 uint32_t c15_i_min;
492 uint32_t c15_threadid;
493 uint32_t c15_config_base_address;
494 uint32_t c15_diagnostic;
495 uint32_t c15_power_diagnostic;
496 uint32_t c15_power_control;
497 uint64_t dbgbvr[16];
498 uint64_t dbgbcr[16];
499 uint64_t dbgwvr[16];
500 uint64_t dbgwcr[16];
501 uint64_t dbgclaim;
502 uint64_t mdscr_el1;
503 uint64_t oslsr_el1;
504 uint64_t osdlr_el1;
505 uint64_t mdcr_el2;
506 uint64_t mdcr_el3;
507
508
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510
511
512 uint64_t c15_ccnt;
513
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518
519
520 uint64_t c15_ccnt_delta;
521 uint64_t c14_pmevcntr[31];
522 uint64_t c14_pmevcntr_delta[31];
523 uint64_t c14_pmevtyper[31];
524 uint64_t pmccfiltr_el0;
525 uint64_t vpidr_el2;
526 uint64_t vmpidr_el2;
527 uint64_t tfsr_el[4];
528 uint64_t gcr_el1;
529 uint64_t rgsr_el1;
530
531
532 uint64_t disr_el1;
533 uint64_t vdisr_el2;
534 uint64_t vsesr_el2;
535
536
537
538
539
540
541
542 uint64_t fgt_read[2];
543 uint64_t fgt_write[2];
544 uint64_t fgt_exec[1];
545
546
547 uint64_t gpccr_el3;
548 uint64_t gptbr_el3;
549 uint64_t mfar_el3;
550 } cp15;
551
552 struct {
553
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562
563
564 uint32_t other_sp;
565 uint32_t other_ss_msp;
566 uint32_t other_ss_psp;
567 uint32_t vecbase[M_REG_NUM_BANKS];
568 uint32_t basepri[M_REG_NUM_BANKS];
569 uint32_t control[M_REG_NUM_BANKS];
570 uint32_t ccr[M_REG_NUM_BANKS];
571 uint32_t cfsr[M_REG_NUM_BANKS];
572 uint32_t hfsr;
573 uint32_t dfsr;
574 uint32_t sfsr;
575 uint32_t mmfar[M_REG_NUM_BANKS];
576 uint32_t bfar;
577 uint32_t sfar;
578 unsigned mpu_ctrl[M_REG_NUM_BANKS];
579 int exception;
580 uint32_t primask[M_REG_NUM_BANKS];
581 uint32_t faultmask[M_REG_NUM_BANKS];
582 uint32_t aircr;
583 uint32_t secure;
584 uint32_t csselr[M_REG_NUM_BANKS];
585 uint32_t scr[M_REG_NUM_BANKS];
586 uint32_t msplim[M_REG_NUM_BANKS];
587 uint32_t psplim[M_REG_NUM_BANKS];
588 uint32_t fpcar[M_REG_NUM_BANKS];
589 uint32_t fpccr[M_REG_NUM_BANKS];
590 uint32_t fpdscr[M_REG_NUM_BANKS];
591 uint32_t cpacr[M_REG_NUM_BANKS];
592 uint32_t nsacr;
593 uint32_t ltpsize;
594 uint32_t vpr;
595 } v7m;
596
597
598
599
600
601
602
603 struct {
604 uint32_t syndrome;
605 uint32_t fsr;
606 uint64_t vaddress;
607 uint32_t target_el;
608
609
610
611 } exception;
612
613
614 struct {
615 uint8_t pending;
616 uint8_t has_esr;
617 uint64_t esr;
618 } serror;
619
620 uint8_t ext_dabt_raised;
621
622
623 uint32_t irq_line_state;
624
625
626 uint32_t teecr;
627 uint32_t teehbr;
628
629
630 struct {
631 ARMVectorReg zregs[32];
632
633#ifdef TARGET_AARCH64
634
635#define FFR_PRED_NUM 16
636 ARMPredicateReg pregs[17];
637
638 ARMPredicateReg preg_tmp;
639#endif
640
641
642 uint32_t qc[4] QEMU_ALIGNED(16);
643 int vec_len;
644 int vec_stride;
645
646 uint32_t xregs[16];
647
648
649 uint32_t scratch[8];
650
651
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677
678 float_status fp_status;
679 float_status fp_status_f16;
680 float_status standard_fp_status;
681 float_status standard_fp_status_f16;
682
683 uint64_t zcr_el[4];
684 uint64_t smcr_el[4];
685 } vfp;
686
687 uint64_t exclusive_addr;
688 uint64_t exclusive_val;
689
690
691
692
693
694
695
696 uint64_t exclusive_high;
697
698
699 struct {
700 uint64_t regs[16];
701 uint64_t val;
702
703 uint32_t cregs[16];
704 } iwmmxt;
705
706#ifdef TARGET_AARCH64
707 struct {
708 ARMPACKey apia;
709 ARMPACKey apib;
710 ARMPACKey apda;
711 ARMPACKey apdb;
712 ARMPACKey apga;
713 } keys;
714
715 uint64_t scxtnum_el[4];
716
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736
737 ARMVectorReg zarray[ARM_MAX_VQ * 16];
738#endif
739
740 struct CPUBreakpoint *cpu_breakpoint[16];
741 struct CPUWatchpoint *cpu_watchpoint[16];
742
743
744 ARMMMUFaultInfo *tlb_fi;
745
746
747 struct {} end_reset_fields;
748
749
750
751
752 uint64_t features;
753
754
755 struct {
756 uint32_t *drbar;
757 uint32_t *drsr;
758 uint32_t *dracr;
759 uint32_t rnr[M_REG_NUM_BANKS];
760 } pmsav7;
761
762
763 struct {
764
765
766
767
768
769 uint32_t *rbar[M_REG_NUM_BANKS];
770 uint32_t *rlar[M_REG_NUM_BANKS];
771 uint32_t *hprbar;
772 uint32_t *hprlar;
773 uint32_t mair0[M_REG_NUM_BANKS];
774 uint32_t mair1[M_REG_NUM_BANKS];
775 uint32_t hprselr;
776 } pmsav8;
777
778
779 struct {
780 uint32_t *rbar;
781 uint32_t *rlar;
782 uint32_t rnr;
783 uint32_t ctrl;
784 } sau;
785
786#if !defined(CONFIG_USER_ONLY)
787 NVICState *nvic;
788 const struct arm_boot_info *boot_info;
789
790 void *gicv3state;
791#else
792
793 bool eabi;
794#endif
795
796#ifdef TARGET_TAGGED_ADDRESSES
797
798 bool tagged_addr_enable;
799#endif
800} CPUARMState;
801
802static inline void set_feature(CPUARMState *env, int feature)
803{
804 env->features |= 1ULL << feature;
805}
806
807static inline void unset_feature(CPUARMState *env, int feature)
808{
809 env->features &= ~(1ULL << feature);
810}
811
812
813
814
815
816
817typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
818typedef struct ARMELChangeHook ARMELChangeHook;
819struct ARMELChangeHook {
820 ARMELChangeHookFn *hook;
821 void *opaque;
822 QLIST_ENTRY(ARMELChangeHook) node;
823};
824
825
826
827typedef enum ARMPSCIState {
828 PSCI_ON = 0,
829 PSCI_OFF = 1,
830 PSCI_ON_PENDING = 2
831} ARMPSCIState;
832
833typedef struct ARMISARegisters ARMISARegisters;
834
835
836
837
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839
840
841
842
843
844typedef struct {
845 uint32_t map, init, supported;
846} ARMVQMap;
847
848
849
850
851
852
853
854struct ArchCPU {
855
856 CPUState parent_obj;
857
858
859 CPUNegativeOffsetState neg;
860 CPUARMState env;
861
862
863 GHashTable *cp_regs;
864
865
866
867
868
869
870
871 uint64_t *cpreg_indexes;
872
873 uint64_t *cpreg_values;
874
875 int32_t cpreg_array_len;
876
877
878
879
880 uint64_t *cpreg_vmstate_indexes;
881 uint64_t *cpreg_vmstate_values;
882 int32_t cpreg_vmstate_array_len;
883
884 DynamicGDBXMLInfo dyn_sysreg_xml;
885 DynamicGDBXMLInfo dyn_svereg_xml;
886 DynamicGDBXMLInfo dyn_m_systemreg_xml;
887 DynamicGDBXMLInfo dyn_m_secextreg_xml;
888
889
890 QEMUTimer *gt_timer[NUM_GTIMERS];
891
892
893
894
895 QEMUTimer *pmu_timer;
896
897 qemu_irq gt_timer_outputs[NUM_GTIMERS];
898
899 qemu_irq gicv3_maintenance_interrupt;
900
901 qemu_irq pmu_interrupt;
902
903
904 MemoryRegion *secure_memory;
905
906
907 MemoryRegion *tag_memory;
908 MemoryRegion *secure_tag_memory;
909
910
911 Object *idau;
912
913
914 const char *dtb_compatible;
915
916
917
918
919
920 uint32_t psci_version;
921
922
923 ARMPSCIState power_state;
924
925
926 bool has_el2;
927
928 bool has_el3;
929
930 bool has_pmu;
931
932 bool has_vfp;
933
934 bool has_vfp_d32;
935
936 bool has_neon;
937
938 bool has_dsp;
939
940
941 bool has_mpu;
942
943 uint32_t pmsav7_dregion;
944
945 uint32_t pmsav8r_hdregion;
946
947 uint32_t sau_sregion;
948
949
950
951
952 uint32_t psci_conduit;
953
954
955 uint32_t init_svtor;
956
957 uint32_t init_nsvtor;
958
959
960
961
962 uint32_t kvm_target;
963
964#ifdef CONFIG_KVM
965
966 uint32_t kvm_init_features[7];
967
968
969
970
971 bool kvm_adjvtime;
972 bool kvm_vtime_dirty;
973 uint64_t kvm_vtime;
974
975
976 OnOffAuto kvm_steal_time;
977#endif
978
979
980 bool mp_is_up;
981
982
983
984
985 bool host_cpu_probe_failed;
986
987
988
989
990 int32_t core_count;
991
992
993
994
995
996
997
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1007
1008
1009 struct ARMISARegisters {
1010 uint32_t id_isar0;
1011 uint32_t id_isar1;
1012 uint32_t id_isar2;
1013 uint32_t id_isar3;
1014 uint32_t id_isar4;
1015 uint32_t id_isar5;
1016 uint32_t id_isar6;
1017 uint32_t id_mmfr0;
1018 uint32_t id_mmfr1;
1019 uint32_t id_mmfr2;
1020 uint32_t id_mmfr3;
1021 uint32_t id_mmfr4;
1022 uint32_t id_mmfr5;
1023 uint32_t id_pfr0;
1024 uint32_t id_pfr1;
1025 uint32_t id_pfr2;
1026 uint32_t mvfr0;
1027 uint32_t mvfr1;
1028 uint32_t mvfr2;
1029 uint32_t id_dfr0;
1030 uint32_t id_dfr1;
1031 uint32_t dbgdidr;
1032 uint32_t dbgdevid;
1033 uint32_t dbgdevid1;
1034 uint64_t id_aa64isar0;
1035 uint64_t id_aa64isar1;
1036 uint64_t id_aa64pfr0;
1037 uint64_t id_aa64pfr1;
1038 uint64_t id_aa64mmfr0;
1039 uint64_t id_aa64mmfr1;
1040 uint64_t id_aa64mmfr2;
1041 uint64_t id_aa64dfr0;
1042 uint64_t id_aa64dfr1;
1043 uint64_t id_aa64zfr0;
1044 uint64_t id_aa64smfr0;
1045 uint64_t reset_pmcr_el0;
1046 } isar;
1047 uint64_t midr;
1048 uint32_t revidr;
1049 uint32_t reset_fpsid;
1050 uint64_t ctr;
1051 uint32_t reset_sctlr;
1052 uint64_t pmceid0;
1053 uint64_t pmceid1;
1054 uint32_t id_afr0;
1055 uint64_t id_aa64afr0;
1056 uint64_t id_aa64afr1;
1057 uint64_t clidr;
1058 uint64_t mp_affinity;
1059
1060
1061
1062 uint64_t ccsidr[16];
1063 uint64_t reset_cbar;
1064 uint32_t reset_auxcr;
1065 bool reset_hivecs;
1066 uint8_t reset_l0gptsz;
1067
1068
1069
1070
1071
1072 bool prop_pauth;
1073 bool prop_pauth_impdef;
1074 bool prop_lpa2;
1075
1076
1077 uint32_t dcz_blocksize;
1078 uint64_t rvbar_prop;
1079
1080
1081 int gic_num_lrs;
1082 int gic_vpribits;
1083 int gic_vprebits;
1084 int gic_pribits;
1085
1086
1087
1088
1089
1090
1091 bool cfgend;
1092
1093 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1094 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1095
1096 int32_t node_id;
1097
1098
1099 uint8_t device_irq_level;
1100
1101
1102 uint32_t sve_max_vq;
1103
1104#ifdef CONFIG_USER_ONLY
1105
1106 uint32_t sve_default_vq;
1107 uint32_t sme_default_vq;
1108#endif
1109
1110 ARMVQMap sve_vq;
1111 ARMVQMap sme_vq;
1112
1113
1114 uint64_t gt_cntfrq_hz;
1115};
1116
1117unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1118
1119void arm_cpu_post_init(Object *obj);
1120
1121uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1122
1123#ifndef CONFIG_USER_ONLY
1124extern const VMStateDescription vmstate_arm_cpu;
1125
1126void arm_cpu_do_interrupt(CPUState *cpu);
1127void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1128
1129hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1130 MemTxAttrs *attrs);
1131#endif
1132
1133int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1134int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1135
1136
1137
1138
1139
1140const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1141
1142int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1143 int cpuid, DumpState *s);
1144int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1145 int cpuid, DumpState *s);
1146
1147#ifdef TARGET_AARCH64
1148int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1149int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1150void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1151void aarch64_sve_change_el(CPUARMState *env, int old_el,
1152 int new_el, bool el0_a64);
1153void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1165{
1166#if HOST_BIG_ENDIAN
1167 int i;
1168
1169 for (i = 0; i < nr; ++i) {
1170 dst[i] = bswap64(src[i]);
1171 }
1172
1173 return dst;
1174#else
1175 return src;
1176#endif
1177}
1178
1179#else
1180static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1181static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1182 int n, bool a)
1183{ }
1184#endif
1185
1186void aarch64_sync_32_to_64(CPUARMState *env);
1187void aarch64_sync_64_to_32(CPUARMState *env);
1188
1189int fp_exception_el(CPUARMState *env, int cur_el);
1190int sve_exception_el(CPUARMState *env, int cur_el);
1191int sme_exception_el(CPUARMState *env, int cur_el);
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
1204
1205
1206uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
1207
1208static inline bool is_a64(CPUARMState *env)
1209{
1210 return env->aarch64;
1211}
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221void pmu_op_start(CPUARMState *env);
1222void pmu_op_finish(CPUARMState *env);
1223
1224
1225
1226
1227void arm_pmu_timer_cb(void *opaque);
1228
1229
1230
1231
1232void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1233void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1234
1235
1236
1237
1238
1239
1240
1241
1242void pmu_init(ARMCPU *cpu);
1243
1244
1245
1246
1247
1248
1249
1250#define SCTLR_M (1U << 0)
1251#define SCTLR_A (1U << 1)
1252#define SCTLR_C (1U << 2)
1253#define SCTLR_W (1U << 3)
1254#define SCTLR_nTLSMD_32 (1U << 3)
1255#define SCTLR_SA (1U << 3)
1256#define SCTLR_P (1U << 4)
1257#define SCTLR_LSMAOE_32 (1U << 4)
1258#define SCTLR_SA0 (1U << 4)
1259#define SCTLR_D (1U << 5)
1260#define SCTLR_CP15BEN (1U << 5)
1261#define SCTLR_L (1U << 6)
1262#define SCTLR_nAA (1U << 6)
1263#define SCTLR_B (1U << 7)
1264#define SCTLR_ITD (1U << 7)
1265#define SCTLR_S (1U << 8)
1266#define SCTLR_SED (1U << 8)
1267#define SCTLR_R (1U << 9)
1268#define SCTLR_UMA (1U << 9)
1269#define SCTLR_F (1U << 10)
1270#define SCTLR_SW (1U << 10)
1271#define SCTLR_EnRCTX (1U << 10)
1272#define SCTLR_Z (1U << 11)
1273#define SCTLR_EOS (1U << 11)
1274#define SCTLR_I (1U << 12)
1275#define SCTLR_V (1U << 13)
1276#define SCTLR_EnDB (1U << 13)
1277#define SCTLR_RR (1U << 14)
1278#define SCTLR_DZE (1U << 14)
1279#define SCTLR_L4 (1U << 15)
1280#define SCTLR_UCT (1U << 15)
1281#define SCTLR_DT (1U << 16)
1282#define SCTLR_nTWI (1U << 16)
1283#define SCTLR_HA (1U << 17)
1284#define SCTLR_BR (1U << 17)
1285#define SCTLR_IT (1U << 18)
1286#define SCTLR_nTWE (1U << 18)
1287#define SCTLR_WXN (1U << 19)
1288#define SCTLR_ST (1U << 20)
1289#define SCTLR_UWXN (1U << 20)
1290#define SCTLR_TSCXT (1U << 20)
1291#define SCTLR_FI (1U << 21)
1292#define SCTLR_IESB (1U << 21)
1293#define SCTLR_U (1U << 22)
1294#define SCTLR_EIS (1U << 22)
1295#define SCTLR_XP (1U << 23)
1296#define SCTLR_SPAN (1U << 23)
1297#define SCTLR_VE (1U << 24)
1298#define SCTLR_E0E (1U << 24)
1299#define SCTLR_EE (1U << 25)
1300#define SCTLR_L2 (1U << 26)
1301#define SCTLR_UCI (1U << 26)
1302#define SCTLR_NMFI (1U << 27)
1303#define SCTLR_EnDA (1U << 27)
1304#define SCTLR_TRE (1U << 28)
1305#define SCTLR_nTLSMD_64 (1U << 28)
1306#define SCTLR_AFE (1U << 29)
1307#define SCTLR_LSMAOE_64 (1U << 29)
1308#define SCTLR_TE (1U << 30)
1309#define SCTLR_EnIB (1U << 30)
1310#define SCTLR_EnIA (1U << 31)
1311#define SCTLR_DSSBS_32 (1U << 31)
1312#define SCTLR_BT0 (1ULL << 35)
1313#define SCTLR_BT1 (1ULL << 36)
1314#define SCTLR_ITFSB (1ULL << 37)
1315#define SCTLR_TCF0 (3ULL << 38)
1316#define SCTLR_TCF (3ULL << 40)
1317#define SCTLR_ATA0 (1ULL << 42)
1318#define SCTLR_ATA (1ULL << 43)
1319#define SCTLR_DSSBS_64 (1ULL << 44)
1320#define SCTLR_TWEDEn (1ULL << 45)
1321#define SCTLR_TWEDEL MAKE_64_MASK(46, 4)
1322#define SCTLR_TMT0 (1ULL << 50)
1323#define SCTLR_TMT (1ULL << 51)
1324#define SCTLR_TME0 (1ULL << 52)
1325#define SCTLR_TME (1ULL << 53)
1326#define SCTLR_EnASR (1ULL << 54)
1327#define SCTLR_EnAS0 (1ULL << 55)
1328#define SCTLR_EnALS (1ULL << 56)
1329#define SCTLR_EPAN (1ULL << 57)
1330#define SCTLR_EnTP2 (1ULL << 60)
1331#define SCTLR_NMI (1ULL << 61)
1332#define SCTLR_SPINTMASK (1ULL << 62)
1333#define SCTLR_TIDCP (1ULL << 63)
1334
1335
1336FIELD(CPACR, CP10, 20, 2)
1337FIELD(CPACR, CP11, 22, 2)
1338FIELD(CPACR, TRCDIS, 28, 1)
1339FIELD(CPACR, D32DIS, 30, 1)
1340FIELD(CPACR, ASEDIS, 31, 1)
1341
1342
1343FIELD(CPACR_EL1, ZEN, 16, 2)
1344FIELD(CPACR_EL1, FPEN, 20, 2)
1345FIELD(CPACR_EL1, SMEN, 24, 2)
1346FIELD(CPACR_EL1, TTA, 28, 1)
1347
1348
1349FIELD(HCPTR, TCP10, 10, 1)
1350FIELD(HCPTR, TCP11, 11, 1)
1351FIELD(HCPTR, TASE, 15, 1)
1352FIELD(HCPTR, TTA, 20, 1)
1353FIELD(HCPTR, TAM, 30, 1)
1354FIELD(HCPTR, TCPAC, 31, 1)
1355
1356
1357FIELD(CPTR_EL2, TZ, 8, 1)
1358FIELD(CPTR_EL2, TFP, 10, 1)
1359FIELD(CPTR_EL2, TSM, 12, 1)
1360FIELD(CPTR_EL2, ZEN, 16, 2)
1361FIELD(CPTR_EL2, FPEN, 20, 2)
1362FIELD(CPTR_EL2, SMEN, 24, 2)
1363FIELD(CPTR_EL2, TTA, 28, 1)
1364FIELD(CPTR_EL2, TAM, 30, 1)
1365FIELD(CPTR_EL2, TCPAC, 31, 1)
1366
1367
1368FIELD(CPTR_EL3, EZ, 8, 1)
1369FIELD(CPTR_EL3, TFP, 10, 1)
1370FIELD(CPTR_EL3, ESM, 12, 1)
1371FIELD(CPTR_EL3, TTA, 20, 1)
1372FIELD(CPTR_EL3, TAM, 30, 1)
1373FIELD(CPTR_EL3, TCPAC, 31, 1)
1374
1375#define MDCR_MTPME (1U << 28)
1376#define MDCR_TDCC (1U << 27)
1377#define MDCR_HLP (1U << 26)
1378#define MDCR_SCCD (1U << 23)
1379#define MDCR_HCCD (1U << 23)
1380#define MDCR_EPMAD (1U << 21)
1381#define MDCR_EDAD (1U << 20)
1382#define MDCR_TTRF (1U << 19)
1383#define MDCR_STE (1U << 18)
1384#define MDCR_SPME (1U << 17)
1385#define MDCR_HPMD (1U << 17)
1386#define MDCR_SDD (1U << 16)
1387#define MDCR_SPD (3U << 14)
1388#define MDCR_TDRA (1U << 11)
1389#define MDCR_TDOSA (1U << 10)
1390#define MDCR_TDA (1U << 9)
1391#define MDCR_TDE (1U << 8)
1392#define MDCR_HPME (1U << 7)
1393#define MDCR_TPM (1U << 6)
1394#define MDCR_TPMCR (1U << 5)
1395#define MDCR_HPMN (0x1fU)
1396
1397
1398#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
1399 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
1400 MDCR_STE | MDCR_SPME | MDCR_SPD)
1401
1402#define CPSR_M (0x1fU)
1403#define CPSR_T (1U << 5)
1404#define CPSR_F (1U << 6)
1405#define CPSR_I (1U << 7)
1406#define CPSR_A (1U << 8)
1407#define CPSR_E (1U << 9)
1408#define CPSR_IT_2_7 (0xfc00U)
1409#define CPSR_GE (0xfU << 16)
1410#define CPSR_IL (1U << 20)
1411#define CPSR_DIT (1U << 21)
1412#define CPSR_PAN (1U << 22)
1413#define CPSR_SSBS (1U << 23)
1414#define CPSR_J (1U << 24)
1415#define CPSR_IT_0_1 (3U << 25)
1416#define CPSR_Q (1U << 27)
1417#define CPSR_V (1U << 28)
1418#define CPSR_C (1U << 29)
1419#define CPSR_Z (1U << 30)
1420#define CPSR_N (1U << 31)
1421#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1422#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1423
1424#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1425#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1426 | CPSR_NZCV)
1427
1428#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1429
1430#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1431
1432
1433#define XPSR_EXCP 0x1ffU
1434#define XPSR_SPREALIGN (1U << 9)
1435#define XPSR_IT_2_7 CPSR_IT_2_7
1436#define XPSR_GE CPSR_GE
1437#define XPSR_SFPA (1U << 20)
1438#define XPSR_T (1U << 24)
1439#define XPSR_IT_0_1 CPSR_IT_0_1
1440#define XPSR_Q CPSR_Q
1441#define XPSR_V CPSR_V
1442#define XPSR_C CPSR_C
1443#define XPSR_Z CPSR_Z
1444#define XPSR_N CPSR_N
1445#define XPSR_NZCV CPSR_NZCV
1446#define XPSR_IT CPSR_IT
1447
1448#define TTBCR_N (7U << 0)
1449#define TTBCR_T0SZ (7U << 0)
1450#define TTBCR_PD0 (1U << 4)
1451#define TTBCR_PD1 (1U << 5)
1452#define TTBCR_EPD0 (1U << 7)
1453#define TTBCR_IRGN0 (3U << 8)
1454#define TTBCR_ORGN0 (3U << 10)
1455#define TTBCR_SH0 (3U << 12)
1456#define TTBCR_T1SZ (3U << 16)
1457#define TTBCR_A1 (1U << 22)
1458#define TTBCR_EPD1 (1U << 23)
1459#define TTBCR_IRGN1 (3U << 24)
1460#define TTBCR_ORGN1 (3U << 26)
1461#define TTBCR_SH1 (1U << 28)
1462#define TTBCR_EAE (1U << 31)
1463
1464FIELD(VTCR, T0SZ, 0, 6)
1465FIELD(VTCR, SL0, 6, 2)
1466FIELD(VTCR, IRGN0, 8, 2)
1467FIELD(VTCR, ORGN0, 10, 2)
1468FIELD(VTCR, SH0, 12, 2)
1469FIELD(VTCR, TG0, 14, 2)
1470FIELD(VTCR, PS, 16, 3)
1471FIELD(VTCR, VS, 19, 1)
1472FIELD(VTCR, HA, 21, 1)
1473FIELD(VTCR, HD, 22, 1)
1474FIELD(VTCR, HWU59, 25, 1)
1475FIELD(VTCR, HWU60, 26, 1)
1476FIELD(VTCR, HWU61, 27, 1)
1477FIELD(VTCR, HWU62, 28, 1)
1478FIELD(VTCR, NSW, 29, 1)
1479FIELD(VTCR, NSA, 30, 1)
1480FIELD(VTCR, DS, 32, 1)
1481FIELD(VTCR, SL2, 33, 1)
1482
1483
1484
1485
1486
1487#define PSTATE_SP (1U)
1488#define PSTATE_M (0xFU)
1489#define PSTATE_nRW (1U << 4)
1490#define PSTATE_F (1U << 6)
1491#define PSTATE_I (1U << 7)
1492#define PSTATE_A (1U << 8)
1493#define PSTATE_D (1U << 9)
1494#define PSTATE_BTYPE (3U << 10)
1495#define PSTATE_SSBS (1U << 12)
1496#define PSTATE_IL (1U << 20)
1497#define PSTATE_SS (1U << 21)
1498#define PSTATE_PAN (1U << 22)
1499#define PSTATE_UAO (1U << 23)
1500#define PSTATE_DIT (1U << 24)
1501#define PSTATE_TCO (1U << 25)
1502#define PSTATE_V (1U << 28)
1503#define PSTATE_C (1U << 29)
1504#define PSTATE_Z (1U << 30)
1505#define PSTATE_N (1U << 31)
1506#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1507#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1508#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1509
1510#define PSTATE_MODE_EL3h 13
1511#define PSTATE_MODE_EL3t 12
1512#define PSTATE_MODE_EL2h 9
1513#define PSTATE_MODE_EL2t 8
1514#define PSTATE_MODE_EL1h 5
1515#define PSTATE_MODE_EL1t 4
1516#define PSTATE_MODE_EL0t 0
1517
1518
1519FIELD(SVCR, SM, 0, 1)
1520FIELD(SVCR, ZA, 1, 1)
1521
1522
1523FIELD(SMCR, LEN, 0, 4)
1524FIELD(SMCR, FA64, 31, 1)
1525
1526
1527
1528
1529void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1530
1531
1532static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1533{
1534 return (el << 2) | handler;
1535}
1536
1537
1538
1539
1540
1541static inline uint32_t pstate_read(CPUARMState *env)
1542{
1543 int ZF;
1544
1545 ZF = (env->ZF == 0);
1546 return (env->NF & 0x80000000) | (ZF << 30)
1547 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1548 | env->pstate | env->daif | (env->btype << 10);
1549}
1550
1551static inline void pstate_write(CPUARMState *env, uint32_t val)
1552{
1553 env->ZF = (~val) & PSTATE_Z;
1554 env->NF = val;
1555 env->CF = (val >> 29) & 1;
1556 env->VF = (val << 3) & 0x80000000;
1557 env->daif = val & PSTATE_DAIF;
1558 env->btype = (val >> 10) & 3;
1559 env->pstate = val & ~CACHED_PSTATE_BITS;
1560}
1561
1562
1563uint32_t cpsr_read(CPUARMState *env);
1564
1565typedef enum CPSRWriteType {
1566 CPSRWriteByInstr = 0,
1567 CPSRWriteExceptionReturn = 1,
1568 CPSRWriteRaw = 2,
1569
1570 CPSRWriteByGDBStub = 3,
1571} CPSRWriteType;
1572
1573
1574
1575
1576
1577
1578
1579void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1580 CPSRWriteType write_type);
1581
1582
1583static inline uint32_t xpsr_read(CPUARMState *env)
1584{
1585 int ZF;
1586 ZF = (env->ZF == 0);
1587 return (env->NF & 0x80000000) | (ZF << 30)
1588 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1589 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1590 | ((env->condexec_bits & 0xfc) << 8)
1591 | (env->GE << 16)
1592 | env->v7m.exception;
1593}
1594
1595
1596static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1597{
1598 if (mask & XPSR_NZCV) {
1599 env->ZF = (~val) & XPSR_Z;
1600 env->NF = val;
1601 env->CF = (val >> 29) & 1;
1602 env->VF = (val << 3) & 0x80000000;
1603 }
1604 if (mask & XPSR_Q) {
1605 env->QF = ((val & XPSR_Q) != 0);
1606 }
1607 if (mask & XPSR_GE) {
1608 env->GE = (val & XPSR_GE) >> 16;
1609 }
1610#ifndef CONFIG_USER_ONLY
1611 if (mask & XPSR_T) {
1612 env->thumb = ((val & XPSR_T) != 0);
1613 }
1614 if (mask & XPSR_IT_0_1) {
1615 env->condexec_bits &= ~3;
1616 env->condexec_bits |= (val >> 25) & 3;
1617 }
1618 if (mask & XPSR_IT_2_7) {
1619 env->condexec_bits &= 3;
1620 env->condexec_bits |= (val >> 8) & 0xfc;
1621 }
1622 if (mask & XPSR_EXCP) {
1623
1624 write_v7m_exception(env, val & XPSR_EXCP);
1625 }
1626#endif
1627}
1628
1629#define HCR_VM (1ULL << 0)
1630#define HCR_SWIO (1ULL << 1)
1631#define HCR_PTW (1ULL << 2)
1632#define HCR_FMO (1ULL << 3)
1633#define HCR_IMO (1ULL << 4)
1634#define HCR_AMO (1ULL << 5)
1635#define HCR_VF (1ULL << 6)
1636#define HCR_VI (1ULL << 7)
1637#define HCR_VSE (1ULL << 8)
1638#define HCR_FB (1ULL << 9)
1639#define HCR_BSU_MASK (3ULL << 10)
1640#define HCR_DC (1ULL << 12)
1641#define HCR_TWI (1ULL << 13)
1642#define HCR_TWE (1ULL << 14)
1643#define HCR_TID0 (1ULL << 15)
1644#define HCR_TID1 (1ULL << 16)
1645#define HCR_TID2 (1ULL << 17)
1646#define HCR_TID3 (1ULL << 18)
1647#define HCR_TSC (1ULL << 19)
1648#define HCR_TIDCP (1ULL << 20)
1649#define HCR_TACR (1ULL << 21)
1650#define HCR_TSW (1ULL << 22)
1651#define HCR_TPCP (1ULL << 23)
1652#define HCR_TPU (1ULL << 24)
1653#define HCR_TTLB (1ULL << 25)
1654#define HCR_TVM (1ULL << 26)
1655#define HCR_TGE (1ULL << 27)
1656#define HCR_TDZ (1ULL << 28)
1657#define HCR_HCD (1ULL << 29)
1658#define HCR_TRVM (1ULL << 30)
1659#define HCR_RW (1ULL << 31)
1660#define HCR_CD (1ULL << 32)
1661#define HCR_ID (1ULL << 33)
1662#define HCR_E2H (1ULL << 34)
1663#define HCR_TLOR (1ULL << 35)
1664#define HCR_TERR (1ULL << 36)
1665#define HCR_TEA (1ULL << 37)
1666#define HCR_MIOCNCE (1ULL << 38)
1667#define HCR_TME (1ULL << 39)
1668#define HCR_APK (1ULL << 40)
1669#define HCR_API (1ULL << 41)
1670#define HCR_NV (1ULL << 42)
1671#define HCR_NV1 (1ULL << 43)
1672#define HCR_AT (1ULL << 44)
1673#define HCR_NV2 (1ULL << 45)
1674#define HCR_FWB (1ULL << 46)
1675#define HCR_FIEN (1ULL << 47)
1676#define HCR_GPF (1ULL << 48)
1677#define HCR_TID4 (1ULL << 49)
1678#define HCR_TICAB (1ULL << 50)
1679#define HCR_AMVOFFEN (1ULL << 51)
1680#define HCR_TOCU (1ULL << 52)
1681#define HCR_ENSCXT (1ULL << 53)
1682#define HCR_TTLBIS (1ULL << 54)
1683#define HCR_TTLBOS (1ULL << 55)
1684#define HCR_ATA (1ULL << 56)
1685#define HCR_DCT (1ULL << 57)
1686#define HCR_TID5 (1ULL << 58)
1687#define HCR_TWEDEN (1ULL << 59)
1688#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1689
1690#define HCRX_ENAS0 (1ULL << 0)
1691#define HCRX_ENALS (1ULL << 1)
1692#define HCRX_ENASR (1ULL << 2)
1693#define HCRX_FNXS (1ULL << 3)
1694#define HCRX_FGTNXS (1ULL << 4)
1695#define HCRX_SMPME (1ULL << 5)
1696#define HCRX_TALLINT (1ULL << 6)
1697#define HCRX_VINMI (1ULL << 7)
1698#define HCRX_VFNMI (1ULL << 8)
1699#define HCRX_CMOW (1ULL << 9)
1700#define HCRX_MCE2 (1ULL << 10)
1701#define HCRX_MSCEN (1ULL << 11)
1702
1703#define HPFAR_NS (1ULL << 63)
1704
1705#define SCR_NS (1ULL << 0)
1706#define SCR_IRQ (1ULL << 1)
1707#define SCR_FIQ (1ULL << 2)
1708#define SCR_EA (1ULL << 3)
1709#define SCR_FW (1ULL << 4)
1710#define SCR_AW (1ULL << 5)
1711#define SCR_NET (1ULL << 6)
1712#define SCR_SMD (1ULL << 7)
1713#define SCR_HCE (1ULL << 8)
1714#define SCR_SIF (1ULL << 9)
1715#define SCR_RW (1ULL << 10)
1716#define SCR_ST (1ULL << 11)
1717#define SCR_TWI (1ULL << 12)
1718#define SCR_TWE (1ULL << 13)
1719#define SCR_TLOR (1ULL << 14)
1720#define SCR_TERR (1ULL << 15)
1721#define SCR_APK (1ULL << 16)
1722#define SCR_API (1ULL << 17)
1723#define SCR_EEL2 (1ULL << 18)
1724#define SCR_EASE (1ULL << 19)
1725#define SCR_NMEA (1ULL << 20)
1726#define SCR_FIEN (1ULL << 21)
1727#define SCR_ENSCXT (1ULL << 25)
1728#define SCR_ATA (1ULL << 26)
1729#define SCR_FGTEN (1ULL << 27)
1730#define SCR_ECVEN (1ULL << 28)
1731#define SCR_TWEDEN (1ULL << 29)
1732#define SCR_TWEDEL MAKE_64BIT_MASK(30, 4)
1733#define SCR_TME (1ULL << 34)
1734#define SCR_AMVOFFEN (1ULL << 35)
1735#define SCR_ENAS0 (1ULL << 36)
1736#define SCR_ADEN (1ULL << 37)
1737#define SCR_HXEN (1ULL << 38)
1738#define SCR_TRNDR (1ULL << 40)
1739#define SCR_ENTP2 (1ULL << 41)
1740#define SCR_GPF (1ULL << 48)
1741#define SCR_NSE (1ULL << 62)
1742
1743#define HSTR_TTEE (1 << 16)
1744#define HSTR_TJDBX (1 << 17)
1745
1746
1747uint32_t vfp_get_fpscr(CPUARMState *env);
1748void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1749
1750
1751
1752
1753
1754
1755
1756
1757#define FPSR_MASK 0xf800009f
1758#define FPCR_MASK 0x07ff9f00
1759
1760#define FPCR_IOE (1 << 8)
1761#define FPCR_DZE (1 << 9)
1762#define FPCR_OFE (1 << 10)
1763#define FPCR_UFE (1 << 11)
1764#define FPCR_IXE (1 << 12)
1765#define FPCR_IDE (1 << 15)
1766#define FPCR_FZ16 (1 << 19)
1767#define FPCR_RMODE_MASK (3 << 22)
1768#define FPCR_FZ (1 << 24)
1769#define FPCR_DN (1 << 25)
1770#define FPCR_AHP (1 << 26)
1771#define FPCR_QC (1 << 27)
1772#define FPCR_V (1 << 28)
1773#define FPCR_C (1 << 29)
1774#define FPCR_Z (1 << 30)
1775#define FPCR_N (1 << 31)
1776
1777#define FPCR_LTPSIZE_SHIFT 16
1778#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1779#define FPCR_LTPSIZE_LENGTH 3
1780
1781#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1782#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1783
1784static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1785{
1786 return vfp_get_fpscr(env) & FPSR_MASK;
1787}
1788
1789static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1790{
1791 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1792 vfp_set_fpscr(env, new_fpscr);
1793}
1794
1795static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1796{
1797 return vfp_get_fpscr(env) & FPCR_MASK;
1798}
1799
1800static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1801{
1802 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1803 vfp_set_fpscr(env, new_fpscr);
1804}
1805
1806enum arm_cpu_mode {
1807 ARM_CPU_MODE_USR = 0x10,
1808 ARM_CPU_MODE_FIQ = 0x11,
1809 ARM_CPU_MODE_IRQ = 0x12,
1810 ARM_CPU_MODE_SVC = 0x13,
1811 ARM_CPU_MODE_MON = 0x16,
1812 ARM_CPU_MODE_ABT = 0x17,
1813 ARM_CPU_MODE_HYP = 0x1a,
1814 ARM_CPU_MODE_UND = 0x1b,
1815 ARM_CPU_MODE_SYS = 0x1f
1816};
1817
1818
1819#define ARM_VFP_FPSID 0
1820#define ARM_VFP_FPSCR 1
1821#define ARM_VFP_MVFR2 5
1822#define ARM_VFP_MVFR1 6
1823#define ARM_VFP_MVFR0 7
1824#define ARM_VFP_FPEXC 8
1825#define ARM_VFP_FPINST 9
1826#define ARM_VFP_FPINST2 10
1827
1828#define ARM_VFP_FPSCR_NZCVQC 2
1829#define ARM_VFP_VPR 12
1830#define ARM_VFP_P0 13
1831#define ARM_VFP_FPCXT_NS 14
1832#define ARM_VFP_FPCXT_S 15
1833
1834
1835#define QEMU_VFP_FPSCR_NZCV 0xffff
1836
1837
1838#define ARM_IWMMXT_wCID 0
1839#define ARM_IWMMXT_wCon 1
1840#define ARM_IWMMXT_wCSSF 2
1841#define ARM_IWMMXT_wCASF 3
1842#define ARM_IWMMXT_wCGR0 8
1843#define ARM_IWMMXT_wCGR1 9
1844#define ARM_IWMMXT_wCGR2 10
1845#define ARM_IWMMXT_wCGR3 11
1846
1847
1848FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1849FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1850FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1851FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1852FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1853FIELD(V7M_CCR, STKALIGN, 9, 1)
1854FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1855FIELD(V7M_CCR, DC, 16, 1)
1856FIELD(V7M_CCR, IC, 17, 1)
1857FIELD(V7M_CCR, BP, 18, 1)
1858FIELD(V7M_CCR, LOB, 19, 1)
1859FIELD(V7M_CCR, TRD, 20, 1)
1860
1861
1862FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1863FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1864FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1865FIELD(V7M_SCR, SEVONPEND, 4, 1)
1866
1867
1868FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1869FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1870FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1871FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1872FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1873FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1874FIELD(V7M_AIRCR, PRIS, 14, 1)
1875FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1876FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1877
1878
1879FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1880FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1881FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1882FIELD(V7M_CFSR, MSTKERR, 4, 1)
1883FIELD(V7M_CFSR, MLSPERR, 5, 1)
1884FIELD(V7M_CFSR, MMARVALID, 7, 1)
1885
1886
1887FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1888FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1889FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1890FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1891FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1892FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1893FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1894
1895
1896FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1897FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1898FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1899FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1900FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1901FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1902FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1903
1904
1905FIELD(V7M_CFSR, MMFSR, 0, 8)
1906FIELD(V7M_CFSR, BFSR, 8, 8)
1907FIELD(V7M_CFSR, UFSR, 16, 16)
1908
1909
1910FIELD(V7M_HFSR, VECTTBL, 1, 1)
1911FIELD(V7M_HFSR, FORCED, 30, 1)
1912FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1913
1914
1915FIELD(V7M_DFSR, HALTED, 0, 1)
1916FIELD(V7M_DFSR, BKPT, 1, 1)
1917FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1918FIELD(V7M_DFSR, VCATCH, 3, 1)
1919FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1920
1921
1922FIELD(V7M_SFSR, INVEP, 0, 1)
1923FIELD(V7M_SFSR, INVIS, 1, 1)
1924FIELD(V7M_SFSR, INVER, 2, 1)
1925FIELD(V7M_SFSR, AUVIOL, 3, 1)
1926FIELD(V7M_SFSR, INVTRAN, 4, 1)
1927FIELD(V7M_SFSR, LSPERR, 5, 1)
1928FIELD(V7M_SFSR, SFARVALID, 6, 1)
1929FIELD(V7M_SFSR, LSERR, 7, 1)
1930
1931
1932FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1933FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1934FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1935
1936
1937FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1938FIELD(V7M_CLIDR, LOUIS, 21, 3)
1939FIELD(V7M_CLIDR, LOC, 24, 3)
1940FIELD(V7M_CLIDR, LOUU, 27, 3)
1941FIELD(V7M_CLIDR, ICB, 30, 2)
1942
1943FIELD(V7M_CSSELR, IND, 0, 1)
1944FIELD(V7M_CSSELR, LEVEL, 1, 3)
1945
1946
1947
1948
1949FIELD(V7M_CSSELR, INDEX, 0, 4)
1950
1951
1952FIELD(V7M_FPCCR, LSPACT, 0, 1)
1953FIELD(V7M_FPCCR, USER, 1, 1)
1954FIELD(V7M_FPCCR, S, 2, 1)
1955FIELD(V7M_FPCCR, THREAD, 3, 1)
1956FIELD(V7M_FPCCR, HFRDY, 4, 1)
1957FIELD(V7M_FPCCR, MMRDY, 5, 1)
1958FIELD(V7M_FPCCR, BFRDY, 6, 1)
1959FIELD(V7M_FPCCR, SFRDY, 7, 1)
1960FIELD(V7M_FPCCR, MONRDY, 8, 1)
1961FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1962FIELD(V7M_FPCCR, UFRDY, 10, 1)
1963FIELD(V7M_FPCCR, RES0, 11, 15)
1964FIELD(V7M_FPCCR, TS, 26, 1)
1965FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1966FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1967FIELD(V7M_FPCCR, LSPENS, 29, 1)
1968FIELD(V7M_FPCCR, LSPEN, 30, 1)
1969FIELD(V7M_FPCCR, ASPEN, 31, 1)
1970
1971#define R_V7M_FPCCR_BANKED_MASK \
1972 (R_V7M_FPCCR_LSPACT_MASK | \
1973 R_V7M_FPCCR_USER_MASK | \
1974 R_V7M_FPCCR_THREAD_MASK | \
1975 R_V7M_FPCCR_MMRDY_MASK | \
1976 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1977 R_V7M_FPCCR_UFRDY_MASK | \
1978 R_V7M_FPCCR_ASPEN_MASK)
1979
1980
1981FIELD(V7M_VPR, P0, 0, 16)
1982FIELD(V7M_VPR, MASK01, 16, 4)
1983FIELD(V7M_VPR, MASK23, 20, 4)
1984
1985
1986
1987
1988FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1989FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1990FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1991FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1992FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1993FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1994FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1995FIELD(CLIDR_EL1, LOUIS, 21, 3)
1996FIELD(CLIDR_EL1, LOC, 24, 3)
1997FIELD(CLIDR_EL1, LOUU, 27, 3)
1998FIELD(CLIDR_EL1, ICB, 30, 3)
1999
2000
2001FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
2002FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
2003FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
2004
2005
2006FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
2007FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
2008FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
2009
2010FIELD(CTR_EL0, IMINLINE, 0, 4)
2011FIELD(CTR_EL0, L1IP, 14, 2)
2012FIELD(CTR_EL0, DMINLINE, 16, 4)
2013FIELD(CTR_EL0, ERG, 20, 4)
2014FIELD(CTR_EL0, CWG, 24, 4)
2015FIELD(CTR_EL0, IDC, 28, 1)
2016FIELD(CTR_EL0, DIC, 29, 1)
2017FIELD(CTR_EL0, TMINLINE, 32, 6)
2018
2019FIELD(MIDR_EL1, REVISION, 0, 4)
2020FIELD(MIDR_EL1, PARTNUM, 4, 12)
2021FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
2022FIELD(MIDR_EL1, VARIANT, 20, 4)
2023FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
2024
2025FIELD(ID_ISAR0, SWAP, 0, 4)
2026FIELD(ID_ISAR0, BITCOUNT, 4, 4)
2027FIELD(ID_ISAR0, BITFIELD, 8, 4)
2028FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
2029FIELD(ID_ISAR0, COPROC, 16, 4)
2030FIELD(ID_ISAR0, DEBUG, 20, 4)
2031FIELD(ID_ISAR0, DIVIDE, 24, 4)
2032
2033FIELD(ID_ISAR1, ENDIAN, 0, 4)
2034FIELD(ID_ISAR1, EXCEPT, 4, 4)
2035FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
2036FIELD(ID_ISAR1, EXTEND, 12, 4)
2037FIELD(ID_ISAR1, IFTHEN, 16, 4)
2038FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
2039FIELD(ID_ISAR1, INTERWORK, 24, 4)
2040FIELD(ID_ISAR1, JAZELLE, 28, 4)
2041
2042FIELD(ID_ISAR2, LOADSTORE, 0, 4)
2043FIELD(ID_ISAR2, MEMHINT, 4, 4)
2044FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
2045FIELD(ID_ISAR2, MULT, 12, 4)
2046FIELD(ID_ISAR2, MULTS, 16, 4)
2047FIELD(ID_ISAR2, MULTU, 20, 4)
2048FIELD(ID_ISAR2, PSR_AR, 24, 4)
2049FIELD(ID_ISAR2, REVERSAL, 28, 4)
2050
2051FIELD(ID_ISAR3, SATURATE, 0, 4)
2052FIELD(ID_ISAR3, SIMD, 4, 4)
2053FIELD(ID_ISAR3, SVC, 8, 4)
2054FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
2055FIELD(ID_ISAR3, TABBRANCH, 16, 4)
2056FIELD(ID_ISAR3, T32COPY, 20, 4)
2057FIELD(ID_ISAR3, TRUENOP, 24, 4)
2058FIELD(ID_ISAR3, T32EE, 28, 4)
2059
2060FIELD(ID_ISAR4, UNPRIV, 0, 4)
2061FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
2062FIELD(ID_ISAR4, WRITEBACK, 8, 4)
2063FIELD(ID_ISAR4, SMC, 12, 4)
2064FIELD(ID_ISAR4, BARRIER, 16, 4)
2065FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
2066FIELD(ID_ISAR4, PSR_M, 24, 4)
2067FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
2068
2069FIELD(ID_ISAR5, SEVL, 0, 4)
2070FIELD(ID_ISAR5, AES, 4, 4)
2071FIELD(ID_ISAR5, SHA1, 8, 4)
2072FIELD(ID_ISAR5, SHA2, 12, 4)
2073FIELD(ID_ISAR5, CRC32, 16, 4)
2074FIELD(ID_ISAR5, RDM, 24, 4)
2075FIELD(ID_ISAR5, VCMA, 28, 4)
2076
2077FIELD(ID_ISAR6, JSCVT, 0, 4)
2078FIELD(ID_ISAR6, DP, 4, 4)
2079FIELD(ID_ISAR6, FHM, 8, 4)
2080FIELD(ID_ISAR6, SB, 12, 4)
2081FIELD(ID_ISAR6, SPECRES, 16, 4)
2082FIELD(ID_ISAR6, BF16, 20, 4)
2083FIELD(ID_ISAR6, I8MM, 24, 4)
2084
2085FIELD(ID_MMFR0, VMSA, 0, 4)
2086FIELD(ID_MMFR0, PMSA, 4, 4)
2087FIELD(ID_MMFR0, OUTERSHR, 8, 4)
2088FIELD(ID_MMFR0, SHARELVL, 12, 4)
2089FIELD(ID_MMFR0, TCM, 16, 4)
2090FIELD(ID_MMFR0, AUXREG, 20, 4)
2091FIELD(ID_MMFR0, FCSE, 24, 4)
2092FIELD(ID_MMFR0, INNERSHR, 28, 4)
2093
2094FIELD(ID_MMFR1, L1HVDVA, 0, 4)
2095FIELD(ID_MMFR1, L1UNIVA, 4, 4)
2096FIELD(ID_MMFR1, L1HVDSW, 8, 4)
2097FIELD(ID_MMFR1, L1UNISW, 12, 4)
2098FIELD(ID_MMFR1, L1HVD, 16, 4)
2099FIELD(ID_MMFR1, L1UNI, 20, 4)
2100FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
2101FIELD(ID_MMFR1, BPRED, 28, 4)
2102
2103FIELD(ID_MMFR2, L1HVDFG, 0, 4)
2104FIELD(ID_MMFR2, L1HVDBG, 4, 4)
2105FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
2106FIELD(ID_MMFR2, HVDTLB, 12, 4)
2107FIELD(ID_MMFR2, UNITLB, 16, 4)
2108FIELD(ID_MMFR2, MEMBARR, 20, 4)
2109FIELD(ID_MMFR2, WFISTALL, 24, 4)
2110FIELD(ID_MMFR2, HWACCFLG, 28, 4)
2111
2112FIELD(ID_MMFR3, CMAINTVA, 0, 4)
2113FIELD(ID_MMFR3, CMAINTSW, 4, 4)
2114FIELD(ID_MMFR3, BPMAINT, 8, 4)
2115FIELD(ID_MMFR3, MAINTBCST, 12, 4)
2116FIELD(ID_MMFR3, PAN, 16, 4)
2117FIELD(ID_MMFR3, COHWALK, 20, 4)
2118FIELD(ID_MMFR3, CMEMSZ, 24, 4)
2119FIELD(ID_MMFR3, SUPERSEC, 28, 4)
2120
2121FIELD(ID_MMFR4, SPECSEI, 0, 4)
2122FIELD(ID_MMFR4, AC2, 4, 4)
2123FIELD(ID_MMFR4, XNX, 8, 4)
2124FIELD(ID_MMFR4, CNP, 12, 4)
2125FIELD(ID_MMFR4, HPDS, 16, 4)
2126FIELD(ID_MMFR4, LSM, 20, 4)
2127FIELD(ID_MMFR4, CCIDX, 24, 4)
2128FIELD(ID_MMFR4, EVT, 28, 4)
2129
2130FIELD(ID_MMFR5, ETS, 0, 4)
2131FIELD(ID_MMFR5, NTLBPA, 4, 4)
2132
2133FIELD(ID_PFR0, STATE0, 0, 4)
2134FIELD(ID_PFR0, STATE1, 4, 4)
2135FIELD(ID_PFR0, STATE2, 8, 4)
2136FIELD(ID_PFR0, STATE3, 12, 4)
2137FIELD(ID_PFR0, CSV2, 16, 4)
2138FIELD(ID_PFR0, AMU, 20, 4)
2139FIELD(ID_PFR0, DIT, 24, 4)
2140FIELD(ID_PFR0, RAS, 28, 4)
2141
2142FIELD(ID_PFR1, PROGMOD, 0, 4)
2143FIELD(ID_PFR1, SECURITY, 4, 4)
2144FIELD(ID_PFR1, MPROGMOD, 8, 4)
2145FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
2146FIELD(ID_PFR1, GENTIMER, 16, 4)
2147FIELD(ID_PFR1, SEC_FRAC, 20, 4)
2148FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
2149FIELD(ID_PFR1, GIC, 28, 4)
2150
2151FIELD(ID_PFR2, CSV3, 0, 4)
2152FIELD(ID_PFR2, SSBS, 4, 4)
2153FIELD(ID_PFR2, RAS_FRAC, 8, 4)
2154
2155FIELD(ID_AA64ISAR0, AES, 4, 4)
2156FIELD(ID_AA64ISAR0, SHA1, 8, 4)
2157FIELD(ID_AA64ISAR0, SHA2, 12, 4)
2158FIELD(ID_AA64ISAR0, CRC32, 16, 4)
2159FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
2160FIELD(ID_AA64ISAR0, RDM, 28, 4)
2161FIELD(ID_AA64ISAR0, SHA3, 32, 4)
2162FIELD(ID_AA64ISAR0, SM3, 36, 4)
2163FIELD(ID_AA64ISAR0, SM4, 40, 4)
2164FIELD(ID_AA64ISAR0, DP, 44, 4)
2165FIELD(ID_AA64ISAR0, FHM, 48, 4)
2166FIELD(ID_AA64ISAR0, TS, 52, 4)
2167FIELD(ID_AA64ISAR0, TLB, 56, 4)
2168FIELD(ID_AA64ISAR0, RNDR, 60, 4)
2169
2170FIELD(ID_AA64ISAR1, DPB, 0, 4)
2171FIELD(ID_AA64ISAR1, APA, 4, 4)
2172FIELD(ID_AA64ISAR1, API, 8, 4)
2173FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
2174FIELD(ID_AA64ISAR1, FCMA, 16, 4)
2175FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
2176FIELD(ID_AA64ISAR1, GPA, 24, 4)
2177FIELD(ID_AA64ISAR1, GPI, 28, 4)
2178FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
2179FIELD(ID_AA64ISAR1, SB, 36, 4)
2180FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
2181FIELD(ID_AA64ISAR1, BF16, 44, 4)
2182FIELD(ID_AA64ISAR1, DGH, 48, 4)
2183FIELD(ID_AA64ISAR1, I8MM, 52, 4)
2184FIELD(ID_AA64ISAR1, XS, 56, 4)
2185FIELD(ID_AA64ISAR1, LS64, 60, 4)
2186
2187FIELD(ID_AA64ISAR2, WFXT, 0, 4)
2188FIELD(ID_AA64ISAR2, RPRES, 4, 4)
2189FIELD(ID_AA64ISAR2, GPA3, 8, 4)
2190FIELD(ID_AA64ISAR2, APA3, 12, 4)
2191FIELD(ID_AA64ISAR2, MOPS, 16, 4)
2192FIELD(ID_AA64ISAR2, BC, 20, 4)
2193FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
2194
2195FIELD(ID_AA64PFR0, EL0, 0, 4)
2196FIELD(ID_AA64PFR0, EL1, 4, 4)
2197FIELD(ID_AA64PFR0, EL2, 8, 4)
2198FIELD(ID_AA64PFR0, EL3, 12, 4)
2199FIELD(ID_AA64PFR0, FP, 16, 4)
2200FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
2201FIELD(ID_AA64PFR0, GIC, 24, 4)
2202FIELD(ID_AA64PFR0, RAS, 28, 4)
2203FIELD(ID_AA64PFR0, SVE, 32, 4)
2204FIELD(ID_AA64PFR0, SEL2, 36, 4)
2205FIELD(ID_AA64PFR0, MPAM, 40, 4)
2206FIELD(ID_AA64PFR0, AMU, 44, 4)
2207FIELD(ID_AA64PFR0, DIT, 48, 4)
2208FIELD(ID_AA64PFR0, RME, 52, 4)
2209FIELD(ID_AA64PFR0, CSV2, 56, 4)
2210FIELD(ID_AA64PFR0, CSV3, 60, 4)
2211
2212FIELD(ID_AA64PFR1, BT, 0, 4)
2213FIELD(ID_AA64PFR1, SSBS, 4, 4)
2214FIELD(ID_AA64PFR1, MTE, 8, 4)
2215FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2216FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2217FIELD(ID_AA64PFR1, SME, 24, 4)
2218FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
2219FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
2220FIELD(ID_AA64PFR1, NMI, 36, 4)
2221
2222FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2223FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2224FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2225FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2226FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2227FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2228FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2229FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2230FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2231FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2232FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2233FIELD(ID_AA64MMFR0, EXS, 44, 4)
2234FIELD(ID_AA64MMFR0, FGT, 56, 4)
2235FIELD(ID_AA64MMFR0, ECV, 60, 4)
2236
2237FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2238FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2239FIELD(ID_AA64MMFR1, VH, 8, 4)
2240FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2241FIELD(ID_AA64MMFR1, LO, 16, 4)
2242FIELD(ID_AA64MMFR1, PAN, 20, 4)
2243FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2244FIELD(ID_AA64MMFR1, XNX, 28, 4)
2245FIELD(ID_AA64MMFR1, TWED, 32, 4)
2246FIELD(ID_AA64MMFR1, ETS, 36, 4)
2247FIELD(ID_AA64MMFR1, HCX, 40, 4)
2248FIELD(ID_AA64MMFR1, AFP, 44, 4)
2249FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
2250FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
2251FIELD(ID_AA64MMFR1, CMOW, 56, 4)
2252
2253FIELD(ID_AA64MMFR2, CNP, 0, 4)
2254FIELD(ID_AA64MMFR2, UAO, 4, 4)
2255FIELD(ID_AA64MMFR2, LSM, 8, 4)
2256FIELD(ID_AA64MMFR2, IESB, 12, 4)
2257FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2258FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2259FIELD(ID_AA64MMFR2, NV, 24, 4)
2260FIELD(ID_AA64MMFR2, ST, 28, 4)
2261FIELD(ID_AA64MMFR2, AT, 32, 4)
2262FIELD(ID_AA64MMFR2, IDS, 36, 4)
2263FIELD(ID_AA64MMFR2, FWB, 40, 4)
2264FIELD(ID_AA64MMFR2, TTL, 48, 4)
2265FIELD(ID_AA64MMFR2, BBM, 52, 4)
2266FIELD(ID_AA64MMFR2, EVT, 56, 4)
2267FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2268
2269FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2270FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2271FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2272FIELD(ID_AA64DFR0, BRPS, 12, 4)
2273FIELD(ID_AA64DFR0, WRPS, 20, 4)
2274FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2275FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2276FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2277FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2278FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
2279FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2280FIELD(ID_AA64DFR0, BRBE, 52, 4)
2281FIELD(ID_AA64DFR0, HPMN0, 60, 4)
2282
2283FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2284FIELD(ID_AA64ZFR0, AES, 4, 4)
2285FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2286FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2287FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2288FIELD(ID_AA64ZFR0, SM4, 40, 4)
2289FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2290FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2291FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2292
2293FIELD(ID_AA64SMFR0, F32F32, 32, 1)
2294FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2295FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2296FIELD(ID_AA64SMFR0, I8I32, 36, 4)
2297FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2298FIELD(ID_AA64SMFR0, I16I64, 52, 4)
2299FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
2300FIELD(ID_AA64SMFR0, FA64, 63, 1)
2301
2302FIELD(ID_DFR0, COPDBG, 0, 4)
2303FIELD(ID_DFR0, COPSDBG, 4, 4)
2304FIELD(ID_DFR0, MMAPDBG, 8, 4)
2305FIELD(ID_DFR0, COPTRC, 12, 4)
2306FIELD(ID_DFR0, MMAPTRC, 16, 4)
2307FIELD(ID_DFR0, MPROFDBG, 20, 4)
2308FIELD(ID_DFR0, PERFMON, 24, 4)
2309FIELD(ID_DFR0, TRACEFILT, 28, 4)
2310
2311FIELD(ID_DFR1, MTPMU, 0, 4)
2312FIELD(ID_DFR1, HPMN0, 4, 4)
2313
2314FIELD(DBGDIDR, SE_IMP, 12, 1)
2315FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2316FIELD(DBGDIDR, VERSION, 16, 4)
2317FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2318FIELD(DBGDIDR, BRPS, 24, 4)
2319FIELD(DBGDIDR, WRPS, 28, 4)
2320
2321FIELD(DBGDEVID, PCSAMPLE, 0, 4)
2322FIELD(DBGDEVID, WPADDRMASK, 4, 4)
2323FIELD(DBGDEVID, BPADDRMASK, 8, 4)
2324FIELD(DBGDEVID, VECTORCATCH, 12, 4)
2325FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
2326FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
2327FIELD(DBGDEVID, AUXREGS, 24, 4)
2328FIELD(DBGDEVID, CIDMASK, 28, 4)
2329
2330FIELD(MVFR0, SIMDREG, 0, 4)
2331FIELD(MVFR0, FPSP, 4, 4)
2332FIELD(MVFR0, FPDP, 8, 4)
2333FIELD(MVFR0, FPTRAP, 12, 4)
2334FIELD(MVFR0, FPDIVIDE, 16, 4)
2335FIELD(MVFR0, FPSQRT, 20, 4)
2336FIELD(MVFR0, FPSHVEC, 24, 4)
2337FIELD(MVFR0, FPROUND, 28, 4)
2338
2339FIELD(MVFR1, FPFTZ, 0, 4)
2340FIELD(MVFR1, FPDNAN, 4, 4)
2341FIELD(MVFR1, SIMDLS, 8, 4)
2342FIELD(MVFR1, SIMDINT, 12, 4)
2343FIELD(MVFR1, SIMDSP, 16, 4)
2344FIELD(MVFR1, SIMDHP, 20, 4)
2345FIELD(MVFR1, MVE, 8, 4)
2346FIELD(MVFR1, FP16, 20, 4)
2347FIELD(MVFR1, FPHP, 24, 4)
2348FIELD(MVFR1, SIMDFMAC, 28, 4)
2349
2350FIELD(MVFR2, SIMDMISC, 0, 4)
2351FIELD(MVFR2, FPMISC, 4, 4)
2352
2353FIELD(GPCCR, PPS, 0, 3)
2354FIELD(GPCCR, IRGN, 8, 2)
2355FIELD(GPCCR, ORGN, 10, 2)
2356FIELD(GPCCR, SH, 12, 2)
2357FIELD(GPCCR, PGS, 14, 2)
2358FIELD(GPCCR, GPC, 16, 1)
2359FIELD(GPCCR, GPCP, 17, 1)
2360FIELD(GPCCR, L0GPTSZ, 20, 4)
2361
2362FIELD(MFAR, FPA, 12, 40)
2363FIELD(MFAR, NSE, 62, 1)
2364FIELD(MFAR, NS, 63, 1)
2365
2366QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2367
2368
2369
2370
2371
2372enum arm_features {
2373 ARM_FEATURE_AUXCR,
2374 ARM_FEATURE_XSCALE,
2375 ARM_FEATURE_IWMMXT,
2376 ARM_FEATURE_V6,
2377 ARM_FEATURE_V6K,
2378 ARM_FEATURE_V7,
2379 ARM_FEATURE_THUMB2,
2380 ARM_FEATURE_PMSA,
2381 ARM_FEATURE_NEON,
2382 ARM_FEATURE_M,
2383 ARM_FEATURE_OMAPCP,
2384 ARM_FEATURE_THUMB2EE,
2385 ARM_FEATURE_V7MP,
2386 ARM_FEATURE_V7VE,
2387 ARM_FEATURE_V4T,
2388 ARM_FEATURE_V5,
2389 ARM_FEATURE_STRONGARM,
2390 ARM_FEATURE_VAPA,
2391 ARM_FEATURE_GENERIC_TIMER,
2392 ARM_FEATURE_MVFR,
2393 ARM_FEATURE_DUMMY_C15_REGS,
2394 ARM_FEATURE_CACHE_TEST_CLEAN,
2395 ARM_FEATURE_CACHE_DIRTY_REG,
2396 ARM_FEATURE_CACHE_BLOCK_OPS,
2397 ARM_FEATURE_MPIDR,
2398 ARM_FEATURE_LPAE,
2399 ARM_FEATURE_V8,
2400 ARM_FEATURE_AARCH64,
2401 ARM_FEATURE_CBAR,
2402 ARM_FEATURE_CBAR_RO,
2403 ARM_FEATURE_EL2,
2404 ARM_FEATURE_EL3,
2405 ARM_FEATURE_THUMB_DSP,
2406 ARM_FEATURE_PMU,
2407 ARM_FEATURE_VBAR,
2408 ARM_FEATURE_M_SECURITY,
2409 ARM_FEATURE_M_MAIN,
2410 ARM_FEATURE_V8_1M,
2411};
2412
2413static inline int arm_feature(CPUARMState *env, int feature)
2414{
2415 return (env->features & (1ULL << feature)) != 0;
2416}
2417
2418void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2419
2420
2421
2422
2423
2424
2425
2426typedef enum ARMSecuritySpace {
2427 ARMSS_Secure = 0,
2428 ARMSS_NonSecure = 1,
2429 ARMSS_Root = 2,
2430 ARMSS_Realm = 3,
2431} ARMSecuritySpace;
2432
2433
2434static inline bool arm_space_is_secure(ARMSecuritySpace space)
2435{
2436 return space == ARMSS_Secure || space == ARMSS_Root;
2437}
2438
2439
2440static inline ARMSecuritySpace arm_secure_to_space(bool secure)
2441{
2442 return secure ? ARMSS_Secure : ARMSS_NonSecure;
2443}
2444
2445#if !defined(CONFIG_USER_ONLY)
2446
2447
2448
2449
2450
2451
2452
2453
2454ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
2455
2456
2457
2458
2459
2460
2461
2462
2463static inline bool arm_is_secure_below_el3(CPUARMState *env)
2464{
2465 ARMSecuritySpace ss = arm_security_space_below_el3(env);
2466 return ss == ARMSS_Secure;
2467}
2468
2469
2470static inline bool arm_is_el3_or_mon(CPUARMState *env)
2471{
2472 assert(!arm_feature(env, ARM_FEATURE_M));
2473 if (arm_feature(env, ARM_FEATURE_EL3)) {
2474 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2475
2476 return true;
2477 } else if (!is_a64(env) &&
2478 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2479
2480 return true;
2481 }
2482 }
2483 return false;
2484}
2485
2486
2487
2488
2489
2490
2491
2492ARMSecuritySpace arm_security_space(CPUARMState *env);
2493
2494
2495
2496
2497
2498
2499
2500static inline bool arm_is_secure(CPUARMState *env)
2501{
2502 return arm_space_is_secure(arm_security_space(env));
2503}
2504
2505
2506
2507
2508
2509static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
2510{
2511 return arm_feature(env, ARM_FEATURE_EL2)
2512 && (!secure || (env->cp15.scr_el3 & SCR_EEL2));
2513}
2514
2515static inline bool arm_is_el2_enabled(CPUARMState *env)
2516{
2517 return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
2518}
2519
2520#else
2521static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
2522{
2523 return ARMSS_NonSecure;
2524}
2525
2526static inline bool arm_is_secure_below_el3(CPUARMState *env)
2527{
2528 return false;
2529}
2530
2531static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
2532{
2533 return ARMSS_NonSecure;
2534}
2535
2536static inline bool arm_is_secure(CPUARMState *env)
2537{
2538 return false;
2539}
2540
2541static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
2542{
2543 return false;
2544}
2545
2546static inline bool arm_is_el2_enabled(CPUARMState *env)
2547{
2548 return false;
2549}
2550#endif
2551
2552
2553
2554
2555
2556
2557
2558uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure);
2559uint64_t arm_hcr_el2_eff(CPUARMState *env);
2560uint64_t arm_hcrx_el2_eff(CPUARMState *env);
2561
2562
2563static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2564{
2565
2566
2567
2568 assert(el >= 1 && el <= 3);
2569 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2570
2571
2572
2573
2574
2575 if (el == 3) {
2576 return aa64;
2577 }
2578
2579 if (arm_feature(env, ARM_FEATURE_EL3) &&
2580 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
2581 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2582 }
2583
2584 if (el == 2) {
2585 return aa64;
2586 }
2587
2588 if (arm_is_el2_enabled(env)) {
2589 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2590 }
2591
2592 return aa64;
2593}
2594
2595
2596
2597
2598
2599
2600
2601
2602static inline bool access_secure_reg(CPUARMState *env)
2603{
2604 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2605 !arm_el_is_aa64(env, 3) &&
2606 !(env->cp15.scr_el3 & SCR_NS));
2607
2608 return ret;
2609}
2610
2611
2612#define A32_BANKED_REG_GET(_env, _regname, _secure) \
2613 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2614
2615#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2616 do { \
2617 if (_secure) { \
2618 (_env)->cp15._regname##_s = (_val); \
2619 } else { \
2620 (_env)->cp15._regname##_ns = (_val); \
2621 } \
2622 } while (0)
2623
2624
2625
2626
2627
2628
2629#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2630 A32_BANKED_REG_GET((_env), _regname, \
2631 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2632
2633#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2634 A32_BANKED_REG_SET((_env), _regname, \
2635 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2636 (_val))
2637
2638void arm_cpu_list(void);
2639uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2640 uint32_t cur_el, bool secure);
2641
2642
2643static inline int arm_highest_el(CPUARMState *env)
2644{
2645 if (arm_feature(env, ARM_FEATURE_EL3)) {
2646 return 3;
2647 }
2648 if (arm_feature(env, ARM_FEATURE_EL2)) {
2649 return 2;
2650 }
2651 return 1;
2652}
2653
2654
2655static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2656{
2657 return env->v7m.exception != 0;
2658}
2659
2660
2661
2662
2663static inline int arm_current_el(CPUARMState *env)
2664{
2665 if (arm_feature(env, ARM_FEATURE_M)) {
2666 return arm_v7m_is_handler_mode(env) ||
2667 !(env->v7m.control[env->v7m.secure] & 1);
2668 }
2669
2670 if (is_a64(env)) {
2671 return extract32(env->pstate, 2, 2);
2672 }
2673
2674 switch (env->uncached_cpsr & 0x1f) {
2675 case ARM_CPU_MODE_USR:
2676 return 0;
2677 case ARM_CPU_MODE_HYP:
2678 return 2;
2679 case ARM_CPU_MODE_MON:
2680 return 3;
2681 default:
2682 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2683
2684
2685
2686 return 3;
2687 }
2688
2689 return 1;
2690 }
2691}
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707bool write_list_to_cpustate(ARMCPU *cpu);
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2731
2732#define ARM_CPUID_TI915T 0x54029152
2733#define ARM_CPUID_TI925T 0x54029252
2734
2735#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2736#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2737#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2738
2739#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2740
2741#define cpu_list arm_cpu_list
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
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2791
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2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840#define ARM_MMU_IDX_A 0x10
2841#define ARM_MMU_IDX_NOTLB 0x20
2842#define ARM_MMU_IDX_M 0x40
2843
2844
2845#define ARM_MMU_IDX_M_PRIV 0x1
2846#define ARM_MMU_IDX_M_NEGPRI 0x2
2847#define ARM_MMU_IDX_M_S 0x4
2848
2849#define ARM_MMU_IDX_TYPE_MASK \
2850 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2851#define ARM_MMU_IDX_COREIDX_MASK 0xf
2852
2853typedef enum ARMMMUIdx {
2854
2855
2856
2857 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2858 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2859 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2860 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A,
2861 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
2862 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
2863 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
2864 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
2865
2866
2867
2868
2869
2870
2871
2872 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A,
2873 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A,
2874
2875
2876 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
2877 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
2878 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A,
2879 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A,
2880
2881
2882
2883
2884
2885 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2886 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2887 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2888
2889
2890
2891
2892 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2893 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2894 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2895 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2896 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2897 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2898 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2899 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2900} ARMMMUIdx;
2901
2902
2903
2904
2905
2906#define TO_CORE_BIT(NAME) \
2907 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2908
2909typedef enum ARMMMUIdxBit {
2910 TO_CORE_BIT(E10_0),
2911 TO_CORE_BIT(E20_0),
2912 TO_CORE_BIT(E10_1),
2913 TO_CORE_BIT(E10_1_PAN),
2914 TO_CORE_BIT(E2),
2915 TO_CORE_BIT(E20_2),
2916 TO_CORE_BIT(E20_2_PAN),
2917 TO_CORE_BIT(E3),
2918 TO_CORE_BIT(Stage2),
2919 TO_CORE_BIT(Stage2_S),
2920
2921 TO_CORE_BIT(MUser),
2922 TO_CORE_BIT(MPriv),
2923 TO_CORE_BIT(MUserNegPri),
2924 TO_CORE_BIT(MPrivNegPri),
2925 TO_CORE_BIT(MSUser),
2926 TO_CORE_BIT(MSPriv),
2927 TO_CORE_BIT(MSUserNegPri),
2928 TO_CORE_BIT(MSPrivNegPri),
2929} ARMMMUIdxBit;
2930
2931#undef TO_CORE_BIT
2932
2933#define MMU_USER_IDX 0
2934
2935
2936typedef enum ARMASIdx {
2937 ARMASIdx_NS = 0,
2938 ARMASIdx_S = 1,
2939 ARMASIdx_TagNS = 2,
2940 ARMASIdx_TagS = 3,
2941} ARMASIdx;
2942
2943static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space)
2944{
2945
2946 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0);
2947 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure);
2948 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root);
2949 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm);
2950
2951 return ARMMMUIdx_Phys_S + space;
2952}
2953
2954static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx)
2955{
2956 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm);
2957 return idx - ARMMMUIdx_Phys_S;
2958}
2959
2960static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2961{
2962
2963
2964
2965 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2966}
2967
2968static inline bool arm_sctlr_b(CPUARMState *env)
2969{
2970 return
2971
2972
2973
2974
2975#ifndef CONFIG_USER_ONLY
2976 !arm_feature(env, ARM_FEATURE_V7) &&
2977#endif
2978 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2979}
2980
2981uint64_t arm_sctlr(CPUARMState *env, int el);
2982
2983static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
2984 bool sctlr_b)
2985{
2986#ifdef CONFIG_USER_ONLY
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999 if (sctlr_b) {
3000 return true;
3001 }
3002#endif
3003
3004 return env->uncached_cpsr & CPSR_E;
3005}
3006
3007static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3008{
3009 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3010}
3011
3012
3013static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3014{
3015 if (!is_a64(env)) {
3016 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3017 } else {
3018 int cur_el = arm_current_el(env);
3019 uint64_t sctlr = arm_sctlr(env, cur_el);
3020 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3021 }
3022}
3023
3024#include "exec/cpu-all.h"
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3051FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3052FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1)
3053FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3054FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
3055
3056FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
3057
3058FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
3059FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
3060FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
3061FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
3062
3063
3064
3065
3066FIELD(TBFLAG_AM32, CONDEXEC, 24, 8)
3067FIELD(TBFLAG_AM32, THUMB, 23, 1)
3068
3069
3070
3071
3072FIELD(TBFLAG_A32, VECLEN, 0, 3)
3073FIELD(TBFLAG_A32, VECSTRIDE, 3, 2)
3074
3075
3076
3077
3078
3079
3080FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3081FIELD(TBFLAG_A32, VFPEN, 7, 1)
3082FIELD(TBFLAG_A32, SCTLR__B, 8, 1)
3083FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3084
3085
3086
3087
3088
3089FIELD(TBFLAG_A32, NS, 10, 1)
3090
3091
3092
3093
3094FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
3095
3096
3097
3098
3099
3100FIELD(TBFLAG_M32, HANDLER, 0, 1)
3101
3102FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3103
3104FIELD(TBFLAG_M32, LSPACT, 2, 1)
3105
3106FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1)
3107
3108FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1)
3109
3110FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1)
3111
3112FIELD(TBFLAG_M32, SECURE, 6, 1)
3113
3114
3115
3116
3117FIELD(TBFLAG_A64, TBII, 0, 2)
3118FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3119
3120FIELD(TBFLAG_A64, VL, 4, 4)
3121FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3122FIELD(TBFLAG_A64, BT, 9, 1)
3123FIELD(TBFLAG_A64, BTYPE, 10, 2)
3124FIELD(TBFLAG_A64, TBID, 12, 2)
3125FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3126FIELD(TBFLAG_A64, ATA, 15, 1)
3127FIELD(TBFLAG_A64, TCMA, 16, 2)
3128FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3129FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3130FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
3131FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3132FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
3133FIELD(TBFLAG_A64, SVL, 24, 4)
3134
3135FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
3136FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
3137FIELD(TBFLAG_A64, NAA, 30, 1)
3138
3139
3140
3141
3142#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3143 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3144#define DP_TBFLAG_A64(DST, WHICH, VAL) \
3145 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
3146#define DP_TBFLAG_A32(DST, WHICH, VAL) \
3147 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3148#define DP_TBFLAG_M32(DST, WHICH, VAL) \
3149 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3150#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3151 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3152
3153#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3154#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
3155#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3156#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3157#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3168{
3169 return EX_TBFLAG_ANY(env->hflags, MMUIDX);
3170}
3171
3172
3173
3174
3175
3176
3177
3178static inline int sve_vq(CPUARMState *env)
3179{
3180 return EX_TBFLAG_A64(env->hflags, VL) + 1;
3181}
3182
3183
3184
3185
3186
3187
3188
3189static inline int sme_vq(CPUARMState *env)
3190{
3191 return EX_TBFLAG_A64(env->hflags, SVL) + 1;
3192}
3193
3194static inline bool bswap_code(bool sctlr_b)
3195{
3196#ifdef CONFIG_USER_ONLY
3197
3198
3199
3200
3201 return
3202#if TARGET_BIG_ENDIAN
3203 1 ^
3204#endif
3205 sctlr_b;
3206#else
3207
3208
3209
3210 return 0;
3211#endif
3212}
3213
3214#ifdef CONFIG_USER_ONLY
3215static inline bool arm_cpu_bswap_data(CPUARMState *env)
3216{
3217 return
3218#if TARGET_BIG_ENDIAN
3219 1 ^
3220#endif
3221 arm_cpu_data_is_big_endian(env);
3222}
3223#endif
3224
3225void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
3226 uint64_t *cs_base, uint32_t *flags);
3227
3228enum {
3229 QEMU_PSCI_CONDUIT_DISABLED = 0,
3230 QEMU_PSCI_CONDUIT_SMC = 1,
3231 QEMU_PSCI_CONDUIT_HVC = 2,
3232};
3233
3234#ifndef CONFIG_USER_ONLY
3235
3236static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3237{
3238 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3239}
3240
3241
3242
3243
3244
3245static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3246{
3247 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3248}
3249#endif
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3262 void *opaque);
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3274 *opaque);
3275
3276
3277
3278
3279
3280void arm_rebuild_hflags(CPUARMState *env);
3281
3282
3283
3284
3285
3286static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3287{
3288 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3289}
3290
3291
3292
3293
3294
3295static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3296{
3297 return &env->vfp.zregs[regno].d[0];
3298}
3299
3300
3301
3302
3303
3304static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3305{
3306 return &env->vfp.zregs[regno].d[0];
3307}
3308
3309
3310extern const uint64_t pred_esz_masks[5];
3311
3312
3313
3314
3315
3316
3317#define PAGE_BTI PAGE_TARGET_1
3318#define PAGE_MTE PAGE_TARGET_2
3319#define PAGE_TARGET_STICKY PAGE_MTE
3320
3321
3322#define LOG2_TAG_GRANULE 4
3323#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
3324
3325#ifdef CONFIG_USER_ONLY
3326#define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1))
3327#endif
3328
3329#ifdef TARGET_TAGGED_ADDRESSES
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3342{
3343 ARMCPU *cpu = ARM_CPU(cs);
3344 if (cpu->env.tagged_addr_enable) {
3345
3346
3347
3348
3349 x &= sextract64(x, 0, 56);
3350 }
3351 return x;
3352}
3353#endif
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3375{
3376 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3377}
3378
3379static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3380{
3381 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3382}
3383
3384static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
3385{
3386
3387 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
3388}
3389
3390static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3391{
3392 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3393}
3394
3395static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3396{
3397 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3398}
3399
3400static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3401{
3402 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3403}
3404
3405static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3406{
3407 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3408}
3409
3410static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3411{
3412 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3413}
3414
3415static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3416{
3417 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3418}
3419
3420static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3421{
3422 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3423}
3424
3425static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3426{
3427 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3428}
3429
3430static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3431{
3432 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3433}
3434
3435static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3436{
3437 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3438}
3439
3440static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3441{
3442 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3443}
3444
3445static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3446{
3447 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3448}
3449
3450static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3451{
3452 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3453}
3454
3455static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
3456{
3457 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
3458}
3459
3460static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
3461{
3462 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
3463}
3464
3465static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
3466{
3467 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
3468}
3469
3470static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
3471{
3472 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
3473}
3474
3475static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
3476{
3477
3478
3479
3480
3481 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
3482}
3483
3484static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3485{
3486
3487 if (isar_feature_aa32_mprofile(id)) {
3488 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
3489 } else {
3490 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
3491 }
3492}
3493
3494static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
3495{
3496
3497
3498
3499
3500
3501 return isar_feature_aa32_mprofile(id) &&
3502 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
3503}
3504
3505static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
3506{
3507
3508
3509
3510
3511
3512 return isar_feature_aa32_mprofile(id) &&
3513 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
3514}
3515
3516static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3517{
3518
3519
3520
3521
3522 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3523}
3524
3525static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3526{
3527
3528 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3529}
3530
3531static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3532{
3533 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3534}
3535
3536static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3537{
3538
3539 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3540}
3541
3542static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3543{
3544
3545 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3546}
3547
3548static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3549{
3550
3551 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3552}
3553
3554static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3555{
3556
3557 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3558}
3559
3560static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3561{
3562 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3563}
3564
3565
3566
3567
3568
3569
3570static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3571{
3572 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3573}
3574
3575static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3576{
3577 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3578}
3579
3580
3581
3582
3583
3584
3585
3586
3587static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3588{
3589 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3590}
3591
3592static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3593{
3594 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3595}
3596
3597static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3598{
3599 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3600}
3601
3602static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3603{
3604 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3605}
3606
3607static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3608{
3609 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3610}
3611
3612static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
3613{
3614 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
3615}
3616
3617static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3618{
3619 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3620}
3621
3622static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3623{
3624 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3625}
3626
3627static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
3628{
3629
3630 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3631 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3632}
3633
3634static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
3635{
3636
3637 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3638 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3639}
3640
3641static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
3642{
3643
3644 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
3645 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3646}
3647
3648static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3649{
3650 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3651}
3652
3653static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3654{
3655 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3656}
3657
3658static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3659{
3660 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3661}
3662
3663static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
3664{
3665 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
3666}
3667
3668static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
3669{
3670 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
3671}
3672
3673static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
3674{
3675 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
3676}
3677
3678static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
3679{
3680 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
3681}
3682
3683static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
3684{
3685 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
3686}
3687
3688static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
3689{
3690 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
3691}
3692
3693static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
3694{
3695 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
3696}
3697
3698static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
3699{
3700 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0;
3701}
3702
3703
3704
3705
3706static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3707{
3708 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3709}
3710
3711static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3712{
3713 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3714}
3715
3716static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3717{
3718 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3719}
3720
3721static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3722{
3723 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3724}
3725
3726static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3727{
3728 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3729}
3730
3731static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3732{
3733 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3734}
3735
3736static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3737{
3738 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3739}
3740
3741static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3742{
3743 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3744}
3745
3746static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3747{
3748 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3749}
3750
3751static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3752{
3753 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3754}
3755
3756static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3757{
3758 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3759}
3760
3761static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3762{
3763 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3764}
3765
3766static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3767{
3768 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3769}
3770
3771static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3772{
3773 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3774}
3775
3776static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3777{
3778 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3779}
3780
3781static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
3782{
3783 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
3784}
3785
3786static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3787{
3788 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3789}
3790
3791static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3792{
3793 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3794}
3795
3796static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3797{
3798
3799
3800
3801
3802 return (id->id_aa64isar1 &
3803 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3804 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3805 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3806 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3807}
3808
3809static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
3810{
3811
3812
3813
3814
3815 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
3816}
3817
3818static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
3819{
3820 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
3821}
3822
3823static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
3824{
3825 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
3826}
3827
3828static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3829{
3830 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3831}
3832
3833static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3834{
3835 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3836}
3837
3838static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3839{
3840 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3841}
3842
3843static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
3844{
3845 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
3846}
3847
3848static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
3849{
3850 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
3851}
3852
3853static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
3854{
3855 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
3856}
3857
3858static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
3859{
3860
3861 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
3862}
3863
3864static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3865{
3866
3867 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3868}
3869
3870static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3871{
3872 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3873}
3874
3875static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
3876{
3877 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
3878}
3879
3880static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
3881{
3882 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
3883}
3884
3885static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
3886{
3887 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
3888}
3889
3890static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
3891{
3892 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
3893}
3894
3895static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3896{
3897 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3898}
3899
3900static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
3901{
3902 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
3903}
3904
3905static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
3906{
3907 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
3908}
3909
3910static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
3911{
3912 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
3913}
3914
3915static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3916{
3917 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3918}
3919
3920static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
3921{
3922 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
3923}
3924
3925static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
3926{
3927 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
3928}
3929
3930static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
3931{
3932 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
3933}
3934
3935static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
3936{
3937 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
3938}
3939
3940static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
3941{
3942 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
3943}
3944
3945static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
3946{
3947 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
3948}
3949
3950static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
3951{
3952 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
3953}
3954
3955static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
3956{
3957 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
3958}
3959
3960static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
3961{
3962 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
3963}
3964
3965static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
3966{
3967 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
3968}
3969
3970static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
3971{
3972 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
3973}
3974
3975static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
3976{
3977 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
3978}
3979
3980static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
3981{
3982 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
3983}
3984
3985static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
3986{
3987 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
3988}
3989
3990static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
3991{
3992 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
3993}
3994
3995static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
3996{
3997 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
3998 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
3999}
4000
4001static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
4002{
4003 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
4004 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4005}
4006
4007static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
4008{
4009 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
4010 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
4011}
4012
4013static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
4014{
4015 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
4016}
4017
4018static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
4019{
4020 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
4021}
4022
4023static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
4024{
4025 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
4026}
4027
4028static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
4029{
4030 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
4031}
4032
4033static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
4034{
4035 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
4036 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
4037}
4038
4039static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
4040{
4041 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
4042}
4043
4044static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
4045{
4046 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
4047 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
4048}
4049
4050static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
4051{
4052 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
4053}
4054
4055static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
4056{
4057 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
4058}
4059
4060static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
4061{
4062 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
4063}
4064
4065static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
4066{
4067 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
4068 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
4069}
4070
4071static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
4072{
4073 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
4074 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
4075}
4076
4077static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
4078{
4079 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
4080 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
4081}
4082
4083static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
4084{
4085 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
4086}
4087
4088static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
4089{
4090 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
4091}
4092
4093static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
4094{
4095 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
4096}
4097
4098static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
4099{
4100 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
4101}
4102
4103static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
4104{
4105 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
4106}
4107
4108static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
4109{
4110 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
4111}
4112
4113static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
4114{
4115 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
4116}
4117
4118static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
4119{
4120 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
4121}
4122
4123static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
4124{
4125 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
4126 if (key >= 2) {
4127 return true;
4128 }
4129 if (key == 1) {
4130 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
4131 return key >= 2;
4132 }
4133 return false;
4134}
4135
4136static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
4137{
4138 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
4139}
4140
4141static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
4142{
4143 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
4144}
4145
4146static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
4147{
4148 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
4149}
4150
4151static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
4152{
4153 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
4154}
4155
4156static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
4157{
4158 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
4159}
4160
4161static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
4162{
4163 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
4164}
4165
4166static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
4167{
4168 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
4169}
4170
4171static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
4172{
4173 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
4174}
4175
4176static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
4177{
4178 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
4179}
4180
4181static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
4182{
4183 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
4184}
4185
4186static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
4187{
4188 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
4189}
4190
4191static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
4192{
4193 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
4194}
4195
4196static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
4197{
4198 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
4199}
4200
4201static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
4202{
4203 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
4204}
4205
4206static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
4207{
4208 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
4209}
4210
4211static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
4212{
4213 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
4214}
4215
4216
4217
4218
4219static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
4220{
4221 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
4222}
4223
4224static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
4225{
4226 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
4227}
4228
4229static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id)
4230{
4231 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id);
4232}
4233
4234static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id)
4235{
4236 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id);
4237}
4238
4239static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id)
4240{
4241 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id);
4242}
4243
4244static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
4245{
4246 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
4247}
4248
4249static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
4250{
4251 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
4252}
4253
4254static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
4255{
4256 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
4257}
4258
4259static inline bool isar_feature_any_ras(const ARMISARegisters *id)
4260{
4261 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
4262}
4263
4264static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
4265{
4266 return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
4267}
4268
4269static inline bool isar_feature_any_evt(const ARMISARegisters *id)
4270{
4271 return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
4272}
4273
4274
4275
4276
4277#define cpu_isar_feature(name, cpu) \
4278 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
4279
4280#endif
4281