LXR qemu/target/hexagon/macros.h

   1/*
   2 *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3 *
   4 *  This program is free software; you can redistribute it and/or modify
   5 *  it under the terms of the GNU General Public License as published by
   6 *  the Free Software Foundation; either version 2 of the License, or
   7 *  (at your option) any later version.
   8 *
   9 *  This program is distributed in the hope that it will be useful,
  10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 *  GNU General Public License for more details.
  13 *
  14 *  You should have received a copy of the GNU General Public License
  15 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef HEXAGON_MACROS_H
  19#define HEXAGON_MACROS_H
  20
  21#include "cpu.h"
  22#include "hex_regs.h"
  23#include "reg_fields.h"
  24
  25#define PCALIGN 4
  26#define PCALIGN_MASK (PCALIGN - 1)
  27
  28#define GET_FIELD(FIELD, REGIN) \
  29    fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
  30                   reg_field_info[FIELD].offset)
  31
  32#ifdef QEMU_GENERATE
  33#define GET_USR_FIELD(FIELD, DST) \
  34    tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \
  35                       reg_field_info[FIELD].offset, \
  36                       reg_field_info[FIELD].width)
  37
  38#define TYPE_INT(X)          __builtin_types_compatible_p(typeof(X), int)
  39#define TYPE_TCGV(X)         __builtin_types_compatible_p(typeof(X), TCGv)
  40#define TYPE_TCGV_I64(X)     __builtin_types_compatible_p(typeof(X), TCGv_i64)
  41#else
  42#define GET_USR_FIELD(FIELD) \
  43    fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
  44                   reg_field_info[FIELD].offset)
  45
  46#define SET_USR_FIELD(FIELD, VAL) \
  47    do { \
  48        if (pkt_need_commit) { \
  49            fINSERT_BITS(env->new_value_usr, \
  50                        reg_field_info[FIELD].width, \
  51                        reg_field_info[FIELD].offset, (VAL)); \
  52        } else { \
  53            fINSERT_BITS(env->gpr[HEX_REG_USR], \
  54                        reg_field_info[FIELD].width, \
  55                        reg_field_info[FIELD].offset, (VAL)); \
  56        } \
  57    } while (0)
  58#endif
  59
  60#ifdef QEMU_GENERATE
  61/*
  62 * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
  63 *
  64 * Slot 1 store with slot 0 load
  65 * A slot 1 store operation with a slot 0 load operation can appear in a packet.
  66 * The packet attribute :mem_noshuf inhibits the instruction reordering that
  67 * would otherwise be done by the assembler. For example:
  68 *     {
  69 *         memw(R5) = R2 // slot 1 store
  70 *         R3 = memh(R6) // slot 0 load
  71 *     }:mem_noshuf
  72 * Unlike most packetized operations, these memory operations are not executed
  73 * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
  74 * effectively executes first, followed by the load instruction in Slot 0. If
  75 * the addresses of the two operations are overlapping, the load will receive
  76 * the newly stored data. This feature is supported in processor versions
  77 * V65 or greater.
  78 *
  79 *
  80 * For qemu, we look for a load in slot 0 when there is  a store in slot 1
  81 * in the same packet.  When we see this, we call a helper that probes the
  82 * load to make sure it doesn't fault.  Then, we process the store ahead of
  83 * the actual load.
  84
  85 */
  86#define CHECK_NOSHUF(VA, SIZE) \
  87    do { \
  88        if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
  89            probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
  90            process_store(ctx, 1); \
  91        } \
  92    } while (0)
  93
  94#define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \
  95    do { \
  96        TCGLabel *label = gen_new_label(); \
  97        tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \
  98        GET_EA; \
  99        if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
 100            probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
 101        } \
 102        gen_set_label(label); \
 103        if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
 104            process_store(ctx, 1); \
 105        } \
 106    } while (0)
 107
 108#define MEM_LOAD1s(DST, VA) \
 109    do { \
 110        CHECK_NOSHUF(VA, 1); \
 111        tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \
 112    } while (0)
 113#define MEM_LOAD1u(DST, VA) \
 114    do { \
 115        CHECK_NOSHUF(VA, 1); \
 116        tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \
 117    } while (0)
 118#define MEM_LOAD2s(DST, VA) \
 119    do { \
 120        CHECK_NOSHUF(VA, 2); \
 121        tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \
 122    } while (0)
 123#define MEM_LOAD2u(DST, VA) \
 124    do { \
 125        CHECK_NOSHUF(VA, 2); \
 126        tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \
 127    } while (0)
 128#define MEM_LOAD4s(DST, VA) \
 129    do { \
 130        CHECK_NOSHUF(VA, 4); \
 131        tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \
 132    } while (0)
 133#define MEM_LOAD4u(DST, VA) \
 134    do { \
 135        CHECK_NOSHUF(VA, 4); \
 136        tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \
 137    } while (0)
 138#define MEM_LOAD8u(DST, VA) \
 139    do { \
 140        CHECK_NOSHUF(VA, 8); \
 141        tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \
 142    } while (0)
 143
 144#define MEM_STORE1_FUNC(X) \
 145    __builtin_choose_expr(TYPE_INT(X), \
 146        gen_store1i, \
 147        __builtin_choose_expr(TYPE_TCGV(X), \
 148            gen_store1, (void)0))
 149#define MEM_STORE1(VA, DATA, SLOT) \
 150    MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 151
 152#define MEM_STORE2_FUNC(X) \
 153    __builtin_choose_expr(TYPE_INT(X), \
 154        gen_store2i, \
 155        __builtin_choose_expr(TYPE_TCGV(X), \
 156            gen_store2, (void)0))
 157#define MEM_STORE2(VA, DATA, SLOT) \
 158    MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 159
 160#define MEM_STORE4_FUNC(X) \
 161    __builtin_choose_expr(TYPE_INT(X), \
 162        gen_store4i, \
 163        __builtin_choose_expr(TYPE_TCGV(X), \
 164            gen_store4, (void)0))
 165#define MEM_STORE4(VA, DATA, SLOT) \
 166    MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 167
 168#define MEM_STORE8_FUNC(X) \
 169    __builtin_choose_expr(TYPE_INT(X), \
 170        gen_store8i, \
 171        __builtin_choose_expr(TYPE_TCGV_I64(X), \
 172            gen_store8, (void)0))
 173#define MEM_STORE8(VA, DATA, SLOT) \
 174    MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 175#else
 176#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
 177#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
 178#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
 179#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, pkt_has_store_s1, slot, VA))
 180#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
 181#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, pkt_has_store_s1, slot, VA))
 182#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
 183#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, pkt_has_store_s1, slot, VA))
 184
 185#define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
 186#define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
 187#define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
 188#define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
 189#endif
 190
 191#ifdef QEMU_GENERATE
 192static inline void gen_cancel(uint32_t slot)
 193{
 194    tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);
 195}
 196
 197#define CANCEL gen_cancel(slot);
 198#else
 199#define CANCEL do { } while (0)
 200#endif
 201
 202#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
 203
 204#define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
 205
 206#define fMAX(A, B) (((A) > (B)) ? (A) : (B))
 207
 208#define fMIN(A, B) (((A) < (B)) ? (A) : (B))
 209
 210#define fABS(A) (((A) < 0) ? (-(A)) : (A))
 211#define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \
 212    REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
 213#define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \
 214    ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
 215#define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
 216    (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
 217#define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \
 218    (((HIBIT) - (LOWBIT) + 1) ? \
 219        extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
 220        0LL)
 221#define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \
 222    do { \
 223        int width = ((HIBIT) - (LOWBIT) + 1); \
 224        INREG = (width >= 0 ? \
 225            deposit64((INREG), (LOWBIT), width, (INVAL)) : \
 226            INREG); \
 227    } while (0)
 228
 229#define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
 230
 231#ifdef QEMU_GENERATE
 232#define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1)
 233#else
 234#define fLSBOLD(VAL)  ((VAL) & 1)
 235#endif
 236
 237#ifdef QEMU_GENERATE
 238#define fLSBNEW(PVAL)   tcg_gen_andi_tl(LSB, (PVAL), 1)
 239#else
 240#define fLSBNEW(PVAL)   ((PVAL) & 1)
 241#endif
 242
 243#ifdef QEMU_GENERATE
 244#define fLSBOLDNOT(VAL) \
 245    do { \
 246        tcg_gen_andi_tl(LSB, (VAL), 1); \
 247        tcg_gen_xori_tl(LSB, LSB, 1); \
 248    } while (0)
 249#define fLSBNEWNOT(PNUM) \
 250    do { \
 251        tcg_gen_andi_tl(LSB, (PNUM), 1); \
 252        tcg_gen_xori_tl(LSB, LSB, 1); \
 253    } while (0)
 254#else
 255#define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
 256#define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
 257#define fLSBNEW0NOT (!fLSBNEW0)
 258#define fLSBNEW1NOT (!fLSBNEW1)
 259#endif
 260
 261#define fNEWREG(VAL) ((int32_t)(VAL))
 262
 263#define fNEWREG_ST(VAL) (VAL)
 264
 265#define fVSATUVALN(N, VAL) \
 266    ({ \
 267        (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \
 268    })
 269#define fSATUVALN(N, VAL) \
 270    ({ \
 271        fSET_OVERFLOW(); \
 272        ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
 273    })
 274#define fSATVALN(N, VAL) \
 275    ({ \
 276        fSET_OVERFLOW(); \
 277        ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 278    })
 279#define fVSATVALN(N, VAL) \
 280    ({ \
 281        ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 282    })
 283#define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
 284#define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
 285#define fSATN(N, VAL) \
 286    ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
 287#define fVSATN(N, VAL) \
 288    ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL))
 289#define fADDSAT64(DST, A, B) \
 290    do { \
 291        uint64_t __a = fCAST8u(A); \
 292        uint64_t __b = fCAST8u(B); \
 293        uint64_t __sum = __a + __b; \
 294        uint64_t __xor = __a ^ __b; \
 295        const uint64_t __mask = 0x8000000000000000ULL; \
 296        if (__xor & __mask) { \
 297            DST = __sum; \
 298        } \
 299        else if ((__a ^ __sum) & __mask) { \
 300            if (__sum & __mask) { \
 301                DST = 0x7FFFFFFFFFFFFFFFLL; \
 302                fSET_OVERFLOW(); \
 303            } else { \
 304                DST = 0x8000000000000000LL; \
 305                fSET_OVERFLOW(); \
 306            } \
 307        } else { \
 308            DST = __sum; \
 309        } \
 310    } while (0)
 311#define fVSATUN(N, VAL) \
 312    ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL))
 313#define fSATUN(N, VAL) \
 314    ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
 315#define fSATH(VAL) (fSATN(16, VAL))
 316#define fSATUH(VAL) (fSATUN(16, VAL))
 317#define fVSATH(VAL) (fVSATN(16, VAL))
 318#define fVSATUH(VAL) (fVSATUN(16, VAL))
 319#define fSATUB(VAL) (fSATUN(8, VAL))
 320#define fSATB(VAL) (fSATN(8, VAL))
 321#define fVSATUB(VAL) (fVSATUN(8, VAL))
 322#define fVSATB(VAL) (fVSATN(8, VAL))
 323#define fIMMEXT(IMM) (IMM = IMM)
 324#define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
 325
 326#define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK)
 327
 328#ifdef QEMU_GENERATE
 329static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 330{
 331    /*
 332     * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual
 333     *
 334     *  The "I" value from a modifier register is divided into two pieces
 335     *      LSB         bits 23:17
 336     *      MSB         bits 31:28
 337     * The value is signed
 338     *
 339     * At the end we shift the result according to the shift argument
 340     */
 341    TCGv msb = tcg_temp_new();
 342    TCGv lsb = tcg_temp_new();
 343
 344    tcg_gen_extract_tl(lsb, val, 17, 7);
 345    tcg_gen_sari_tl(msb, val, 21);
 346    tcg_gen_deposit_tl(result, msb, lsb, 0, 7);
 347
 348    tcg_gen_shli_tl(result, result, shift);
 349    return result;
 350}
 351#endif
 352
 353#define fREAD_LR() (env->gpr[HEX_REG_LR])
 354
 355#define fREAD_SP() (env->gpr[HEX_REG_SP])
 356#define fREAD_LC0 (env->gpr[HEX_REG_LC0])
 357#define fREAD_LC1 (env->gpr[HEX_REG_LC1])
 358#define fREAD_SA0 (env->gpr[HEX_REG_SA0])
 359#define fREAD_SA1 (env->gpr[HEX_REG_SA1])
 360#define fREAD_FP() (env->gpr[HEX_REG_FP])
 361#ifdef FIXME
 362/* Figure out how to get insn->extension_valid to helper */
 363#define fREAD_GP() \
 364    (insn->extension_valid ? 0 : env->gpr[HEX_REG_GP])
 365#else
 366#define fREAD_GP() (env->gpr[HEX_REG_GP])
 367#endif
 368#define fREAD_PC() (PC)
 369
 370#define fREAD_P0() (env->pred[0])
 371
 372#define fCHECK_PCALIGN(A)
 373
 374#define fWRITE_NPC(A) write_new_pc(env, pkt_has_multi_cof != 0, A)
 375
 376#define fBRANCH(LOC, TYPE)          fWRITE_NPC(LOC)
 377#define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
 378#define fHINTJR(TARGET) { /* Not modelled in qemu */}
 379
 380#define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 381#define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 382#define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
 383#define fPART1(WORK) if (part1) { WORK; return; }
 384#define fCAST4u(A) ((uint32_t)(A))
 385#define fCAST4s(A) ((int32_t)(A))
 386#define fCAST8u(A) ((uint64_t)(A))
 387#define fCAST8s(A) ((int64_t)(A))
 388#define fCAST2_2s(A) ((int16_t)(A))
 389#define fCAST2_2u(A) ((uint16_t)(A))
 390#define fCAST4_4s(A) ((int32_t)(A))
 391#define fCAST4_4u(A) ((uint32_t)(A))
 392#define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
 393#define fCAST4_8u(A) ((uint64_t)((uint32_t)(A)))
 394#define fCAST8_8s(A) ((int64_t)(A))
 395#define fCAST8_8u(A) ((uint64_t)(A))
 396#define fCAST2_8s(A) ((int64_t)((int16_t)(A)))
 397#define fCAST2_8u(A) ((uint64_t)((uint16_t)(A)))
 398#define fZE8_16(A) ((int16_t)((uint8_t)(A)))
 399#define fSE8_16(A) ((int16_t)((int8_t)(A)))
 400#define fSE16_32(A) ((int32_t)((int16_t)(A)))
 401#define fZE16_32(A) ((uint32_t)((uint16_t)(A)))
 402#define fSE32_64(A) ((int64_t)((int32_t)(A)))
 403#define fZE32_64(A) ((uint64_t)((uint32_t)(A)))
 404#define fSE8_32(A) ((int32_t)((int8_t)(A)))
 405#define fZE8_32(A) ((int32_t)((uint8_t)(A)))
 406#define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B))
 407#define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B))
 408#define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B))
 409#define fMPY8SS(A, B) (int)((short)(A) * (short)(B))
 410#define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B))
 411#define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B))
 412#define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B))
 413#define fMPY16US(A, B) fMPY16SU(B, A)
 414#define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B))
 415#define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B))
 416#define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B))
 417#define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B))
 418#define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
 419#define fROUND(A) (A + 0x8000)
 420#define fCLIP(DST, SRC, U) \
 421    do { \
 422        int32_t maxv = (1 << U) - 1; \
 423        int32_t minv = -(1 << U); \
 424        DST = fMIN(maxv, fMAX(SRC, minv)); \
 425    } while (0)
 426#define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A)))
 427#define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
 428#define fCRNDN(A, N) (conv_round(A, N))
 429#define fADD128(A, B) (int128_add(A, B))
 430#define fSUB128(A, B) (int128_sub(A, B))
 431#define fSHIFTR128(A, B) (int128_rshift(A, B))
 432#define fSHIFTL128(A, B) (int128_lshift(A, B))
 433#define fAND128(A, B) (int128_and(A, B))
 434#define fCAST8S_16S(A) (int128_exts64(A))
 435#define fCAST16S_8S(A) (int128_getlo(A))
 436
 437#ifdef QEMU_GENERATE
 438#define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM)
 439#define fEA_RRs(REG, REG2, SCALE) \
 440    do { \
 441        TCGv tmp = tcg_temp_new(); \
 442        tcg_gen_shli_tl(tmp, REG2, SCALE); \
 443        tcg_gen_add_tl(EA, REG, tmp); \
 444    } while (0)
 445#define fEA_IRs(IMM, REG, SCALE) \
 446    do { \
 447        tcg_gen_shli_tl(EA, REG, SCALE); \
 448        tcg_gen_addi_tl(EA, EA, IMM); \
 449    } while (0)
 450#else
 451#define fEA_RI(REG, IMM) \
 452    do { \
 453        EA = REG + IMM; \
 454    } while (0)
 455#define fEA_RRs(REG, REG2, SCALE) \
 456    do { \
 457        EA = REG + (REG2 << SCALE); \
 458    } while (0)
 459#define fEA_IRs(IMM, REG, SCALE) \
 460    do { \
 461        EA = IMM + (REG << SCALE); \
 462    } while (0)
 463#endif
 464
 465#ifdef QEMU_GENERATE
 466#define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM)
 467#define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
 468#define fEA_BREVR(REG)      gen_helper_fbrev(EA, REG)
 469#define fPM_I(REG, IMM)     tcg_gen_addi_tl(REG, REG, IMM)
 470#define fPM_M(REG, MVAL)    tcg_gen_add_tl(REG, REG, MVAL)
 471#define fPM_CIRI(REG, IMM, MVAL) \
 472    do { \
 473        TCGv tcgv_siV = tcg_constant_tl(siV); \
 474        gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \
 475                            hex_gpr[HEX_REG_CS0 + MuN]); \
 476    } while (0)
 477#else
 478#define fEA_IMM(IMM)        do { EA = (IMM); } while (0)
 479#define fEA_REG(REG)        do { EA = (REG); } while (0)
 480#define fEA_GPI(IMM)        do { EA = (fREAD_GP() + (IMM)); } while (0)
 481#define fPM_I(REG, IMM)     do { REG = REG + (IMM); } while (0)
 482#define fPM_M(REG, MVAL)    do { REG = REG + (MVAL); } while (0)
 483#endif
 484#define fSCALE(N, A) (((int64_t)(A)) << N)
 485#define fVSATW(A) fVSATN(32, ((long long)A))
 486#define fSATW(A) fSATN(32, ((long long)A))
 487#define fVSAT(A) fVSATN(32, (A))
 488#define fSAT(A) fSATN(32, (A))
 489#define fSAT_ORIG_SHL(A, ORIG_REG) \
 490    ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
 491        ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
 492        : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
 493                                            : fSAT(A)))
 494#define fPASS(A) A
 495#define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \
 496    (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 497                   : (fCAST##REGSTYPE(SRC) << (SHAMT)))
 498#define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
 499    fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s)
 500#define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
 501    fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u)
 502#define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
 503    (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 504                   : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
 505#define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
 506    (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
 507                   : (fCAST##REGSTYPE(SRC) >> (SHAMT)))
 508#define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
 509    fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s)
 510#define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
 511    fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
 512#define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
 513    (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
 514                        << ((-(SHAMT)) - 1)) << 1, (SRC)) \
 515                   : (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
 516#define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
 517#define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
 518    (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
 519#define fROTL(SRC, SHAMT, REGSTYPE) \
 520    (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
 521                              ((fCAST##REGSTYPE##u(SRC) >> \
 522                                 ((sizeof(SRC) * 8) - (SHAMT))))))
 523#define fROTR(SRC, SHAMT, REGSTYPE) \
 524    (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
 525                              ((fCAST##REGSTYPE##u(SRC) << \
 526                                 ((sizeof(SRC) * 8) - (SHAMT))))))
 527#define fASHIFTL(SRC, SHAMT, REGSTYPE) \
 528    (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))
 529
 530#ifdef QEMU_GENERATE
 531#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
 532#else
 533#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
 534    DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
 535#endif
 536
 537#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
 538
 539#define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY])
 540#define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
 541#define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
 542
 543#ifdef CONFIG_USER_ONLY
 544#define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */
 545#else
 546/* System mode not implemented yet */
 547#define fFRAMECHECK(ADDR, EA)  g_assert_not_reached();
 548#endif
 549
 550#ifdef QEMU_GENERATE
 551#define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \
 552    gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
 553#endif
 554
 555#ifdef QEMU_GENERATE
 556#define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
 557#else
 558#define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
 559#endif
 560
 561#ifdef QEMU_GENERATE
 562#define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
 563    gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
 564#endif
 565
 566#ifdef QEMU_GENERATE
 567#define GETBYTE_FUNC(X) \
 568    __builtin_choose_expr(TYPE_TCGV(X), \
 569        gen_get_byte, \
 570        __builtin_choose_expr(TYPE_TCGV_I64(X), \
 571            gen_get_byte_i64, (void)0))
 572#define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true)
 573#define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false)
 574#else
 575#define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
 576#define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
 577#endif
 578
 579#define fSETBYTE(N, DST, VAL) \
 580    do { \
 581        DST = (DST & ~(0x0ffLL << ((N) * 8))) | \
 582        (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \
 583    } while (0)
 584
 585#ifdef QEMU_GENERATE
 586#define fGETHALF(N, SRC)  gen_get_half(HALF, N, SRC, true)
 587#define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false)
 588#else
 589#define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
 590#define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
 591#endif
 592#define fSETHALF(N, DST, VAL) \
 593    do { \
 594        DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \
 595        (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \
 596    } while (0)
 597#define fSETHALFw fSETHALF
 598#define fSETHALFd fSETHALF
 599
 600#define fGETWORD(N, SRC) \
 601    ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 602#define fGETUWORD(N, SRC) \
 603    ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 604
 605#define fSETWORD(N, DST, VAL) \
 606    do { \
 607        DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \
 608              (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \
 609    } while (0)
 610
 611#define fSETBIT(N, DST, VAL) \
 612    do { \
 613        DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \
 614    } while (0)
 615
 616#define fGETBIT(N, SRC) (((SRC) >> N) & 1)
 617#define fSETBITS(HI, LO, DST, VAL) \
 618    do { \
 619        int j; \
 620        for (j = LO; j <= HI; j++) { \
 621            fSETBIT(j, DST, VAL); \
 622        } \
 623    } while (0)
 624#define fCOUNTONES_2(VAL) ctpop16(VAL)
 625#define fCOUNTONES_4(VAL) ctpop32(VAL)
 626#define fCOUNTONES_8(VAL) ctpop64(VAL)
 627#define fBREV_8(VAL) revbit64(VAL)
 628#define fBREV_4(VAL) revbit32(VAL)
 629#define fCL1_8(VAL) clo64(VAL)
 630#define fCL1_4(VAL) clo32(VAL)
 631#define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16)
 632#define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
 633#define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
 634#define fHIDE(A) A
 635#define fCONSTLL(A) A##LL
 636#define fECHO(A) (A)
 637
 638#define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)
 639#define fPAUSE(IMM)
 640
 641#define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \
 642    ((VAL) << reg_field_info[FIELD].offset)
 643#define fGET_REG_FIELD_MASK(FIELD) \
 644    (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
 645#define fREAD_REG_FIELD(REG, FIELD) \
 646    fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
 647                   reg_field_info[FIELD].width, \
 648                   reg_field_info[FIELD].offset)
 649
 650#ifdef QEMU_GENERATE
 651#define fDCZEROA(REG) \
 652    do { \
 653        ctx->dczero_addr = tcg_temp_new(); \
 654        tcg_gen_mov_tl(ctx->dczero_addr, (REG)); \
 655    } while (0)
 656#endif
 657
 658#define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
 659                                STRBITNUM) /* Nothing */
 660
 661
 662#endif
 663