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20#ifndef I386_CPU_H
21#define I386_CPU_H
22
23#include "sysemu/tcg.h"
24#include "cpu-qom.h"
25#include "kvm/hyperv-proto.h"
26#include "exec/cpu-defs.h"
27#include "qapi/qapi-types-common.h"
28#include "qemu/cpu-float.h"
29#include "qemu/timer.h"
30
31#define XEN_NR_VIRQS 24
32
33
34#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
35
36#define KVM_HAVE_MCE_INJECTION 1
37
38
39
40#define TARGET_HAS_PRECISE_SMC
41
42#ifdef TARGET_X86_64
43#define I386_ELF_MACHINE EM_X86_64
44#define ELF_MACHINE_UNAME "x86_64"
45#else
46#define I386_ELF_MACHINE EM_386
47#define ELF_MACHINE_UNAME "i686"
48#endif
49
50enum {
51 R_EAX = 0,
52 R_ECX = 1,
53 R_EDX = 2,
54 R_EBX = 3,
55 R_ESP = 4,
56 R_EBP = 5,
57 R_ESI = 6,
58 R_EDI = 7,
59 R_R8 = 8,
60 R_R9 = 9,
61 R_R10 = 10,
62 R_R11 = 11,
63 R_R12 = 12,
64 R_R13 = 13,
65 R_R14 = 14,
66 R_R15 = 15,
67
68 R_AL = 0,
69 R_CL = 1,
70 R_DL = 2,
71 R_BL = 3,
72 R_AH = 4,
73 R_CH = 5,
74 R_DH = 6,
75 R_BH = 7,
76};
77
78typedef enum X86Seg {
79 R_ES = 0,
80 R_CS = 1,
81 R_SS = 2,
82 R_DS = 3,
83 R_FS = 4,
84 R_GS = 5,
85 R_LDTR = 6,
86 R_TR = 7,
87} X86Seg;
88
89
90#define DESC_G_SHIFT 23
91#define DESC_G_MASK (1 << DESC_G_SHIFT)
92#define DESC_B_SHIFT 22
93#define DESC_B_MASK (1 << DESC_B_SHIFT)
94#define DESC_L_SHIFT 21
95#define DESC_L_MASK (1 << DESC_L_SHIFT)
96#define DESC_AVL_SHIFT 20
97#define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
98#define DESC_P_SHIFT 15
99#define DESC_P_MASK (1 << DESC_P_SHIFT)
100#define DESC_DPL_SHIFT 13
101#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
102#define DESC_S_SHIFT 12
103#define DESC_S_MASK (1 << DESC_S_SHIFT)
104#define DESC_TYPE_SHIFT 8
105#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
106#define DESC_A_MASK (1 << 8)
107
108#define DESC_CS_MASK (1 << 11)
109#define DESC_C_MASK (1 << 10)
110#define DESC_R_MASK (1 << 9)
111
112#define DESC_E_MASK (1 << 10)
113#define DESC_W_MASK (1 << 9)
114
115#define DESC_TSS_BUSY_MASK (1 << 9)
116
117
118#define CC_C 0x0001
119#define CC_P 0x0004
120#define CC_A 0x0010
121#define CC_Z 0x0040
122#define CC_S 0x0080
123#define CC_O 0x0800
124
125#define TF_SHIFT 8
126#define IOPL_SHIFT 12
127#define VM_SHIFT 17
128
129#define TF_MASK 0x00000100
130#define IF_MASK 0x00000200
131#define DF_MASK 0x00000400
132#define IOPL_MASK 0x00003000
133#define NT_MASK 0x00004000
134#define RF_MASK 0x00010000
135#define VM_MASK 0x00020000
136#define AC_MASK 0x00040000
137#define VIF_MASK 0x00080000
138#define VIP_MASK 0x00100000
139#define ID_MASK 0x00200000
140
141
142
143
144
145
146#define HF_CPL_SHIFT 0
147
148#define HF_INHIBIT_IRQ_SHIFT 3
149
150#define HF_CS32_SHIFT 4
151#define HF_SS32_SHIFT 5
152
153#define HF_ADDSEG_SHIFT 6
154
155#define HF_PE_SHIFT 7
156#define HF_TF_SHIFT 8
157#define HF_MP_SHIFT 9
158#define HF_EM_SHIFT 10
159#define HF_TS_SHIFT 11
160#define HF_IOPL_SHIFT 12
161#define HF_LMA_SHIFT 14
162#define HF_CS64_SHIFT 15
163#define HF_RF_SHIFT 16
164#define HF_VM_SHIFT 17
165#define HF_AC_SHIFT 18
166#define HF_SMM_SHIFT 19
167#define HF_SVME_SHIFT 20
168#define HF_GUEST_SHIFT 21
169#define HF_OSFXSR_SHIFT 22
170#define HF_SMAP_SHIFT 23
171#define HF_IOBPT_SHIFT 24
172#define HF_MPX_EN_SHIFT 25
173#define HF_MPX_IU_SHIFT 26
174#define HF_UMIP_SHIFT 27
175#define HF_AVX_EN_SHIFT 28
176
177#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
178#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
179#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
180#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
181#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
182#define HF_PE_MASK (1 << HF_PE_SHIFT)
183#define HF_TF_MASK (1 << HF_TF_SHIFT)
184#define HF_MP_MASK (1 << HF_MP_SHIFT)
185#define HF_EM_MASK (1 << HF_EM_SHIFT)
186#define HF_TS_MASK (1 << HF_TS_SHIFT)
187#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
188#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
189#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
190#define HF_RF_MASK (1 << HF_RF_SHIFT)
191#define HF_VM_MASK (1 << HF_VM_SHIFT)
192#define HF_AC_MASK (1 << HF_AC_SHIFT)
193#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
194#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
195#define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
196#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
197#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
198#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
199#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
200#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
201#define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
202#define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT)
203
204
205
206#define HF2_GIF_SHIFT 0
207#define HF2_HIF_SHIFT 1
208#define HF2_NMI_SHIFT 2
209#define HF2_VINTR_SHIFT 3
210#define HF2_SMM_INSIDE_NMI_SHIFT 4
211#define HF2_MPX_PR_SHIFT 5
212#define HF2_NPT_SHIFT 6
213#define HF2_IGNNE_SHIFT 7
214#define HF2_VGIF_SHIFT 8
215
216#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
217#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
218#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
219#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
220#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
221#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
222#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
223#define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
224#define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)
225
226#define CR0_PE_SHIFT 0
227#define CR0_MP_SHIFT 1
228
229#define CR0_PE_MASK (1U << 0)
230#define CR0_MP_MASK (1U << 1)
231#define CR0_EM_MASK (1U << 2)
232#define CR0_TS_MASK (1U << 3)
233#define CR0_ET_MASK (1U << 4)
234#define CR0_NE_MASK (1U << 5)
235#define CR0_WP_MASK (1U << 16)
236#define CR0_AM_MASK (1U << 18)
237#define CR0_NW_MASK (1U << 29)
238#define CR0_CD_MASK (1U << 30)
239#define CR0_PG_MASK (1U << 31)
240
241#define CR4_VME_MASK (1U << 0)
242#define CR4_PVI_MASK (1U << 1)
243#define CR4_TSD_MASK (1U << 2)
244#define CR4_DE_MASK (1U << 3)
245#define CR4_PSE_MASK (1U << 4)
246#define CR4_PAE_MASK (1U << 5)
247#define CR4_MCE_MASK (1U << 6)
248#define CR4_PGE_MASK (1U << 7)
249#define CR4_PCE_MASK (1U << 8)
250#define CR4_OSFXSR_SHIFT 9
251#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
252#define CR4_OSXMMEXCPT_MASK (1U << 10)
253#define CR4_UMIP_MASK (1U << 11)
254#define CR4_LA57_MASK (1U << 12)
255#define CR4_VMXE_MASK (1U << 13)
256#define CR4_SMXE_MASK (1U << 14)
257#define CR4_FSGSBASE_MASK (1U << 16)
258#define CR4_PCIDE_MASK (1U << 17)
259#define CR4_OSXSAVE_MASK (1U << 18)
260#define CR4_SMEP_MASK (1U << 20)
261#define CR4_SMAP_MASK (1U << 21)
262#define CR4_PKE_MASK (1U << 22)
263#define CR4_PKS_MASK (1U << 24)
264
265#define CR4_RESERVED_MASK \
266(~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
267 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
268 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
269 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
270 | CR4_LA57_MASK \
271 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
272 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
273
274#define DR6_BD (1 << 13)
275#define DR6_BS (1 << 14)
276#define DR6_BT (1 << 15)
277#define DR6_FIXED_1 0xffff0ff0
278
279#define DR7_GD (1 << 13)
280#define DR7_TYPE_SHIFT 16
281#define DR7_LEN_SHIFT 18
282#define DR7_FIXED_1 0x00000400
283#define DR7_GLOBAL_BP_MASK 0xaa
284#define DR7_LOCAL_BP_MASK 0x55
285#define DR7_MAX_BP 4
286#define DR7_TYPE_BP_INST 0x0
287#define DR7_TYPE_DATA_WR 0x1
288#define DR7_TYPE_IO_RW 0x2
289#define DR7_TYPE_DATA_RW 0x3
290
291#define DR_RESERVED_MASK 0xffffffff00000000ULL
292
293#define PG_PRESENT_BIT 0
294#define PG_RW_BIT 1
295#define PG_USER_BIT 2
296#define PG_PWT_BIT 3
297#define PG_PCD_BIT 4
298#define PG_ACCESSED_BIT 5
299#define PG_DIRTY_BIT 6
300#define PG_PSE_BIT 7
301#define PG_GLOBAL_BIT 8
302#define PG_PSE_PAT_BIT 12
303#define PG_PKRU_BIT 59
304#define PG_NX_BIT 63
305
306#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
307#define PG_RW_MASK (1 << PG_RW_BIT)
308#define PG_USER_MASK (1 << PG_USER_BIT)
309#define PG_PWT_MASK (1 << PG_PWT_BIT)
310#define PG_PCD_MASK (1 << PG_PCD_BIT)
311#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
312#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
313#define PG_PSE_MASK (1 << PG_PSE_BIT)
314#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
315#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
316#define PG_ADDRESS_MASK 0x000ffffffffff000LL
317#define PG_HI_USER_MASK 0x7ff0000000000000LL
318#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
319#define PG_NX_MASK (1ULL << PG_NX_BIT)
320
321#define PG_ERROR_W_BIT 1
322
323#define PG_ERROR_P_MASK 0x01
324#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
325#define PG_ERROR_U_MASK 0x04
326#define PG_ERROR_RSVD_MASK 0x08
327#define PG_ERROR_I_D_MASK 0x10
328#define PG_ERROR_PK_MASK 0x20
329
330#define PG_MODE_PAE (1 << 0)
331#define PG_MODE_LMA (1 << 1)
332#define PG_MODE_NXE (1 << 2)
333#define PG_MODE_PSE (1 << 3)
334#define PG_MODE_LA57 (1 << 4)
335#define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
336
337
338#define PG_MODE_WP (1 << 16)
339#define PG_MODE_PKE (1 << 17)
340#define PG_MODE_PKS (1 << 18)
341#define PG_MODE_SMEP (1 << 19)
342
343#define MCG_CTL_P (1ULL<<8)
344#define MCG_SER_P (1ULL<<24)
345#define MCG_LMCE_P (1ULL<<27)
346
347#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
348#define MCE_BANKS_DEF 10
349
350#define MCG_CAP_BANKS_MASK 0xff
351
352#define MCG_STATUS_RIPV (1ULL<<0)
353#define MCG_STATUS_EIPV (1ULL<<1)
354#define MCG_STATUS_MCIP (1ULL<<2)
355#define MCG_STATUS_LMCE (1ULL<<3)
356
357#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
358
359#define MCI_STATUS_VAL (1ULL<<63)
360#define MCI_STATUS_OVER (1ULL<<62)
361#define MCI_STATUS_UC (1ULL<<61)
362#define MCI_STATUS_EN (1ULL<<60)
363#define MCI_STATUS_MISCV (1ULL<<59)
364#define MCI_STATUS_ADDRV (1ULL<<58)
365#define MCI_STATUS_PCC (1ULL<<57)
366#define MCI_STATUS_S (1ULL<<56)
367#define MCI_STATUS_AR (1ULL<<55)
368
369
370#define MCM_ADDR_SEGOFF 0
371#define MCM_ADDR_LINEAR 1
372#define MCM_ADDR_PHYS 2
373#define MCM_ADDR_MEM 3
374#define MCM_ADDR_GENERIC 7
375
376#define MSR_IA32_TSC 0x10
377#define MSR_IA32_APICBASE 0x1b
378#define MSR_IA32_APICBASE_BSP (1<<8)
379#define MSR_IA32_APICBASE_ENABLE (1<<11)
380#define MSR_IA32_APICBASE_EXTD (1 << 10)
381#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
382#define MSR_IA32_FEATURE_CONTROL 0x0000003a
383#define MSR_TSC_ADJUST 0x0000003b
384#define MSR_IA32_SPEC_CTRL 0x48
385#define MSR_VIRT_SSBD 0xc001011f
386#define MSR_IA32_PRED_CMD 0x49
387#define MSR_IA32_UCODE_REV 0x8b
388#define MSR_IA32_CORE_CAPABILITY 0xcf
389
390#define MSR_IA32_ARCH_CAPABILITIES 0x10a
391#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
392
393#define MSR_IA32_PERF_CAPABILITIES 0x345
394#define PERF_CAP_LBR_FMT 0x3f
395
396#define MSR_IA32_TSX_CTRL 0x122
397#define MSR_IA32_TSCDEADLINE 0x6e0
398#define MSR_IA32_PKRS 0x6e1
399#define MSR_ARCH_LBR_CTL 0x000014ce
400#define MSR_ARCH_LBR_DEPTH 0x000014cf
401#define MSR_ARCH_LBR_FROM_0 0x00001500
402#define MSR_ARCH_LBR_TO_0 0x00001600
403#define MSR_ARCH_LBR_INFO_0 0x00001200
404
405#define FEATURE_CONTROL_LOCKED (1<<0)
406#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1)
407#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
408#define FEATURE_CONTROL_SGX_LC (1ULL << 17)
409#define FEATURE_CONTROL_SGX (1ULL << 18)
410#define FEATURE_CONTROL_LMCE (1<<20)
411
412#define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
413#define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
414#define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
415#define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
416
417#define MSR_P6_PERFCTR0 0xc1
418
419#define MSR_IA32_SMBASE 0x9e
420#define MSR_SMI_COUNT 0x34
421#define MSR_CORE_THREAD_COUNT 0x35
422#define MSR_MTRRcap 0xfe
423#define MSR_MTRRcap_VCNT 8
424#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
425#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
426
427#define MSR_IA32_SYSENTER_CS 0x174
428#define MSR_IA32_SYSENTER_ESP 0x175
429#define MSR_IA32_SYSENTER_EIP 0x176
430
431#define MSR_MCG_CAP 0x179
432#define MSR_MCG_STATUS 0x17a
433#define MSR_MCG_CTL 0x17b
434#define MSR_MCG_EXT_CTL 0x4d0
435
436#define MSR_P6_EVNTSEL0 0x186
437
438#define MSR_IA32_PERF_STATUS 0x198
439
440#define MSR_IA32_MISC_ENABLE 0x1a0
441
442#define MSR_IA32_MISC_ENABLE_DEFAULT 1
443#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
444
445#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
446#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
447
448#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
449
450#define MSR_MTRRfix64K_00000 0x250
451#define MSR_MTRRfix16K_80000 0x258
452#define MSR_MTRRfix16K_A0000 0x259
453#define MSR_MTRRfix4K_C0000 0x268
454#define MSR_MTRRfix4K_C8000 0x269
455#define MSR_MTRRfix4K_D0000 0x26a
456#define MSR_MTRRfix4K_D8000 0x26b
457#define MSR_MTRRfix4K_E0000 0x26c
458#define MSR_MTRRfix4K_E8000 0x26d
459#define MSR_MTRRfix4K_F0000 0x26e
460#define MSR_MTRRfix4K_F8000 0x26f
461
462#define MSR_PAT 0x277
463
464#define MSR_MTRRdefType 0x2ff
465
466#define MSR_CORE_PERF_FIXED_CTR0 0x309
467#define MSR_CORE_PERF_FIXED_CTR1 0x30a
468#define MSR_CORE_PERF_FIXED_CTR2 0x30b
469#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
470#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
471#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
472#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
473
474#define MSR_MC0_CTL 0x400
475#define MSR_MC0_STATUS 0x401
476#define MSR_MC0_ADDR 0x402
477#define MSR_MC0_MISC 0x403
478
479#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
480#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
481#define MSR_IA32_RTIT_CTL 0x570
482#define MSR_IA32_RTIT_STATUS 0x571
483#define MSR_IA32_RTIT_CR3_MATCH 0x572
484#define MSR_IA32_RTIT_ADDR0_A 0x580
485#define MSR_IA32_RTIT_ADDR0_B 0x581
486#define MSR_IA32_RTIT_ADDR1_A 0x582
487#define MSR_IA32_RTIT_ADDR1_B 0x583
488#define MSR_IA32_RTIT_ADDR2_A 0x584
489#define MSR_IA32_RTIT_ADDR2_B 0x585
490#define MSR_IA32_RTIT_ADDR3_A 0x586
491#define MSR_IA32_RTIT_ADDR3_B 0x587
492#define MAX_RTIT_ADDRS 8
493
494#define MSR_EFER 0xc0000080
495
496#define MSR_EFER_SCE (1 << 0)
497#define MSR_EFER_LME (1 << 8)
498#define MSR_EFER_LMA (1 << 10)
499#define MSR_EFER_NXE (1 << 11)
500#define MSR_EFER_SVME (1 << 12)
501#define MSR_EFER_FFXSR (1 << 14)
502
503#define MSR_EFER_RESERVED\
504 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
505 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
506 | MSR_EFER_FFXSR))
507
508#define MSR_STAR 0xc0000081
509#define MSR_LSTAR 0xc0000082
510#define MSR_CSTAR 0xc0000083
511#define MSR_FMASK 0xc0000084
512#define MSR_FSBASE 0xc0000100
513#define MSR_GSBASE 0xc0000101
514#define MSR_KERNELGSBASE 0xc0000102
515#define MSR_TSC_AUX 0xc0000103
516#define MSR_AMD64_TSC_RATIO 0xc0000104
517
518#define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
519
520#define MSR_VM_HSAVE_PA 0xc0010117
521
522#define MSR_IA32_XFD 0x000001c4
523#define MSR_IA32_XFD_ERR 0x000001c5
524
525#define MSR_IA32_BNDCFGS 0x00000d90
526#define MSR_IA32_XSS 0x00000da0
527#define MSR_IA32_UMWAIT_CONTROL 0xe1
528
529#define MSR_IA32_VMX_BASIC 0x00000480
530#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
531#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
532#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
533#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
534#define MSR_IA32_VMX_MISC 0x00000485
535#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
536#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
537#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
538#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
539#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
540#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
541#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
542#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
543#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
544#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
545#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
546#define MSR_IA32_VMX_VMFUNC 0x00000491
547
548#define XSTATE_FP_BIT 0
549#define XSTATE_SSE_BIT 1
550#define XSTATE_YMM_BIT 2
551#define XSTATE_BNDREGS_BIT 3
552#define XSTATE_BNDCSR_BIT 4
553#define XSTATE_OPMASK_BIT 5
554#define XSTATE_ZMM_Hi256_BIT 6
555#define XSTATE_Hi16_ZMM_BIT 7
556#define XSTATE_PKRU_BIT 9
557#define XSTATE_ARCH_LBR_BIT 15
558#define XSTATE_XTILE_CFG_BIT 17
559#define XSTATE_XTILE_DATA_BIT 18
560
561#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
562#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
563#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
564#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
565#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
566#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
567#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
568#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
569#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
570#define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
571#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
572#define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
573
574#define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK)
575
576#define ESA_FEATURE_ALIGN64_BIT 1
577#define ESA_FEATURE_XFD_BIT 2
578
579#define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
580#define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
581
582
583
584#define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
585 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
586 XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
587 XSTATE_ZMM_Hi256_MASK | \
588 XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
589 XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
590
591
592typedef enum FeatureWord {
593 FEAT_1_EDX,
594 FEAT_1_ECX,
595 FEAT_7_0_EBX,
596 FEAT_7_0_ECX,
597 FEAT_7_0_EDX,
598 FEAT_7_1_EAX,
599 FEAT_8000_0001_EDX,
600 FEAT_8000_0001_ECX,
601 FEAT_8000_0007_EDX,
602 FEAT_8000_0008_EBX,
603 FEAT_8000_0021_EAX,
604 FEAT_C000_0001_EDX,
605 FEAT_KVM,
606 FEAT_KVM_HINTS,
607 FEAT_SVM,
608 FEAT_XSAVE,
609 FEAT_6_EAX,
610 FEAT_XSAVE_XCR0_LO,
611 FEAT_XSAVE_XCR0_HI,
612 FEAT_ARCH_CAPABILITIES,
613 FEAT_CORE_CAPABILITY,
614 FEAT_PERF_CAPABILITIES,
615 FEAT_VMX_PROCBASED_CTLS,
616 FEAT_VMX_SECONDARY_CTLS,
617 FEAT_VMX_PINBASED_CTLS,
618 FEAT_VMX_EXIT_CTLS,
619 FEAT_VMX_ENTRY_CTLS,
620 FEAT_VMX_MISC,
621 FEAT_VMX_EPT_VPID_CAPS,
622 FEAT_VMX_BASIC,
623 FEAT_VMX_VMFUNC,
624 FEAT_14_0_ECX,
625 FEAT_SGX_12_0_EAX,
626 FEAT_SGX_12_0_EBX,
627 FEAT_SGX_12_1_EAX,
628 FEAT_XSAVE_XSS_LO,
629 FEAT_XSAVE_XSS_HI,
630 FEAT_7_1_EDX,
631 FEAT_7_2_EDX,
632 FEATURE_WORDS,
633} FeatureWord;
634
635typedef uint64_t FeatureWordArray[FEATURE_WORDS];
636uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
637 bool migratable_only);
638
639
640#define CPUID_FP87 (1U << 0)
641#define CPUID_VME (1U << 1)
642#define CPUID_DE (1U << 2)
643#define CPUID_PSE (1U << 3)
644#define CPUID_TSC (1U << 4)
645#define CPUID_MSR (1U << 5)
646#define CPUID_PAE (1U << 6)
647#define CPUID_MCE (1U << 7)
648#define CPUID_CX8 (1U << 8)
649#define CPUID_APIC (1U << 9)
650#define CPUID_SEP (1U << 11)
651#define CPUID_MTRR (1U << 12)
652#define CPUID_PGE (1U << 13)
653#define CPUID_MCA (1U << 14)
654#define CPUID_CMOV (1U << 15)
655#define CPUID_PAT (1U << 16)
656#define CPUID_PSE36 (1U << 17)
657#define CPUID_PN (1U << 18)
658#define CPUID_CLFLUSH (1U << 19)
659#define CPUID_DTS (1U << 21)
660#define CPUID_ACPI (1U << 22)
661#define CPUID_MMX (1U << 23)
662#define CPUID_FXSR (1U << 24)
663#define CPUID_SSE (1U << 25)
664#define CPUID_SSE2 (1U << 26)
665#define CPUID_SS (1U << 27)
666#define CPUID_HT (1U << 28)
667#define CPUID_TM (1U << 29)
668#define CPUID_IA64 (1U << 30)
669#define CPUID_PBE (1U << 31)
670
671#define CPUID_EXT_SSE3 (1U << 0)
672#define CPUID_EXT_PCLMULQDQ (1U << 1)
673#define CPUID_EXT_DTES64 (1U << 2)
674#define CPUID_EXT_MONITOR (1U << 3)
675#define CPUID_EXT_DSCPL (1U << 4)
676#define CPUID_EXT_VMX (1U << 5)
677#define CPUID_EXT_SMX (1U << 6)
678#define CPUID_EXT_EST (1U << 7)
679#define CPUID_EXT_TM2 (1U << 8)
680#define CPUID_EXT_SSSE3 (1U << 9)
681#define CPUID_EXT_CID (1U << 10)
682#define CPUID_EXT_FMA (1U << 12)
683#define CPUID_EXT_CX16 (1U << 13)
684#define CPUID_EXT_XTPR (1U << 14)
685#define CPUID_EXT_PDCM (1U << 15)
686#define CPUID_EXT_PCID (1U << 17)
687#define CPUID_EXT_DCA (1U << 18)
688#define CPUID_EXT_SSE41 (1U << 19)
689#define CPUID_EXT_SSE42 (1U << 20)
690#define CPUID_EXT_X2APIC (1U << 21)
691#define CPUID_EXT_MOVBE (1U << 22)
692#define CPUID_EXT_POPCNT (1U << 23)
693#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
694#define CPUID_EXT_AES (1U << 25)
695#define CPUID_EXT_XSAVE (1U << 26)
696#define CPUID_EXT_OSXSAVE (1U << 27)
697#define CPUID_EXT_AVX (1U << 28)
698#define CPUID_EXT_F16C (1U << 29)
699#define CPUID_EXT_RDRAND (1U << 30)
700#define CPUID_EXT_HYPERVISOR (1U << 31)
701
702#define CPUID_EXT2_FPU (1U << 0)
703#define CPUID_EXT2_VME (1U << 1)
704#define CPUID_EXT2_DE (1U << 2)
705#define CPUID_EXT2_PSE (1U << 3)
706#define CPUID_EXT2_TSC (1U << 4)
707#define CPUID_EXT2_MSR (1U << 5)
708#define CPUID_EXT2_PAE (1U << 6)
709#define CPUID_EXT2_MCE (1U << 7)
710#define CPUID_EXT2_CX8 (1U << 8)
711#define CPUID_EXT2_APIC (1U << 9)
712#define CPUID_EXT2_SYSCALL (1U << 11)
713#define CPUID_EXT2_MTRR (1U << 12)
714#define CPUID_EXT2_PGE (1U << 13)
715#define CPUID_EXT2_MCA (1U << 14)
716#define CPUID_EXT2_CMOV (1U << 15)
717#define CPUID_EXT2_PAT (1U << 16)
718#define CPUID_EXT2_PSE36 (1U << 17)
719#define CPUID_EXT2_MP (1U << 19)
720#define CPUID_EXT2_NX (1U << 20)
721#define CPUID_EXT2_MMXEXT (1U << 22)
722#define CPUID_EXT2_MMX (1U << 23)
723#define CPUID_EXT2_FXSR (1U << 24)
724#define CPUID_EXT2_FFXSR (1U << 25)
725#define CPUID_EXT2_PDPE1GB (1U << 26)
726#define CPUID_EXT2_RDTSCP (1U << 27)
727#define CPUID_EXT2_LM (1U << 29)
728#define CPUID_EXT2_3DNOWEXT (1U << 30)
729#define CPUID_EXT2_3DNOW (1U << 31)
730
731
732#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
733 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
734 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
735 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
736 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
737 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
738 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
739 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
740 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
741
742#define CPUID_EXT3_LAHF_LM (1U << 0)
743#define CPUID_EXT3_CMP_LEG (1U << 1)
744#define CPUID_EXT3_SVM (1U << 2)
745#define CPUID_EXT3_EXTAPIC (1U << 3)
746#define CPUID_EXT3_CR8LEG (1U << 4)
747#define CPUID_EXT3_ABM (1U << 5)
748#define CPUID_EXT3_SSE4A (1U << 6)
749#define CPUID_EXT3_MISALIGNSSE (1U << 7)
750#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
751#define CPUID_EXT3_OSVW (1U << 9)
752#define CPUID_EXT3_IBS (1U << 10)
753#define CPUID_EXT3_XOP (1U << 11)
754#define CPUID_EXT3_SKINIT (1U << 12)
755#define CPUID_EXT3_WDT (1U << 13)
756#define CPUID_EXT3_LWP (1U << 15)
757#define CPUID_EXT3_FMA4 (1U << 16)
758#define CPUID_EXT3_TCE (1U << 17)
759#define CPUID_EXT3_NODEID (1U << 19)
760#define CPUID_EXT3_TBM (1U << 21)
761#define CPUID_EXT3_TOPOEXT (1U << 22)
762#define CPUID_EXT3_PERFCORE (1U << 23)
763#define CPUID_EXT3_PERFNB (1U << 24)
764
765#define CPUID_SVM_NPT (1U << 0)
766#define CPUID_SVM_LBRV (1U << 1)
767#define CPUID_SVM_SVMLOCK (1U << 2)
768#define CPUID_SVM_NRIPSAVE (1U << 3)
769#define CPUID_SVM_TSCSCALE (1U << 4)
770#define CPUID_SVM_VMCBCLEAN (1U << 5)
771#define CPUID_SVM_FLUSHASID (1U << 6)
772#define CPUID_SVM_DECODEASSIST (1U << 7)
773#define CPUID_SVM_PAUSEFILTER (1U << 10)
774#define CPUID_SVM_PFTHRESHOLD (1U << 12)
775#define CPUID_SVM_AVIC (1U << 13)
776#define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
777#define CPUID_SVM_VGIF (1U << 16)
778#define CPUID_SVM_VNMI (1U << 25)
779#define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
780
781
782#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
783
784#define CPUID_7_0_EBX_SGX (1U << 2)
785
786#define CPUID_7_0_EBX_BMI1 (1U << 3)
787
788#define CPUID_7_0_EBX_HLE (1U << 4)
789
790#define CPUID_7_0_EBX_AVX2 (1U << 5)
791
792#define CPUID_7_0_EBX_SMEP (1U << 7)
793
794#define CPUID_7_0_EBX_BMI2 (1U << 8)
795
796#define CPUID_7_0_EBX_ERMS (1U << 9)
797
798#define CPUID_7_0_EBX_INVPCID (1U << 10)
799
800#define CPUID_7_0_EBX_RTM (1U << 11)
801
802#define CPUID_7_0_EBX_MPX (1U << 14)
803
804#define CPUID_7_0_EBX_AVX512F (1U << 16)
805
806#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
807
808#define CPUID_7_0_EBX_RDSEED (1U << 18)
809
810#define CPUID_7_0_EBX_ADX (1U << 19)
811
812#define CPUID_7_0_EBX_SMAP (1U << 20)
813
814#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
815
816#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
817
818#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
819
820#define CPUID_7_0_EBX_CLWB (1U << 24)
821
822#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
823
824#define CPUID_7_0_EBX_AVX512PF (1U << 26)
825
826#define CPUID_7_0_EBX_AVX512ER (1U << 27)
827
828#define CPUID_7_0_EBX_AVX512CD (1U << 28)
829
830#define CPUID_7_0_EBX_SHA_NI (1U << 29)
831
832#define CPUID_7_0_EBX_AVX512BW (1U << 30)
833
834#define CPUID_7_0_EBX_AVX512VL (1U << 31)
835
836
837#define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
838
839#define CPUID_7_0_ECX_UMIP (1U << 2)
840
841#define CPUID_7_0_ECX_PKU (1U << 3)
842
843#define CPUID_7_0_ECX_OSPKE (1U << 4)
844
845#define CPUID_7_0_ECX_WAITPKG (1U << 5)
846
847#define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
848
849#define CPUID_7_0_ECX_GFNI (1U << 8)
850
851#define CPUID_7_0_ECX_VAES (1U << 9)
852
853#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
854
855#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
856
857#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
858
859#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
860
861#define CPUID_7_0_ECX_LA57 (1U << 16)
862
863#define CPUID_7_0_ECX_RDPID (1U << 22)
864
865#define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
866
867#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
868
869#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
870
871#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
872
873#define CPUID_7_0_ECX_SGX_LC (1U << 30)
874
875#define CPUID_7_0_ECX_PKS (1U << 31)
876
877
878#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
879
880#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
881
882#define CPUID_7_0_EDX_FSRM (1U << 4)
883
884#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
885
886#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
887
888#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
889
890#define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
891
892#define CPUID_7_0_EDX_AMX_BF16 (1U << 22)
893
894#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
895
896#define CPUID_7_0_EDX_AMX_TILE (1U << 24)
897
898#define CPUID_7_0_EDX_AMX_INT8 (1U << 25)
899
900#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
901
902#define CPUID_7_0_EDX_STIBP (1U << 27)
903
904#define CPUID_7_0_EDX_FLUSH_L1D (1U << 28)
905
906#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
907
908#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
909
910#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
911
912
913#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
914
915#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
916
917#define CPUID_7_1_EAX_CMPCCXADD (1U << 7)
918
919#define CPUID_7_1_EAX_FZRM (1U << 10)
920
921#define CPUID_7_1_EAX_FSRS (1U << 11)
922
923#define CPUID_7_1_EAX_FSRC (1U << 12)
924
925#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
926
927#define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
928
929
930#define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
931
932#define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
933
934#define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
935
936
937#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
938
939
940#define CPUID_D_1_EAX_XFD (1U << 4)
941
942
943#define CPUID_14_0_ECX_LIP (1U << 31)
944
945
946#define CPUID_8000_0008_EBX_CLZERO (1U << 0)
947
948#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
949
950#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
951
952#define CPUID_8000_0008_EBX_IBPB (1U << 12)
953
954#define CPUID_8000_0008_EBX_IBRS (1U << 14)
955
956#define CPUID_8000_0008_EBX_STIBP (1U << 15)
957
958#define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17)
959
960#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
961
962#define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
963
964
965#define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0)
966
967#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
968
969#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
970
971#define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
972
973#define CPUID_XSAVE_XSAVEOPT (1U << 0)
974#define CPUID_XSAVE_XSAVEC (1U << 1)
975#define CPUID_XSAVE_XGETBV1 (1U << 2)
976#define CPUID_XSAVE_XSAVES (1U << 3)
977
978#define CPUID_6_EAX_ARAT (1U << 2)
979
980
981#define CPUID_APM_INVTSC (1U << 8)
982
983#define CPUID_VENDOR_SZ 12
984
985#define CPUID_VENDOR_INTEL_1 0x756e6547
986#define CPUID_VENDOR_INTEL_2 0x49656e69
987#define CPUID_VENDOR_INTEL_3 0x6c65746e
988#define CPUID_VENDOR_INTEL "GenuineIntel"
989
990#define CPUID_VENDOR_AMD_1 0x68747541
991#define CPUID_VENDOR_AMD_2 0x69746e65
992#define CPUID_VENDOR_AMD_3 0x444d4163
993#define CPUID_VENDOR_AMD "AuthenticAMD"
994
995#define CPUID_VENDOR_VIA "CentaurHauls"
996
997#define CPUID_VENDOR_HYGON "HygonGenuine"
998
999#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
1000 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
1001 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
1002#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
1003 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
1004 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
1005
1006#define CPUID_MWAIT_IBE (1U << 1)
1007#define CPUID_MWAIT_EMX (1U << 0)
1008
1009
1010#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
1011#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
1012#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
1013#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
1014
1015
1016#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
1017#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
1018#define MSR_ARCH_CAP_RSBA (1U << 2)
1019#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1020#define MSR_ARCH_CAP_SSB_NO (1U << 4)
1021#define MSR_ARCH_CAP_MDS_NO (1U << 5)
1022#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
1023#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
1024#define MSR_ARCH_CAP_TAA_NO (1U << 8)
1025#define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13)
1026#define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
1027#define MSR_ARCH_CAP_PSDP_NO (1U << 15)
1028#define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
1029#define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
1030
1031#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
1032
1033
1034#define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
1035#define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
1036#define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
1037#define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
1038#define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
1039#define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
1040
1041#define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
1042#define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
1043#define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
1044#define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
1045#define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
1046#define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
1047#define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
1048#define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
1049
1050#define MSR_VMX_EPT_EXECONLY (1ULL << 0)
1051#define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
1052#define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
1053#define MSR_VMX_EPT_UC (1ULL << 8)
1054#define MSR_VMX_EPT_WB (1ULL << 14)
1055#define MSR_VMX_EPT_2MB (1ULL << 16)
1056#define MSR_VMX_EPT_1GB (1ULL << 17)
1057#define MSR_VMX_EPT_INVEPT (1ULL << 20)
1058#define MSR_VMX_EPT_AD_BITS (1ULL << 21)
1059#define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
1060#define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
1061#define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
1062#define MSR_VMX_EPT_INVVPID (1ULL << 32)
1063#define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
1064#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
1065#define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
1066#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1067
1068#define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1069
1070
1071
1072#define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1073#define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1074#define VMX_CPU_BASED_HLT_EXITING 0x00000080
1075#define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1076#define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1077#define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1078#define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1079#define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1080#define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1081#define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1082#define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1083#define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1084#define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1085#define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1086#define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1087#define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1088#define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1089#define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1090#define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1091#define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1092#define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1093
1094#define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1095#define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1096#define VMX_SECONDARY_EXEC_DESC 0x00000004
1097#define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1098#define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1099#define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1100#define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1101#define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1102#define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1103#define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1104#define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1105#define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1106#define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1107#define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1108#define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1109#define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1110#define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1111#define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1112#define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1113#define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1114
1115#define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1116#define VMX_PIN_BASED_NMI_EXITING 0x00000008
1117#define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1118#define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1119#define VMX_PIN_BASED_POSTED_INTR 0x00000080
1120
1121#define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1122#define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1123#define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1124#define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1125#define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1126#define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1127#define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1128#define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1129#define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1130#define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1131#define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1132#define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1133#define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1134
1135#define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1136#define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1137#define VMX_VM_ENTRY_SMM 0x00000400
1138#define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1139#define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1140#define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1141#define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1142#define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1143#define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1144#define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1145#define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1146
1147
1148#define HYPERV_FEAT_RELAXED 0
1149#define HYPERV_FEAT_VAPIC 1
1150#define HYPERV_FEAT_TIME 2
1151#define HYPERV_FEAT_CRASH 3
1152#define HYPERV_FEAT_RESET 4
1153#define HYPERV_FEAT_VPINDEX 5
1154#define HYPERV_FEAT_RUNTIME 6
1155#define HYPERV_FEAT_SYNIC 7
1156#define HYPERV_FEAT_STIMER 8
1157#define HYPERV_FEAT_FREQUENCIES 9
1158#define HYPERV_FEAT_REENLIGHTENMENT 10
1159#define HYPERV_FEAT_TLBFLUSH 11
1160#define HYPERV_FEAT_EVMCS 12
1161#define HYPERV_FEAT_IPI 13
1162#define HYPERV_FEAT_STIMER_DIRECT 14
1163#define HYPERV_FEAT_AVIC 15
1164#define HYPERV_FEAT_SYNDBG 16
1165#define HYPERV_FEAT_MSR_BITMAP 17
1166#define HYPERV_FEAT_XMM_INPUT 18
1167#define HYPERV_FEAT_TLBFLUSH_EXT 19
1168#define HYPERV_FEAT_TLBFLUSH_DIRECT 20
1169
1170#ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1171#define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1172#endif
1173
1174#define EXCP00_DIVZ 0
1175#define EXCP01_DB 1
1176#define EXCP02_NMI 2
1177#define EXCP03_INT3 3
1178#define EXCP04_INTO 4
1179#define EXCP05_BOUND 5
1180#define EXCP06_ILLOP 6
1181#define EXCP07_PREX 7
1182#define EXCP08_DBLE 8
1183#define EXCP09_XERR 9
1184#define EXCP0A_TSS 10
1185#define EXCP0B_NOSEG 11
1186#define EXCP0C_STACK 12
1187#define EXCP0D_GPF 13
1188#define EXCP0E_PAGE 14
1189#define EXCP10_COPR 16
1190#define EXCP11_ALGN 17
1191#define EXCP12_MCHK 18
1192
1193#define EXCP_VMEXIT 0x100
1194#define EXCP_SYSCALL 0x101
1195#define EXCP_VSYSCALL 0x102
1196
1197
1198#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1199#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1200#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1201#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1202#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1203#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1204#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1205
1206
1207#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1208
1209
1210
1211
1212
1213
1214
1215
1216typedef enum {
1217 CC_OP_DYNAMIC,
1218 CC_OP_EFLAGS,
1219
1220 CC_OP_MULB,
1221 CC_OP_MULW,
1222 CC_OP_MULL,
1223 CC_OP_MULQ,
1224
1225 CC_OP_ADDB,
1226 CC_OP_ADDW,
1227 CC_OP_ADDL,
1228 CC_OP_ADDQ,
1229
1230 CC_OP_ADCB,
1231 CC_OP_ADCW,
1232 CC_OP_ADCL,
1233 CC_OP_ADCQ,
1234
1235 CC_OP_SUBB,
1236 CC_OP_SUBW,
1237 CC_OP_SUBL,
1238 CC_OP_SUBQ,
1239
1240 CC_OP_SBBB,
1241 CC_OP_SBBW,
1242 CC_OP_SBBL,
1243 CC_OP_SBBQ,
1244
1245 CC_OP_LOGICB,
1246 CC_OP_LOGICW,
1247 CC_OP_LOGICL,
1248 CC_OP_LOGICQ,
1249
1250 CC_OP_INCB,
1251 CC_OP_INCW,
1252 CC_OP_INCL,
1253 CC_OP_INCQ,
1254
1255 CC_OP_DECB,
1256 CC_OP_DECW,
1257 CC_OP_DECL,
1258 CC_OP_DECQ,
1259
1260 CC_OP_SHLB,
1261 CC_OP_SHLW,
1262 CC_OP_SHLL,
1263 CC_OP_SHLQ,
1264
1265 CC_OP_SARB,
1266 CC_OP_SARW,
1267 CC_OP_SARL,
1268 CC_OP_SARQ,
1269
1270 CC_OP_BMILGB,
1271 CC_OP_BMILGW,
1272 CC_OP_BMILGL,
1273 CC_OP_BMILGQ,
1274
1275 CC_OP_ADCX,
1276 CC_OP_ADOX,
1277 CC_OP_ADCOX,
1278
1279 CC_OP_CLR,
1280 CC_OP_POPCNT,
1281
1282 CC_OP_NB,
1283} CCOp;
1284
1285typedef struct SegmentCache {
1286 uint32_t selector;
1287 target_ulong base;
1288 uint32_t limit;
1289 uint32_t flags;
1290} SegmentCache;
1291
1292typedef union MMXReg {
1293 uint8_t _b_MMXReg[64 / 8];
1294 uint16_t _w_MMXReg[64 / 16];
1295 uint32_t _l_MMXReg[64 / 32];
1296 uint64_t _q_MMXReg[64 / 64];
1297 float32 _s_MMXReg[64 / 32];
1298 float64 _d_MMXReg[64 / 64];
1299} MMXReg;
1300
1301typedef union XMMReg {
1302 uint64_t _q_XMMReg[128 / 64];
1303} XMMReg;
1304
1305typedef union YMMReg {
1306 uint64_t _q_YMMReg[256 / 64];
1307 XMMReg _x_YMMReg[256 / 128];
1308} YMMReg;
1309
1310typedef union ZMMReg {
1311 uint8_t _b_ZMMReg[512 / 8];
1312 uint16_t _w_ZMMReg[512 / 16];
1313 uint32_t _l_ZMMReg[512 / 32];
1314 uint64_t _q_ZMMReg[512 / 64];
1315 float16 _h_ZMMReg[512 / 16];
1316 float32 _s_ZMMReg[512 / 32];
1317 float64 _d_ZMMReg[512 / 64];
1318 XMMReg _x_ZMMReg[512 / 128];
1319 YMMReg _y_ZMMReg[512 / 256];
1320} ZMMReg;
1321
1322typedef struct BNDReg {
1323 uint64_t lb;
1324 uint64_t ub;
1325} BNDReg;
1326
1327typedef struct BNDCSReg {
1328 uint64_t cfgu;
1329 uint64_t sts;
1330} BNDCSReg;
1331
1332#define BNDCFG_ENABLE 1ULL
1333#define BNDCFG_BNDPRESERVE 2ULL
1334#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1335
1336#if HOST_BIG_ENDIAN
1337#define ZMM_B(n) _b_ZMMReg[63 - (n)]
1338#define ZMM_W(n) _w_ZMMReg[31 - (n)]
1339#define ZMM_L(n) _l_ZMMReg[15 - (n)]
1340#define ZMM_H(n) _h_ZMMReg[31 - (n)]
1341#define ZMM_S(n) _s_ZMMReg[15 - (n)]
1342#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1343#define ZMM_D(n) _d_ZMMReg[7 - (n)]
1344#define ZMM_X(n) _x_ZMMReg[3 - (n)]
1345#define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1346
1347#define XMM_Q(n) _q_XMMReg[1 - (n)]
1348
1349#define YMM_Q(n) _q_YMMReg[3 - (n)]
1350#define YMM_X(n) _x_YMMReg[1 - (n)]
1351
1352#define MMX_B(n) _b_MMXReg[7 - (n)]
1353#define MMX_W(n) _w_MMXReg[3 - (n)]
1354#define MMX_L(n) _l_MMXReg[1 - (n)]
1355#define MMX_S(n) _s_MMXReg[1 - (n)]
1356#else
1357#define ZMM_B(n) _b_ZMMReg[n]
1358#define ZMM_W(n) _w_ZMMReg[n]
1359#define ZMM_L(n) _l_ZMMReg[n]
1360#define ZMM_H(n) _h_ZMMReg[n]
1361#define ZMM_S(n) _s_ZMMReg[n]
1362#define ZMM_Q(n) _q_ZMMReg[n]
1363#define ZMM_D(n) _d_ZMMReg[n]
1364#define ZMM_X(n) _x_ZMMReg[n]
1365#define ZMM_Y(n) _y_ZMMReg[n]
1366
1367#define XMM_Q(n) _q_XMMReg[n]
1368
1369#define YMM_Q(n) _q_YMMReg[n]
1370#define YMM_X(n) _x_YMMReg[n]
1371
1372#define MMX_B(n) _b_MMXReg[n]
1373#define MMX_W(n) _w_MMXReg[n]
1374#define MMX_L(n) _l_MMXReg[n]
1375#define MMX_S(n) _s_MMXReg[n]
1376#endif
1377#define MMX_Q(n) _q_MMXReg[n]
1378
1379typedef union {
1380 floatx80 d __attribute__((aligned(16)));
1381 MMXReg mmx;
1382} FPReg;
1383
1384typedef struct {
1385 uint64_t base;
1386 uint64_t mask;
1387} MTRRVar;
1388
1389#define CPU_NB_REGS64 16
1390#define CPU_NB_REGS32 8
1391
1392#ifdef TARGET_X86_64
1393#define CPU_NB_REGS CPU_NB_REGS64
1394#else
1395#define CPU_NB_REGS CPU_NB_REGS32
1396#endif
1397
1398#define MAX_FIXED_COUNTERS 3
1399#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1400
1401#define TARGET_INSN_START_EXTRA_WORDS 1
1402
1403#define NB_OPMASK_REGS 8
1404
1405
1406
1407
1408#define UNASSIGNED_APIC_ID 0xFFFFFFFF
1409
1410typedef union X86LegacyXSaveArea {
1411 struct {
1412 uint16_t fcw;
1413 uint16_t fsw;
1414 uint8_t ftw;
1415 uint8_t reserved;
1416 uint16_t fpop;
1417 uint64_t fpip;
1418 uint64_t fpdp;
1419 uint32_t mxcsr;
1420 uint32_t mxcsr_mask;
1421 FPReg fpregs[8];
1422 uint8_t xmm_regs[16][16];
1423 };
1424 uint8_t data[512];
1425} X86LegacyXSaveArea;
1426
1427typedef struct X86XSaveHeader {
1428 uint64_t xstate_bv;
1429 uint64_t xcomp_bv;
1430 uint64_t reserve0;
1431 uint8_t reserved[40];
1432} X86XSaveHeader;
1433
1434
1435typedef struct XSaveAVX {
1436 uint8_t ymmh[16][16];
1437} XSaveAVX;
1438
1439
1440typedef struct XSaveBNDREG {
1441 BNDReg bnd_regs[4];
1442} XSaveBNDREG;
1443
1444
1445typedef union XSaveBNDCSR {
1446 BNDCSReg bndcsr;
1447 uint8_t data[64];
1448} XSaveBNDCSR;
1449
1450
1451typedef struct XSaveOpmask {
1452 uint64_t opmask_regs[NB_OPMASK_REGS];
1453} XSaveOpmask;
1454
1455
1456typedef struct XSaveZMM_Hi256 {
1457 uint8_t zmm_hi256[16][32];
1458} XSaveZMM_Hi256;
1459
1460
1461typedef struct XSaveHi16_ZMM {
1462 uint8_t hi16_zmm[16][64];
1463} XSaveHi16_ZMM;
1464
1465
1466typedef struct XSavePKRU {
1467 uint32_t pkru;
1468 uint32_t padding;
1469} XSavePKRU;
1470
1471
1472typedef struct XSaveXTILECFG {
1473 uint8_t xtilecfg[64];
1474} XSaveXTILECFG;
1475
1476
1477typedef struct XSaveXTILEDATA {
1478 uint8_t xtiledata[8][1024];
1479} XSaveXTILEDATA;
1480
1481typedef struct {
1482 uint64_t from;
1483 uint64_t to;
1484 uint64_t info;
1485} LBREntry;
1486
1487#define ARCH_LBR_NR_ENTRIES 32
1488
1489
1490typedef struct XSavesArchLBR {
1491 uint64_t lbr_ctl;
1492 uint64_t lbr_depth;
1493 uint64_t ler_from;
1494 uint64_t ler_to;
1495 uint64_t ler_info;
1496 LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1497} XSavesArchLBR;
1498
1499QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1500QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1501QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1502QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1503QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1504QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1505QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1506QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1507QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1508QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1509
1510typedef struct ExtSaveArea {
1511 uint32_t feature, bits;
1512 uint32_t offset, size;
1513 uint32_t ecx;
1514} ExtSaveArea;
1515
1516#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1517
1518extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
1519
1520typedef enum TPRAccess {
1521 TPR_ACCESS_READ,
1522 TPR_ACCESS_WRITE,
1523} TPRAccess;
1524
1525
1526
1527enum CacheType {
1528 DATA_CACHE,
1529 INSTRUCTION_CACHE,
1530 UNIFIED_CACHE
1531};
1532
1533typedef struct CPUCacheInfo {
1534 enum CacheType type;
1535 uint8_t level;
1536
1537 uint32_t size;
1538
1539 uint16_t line_size;
1540
1541
1542
1543
1544 uint8_t associativity;
1545
1546 uint8_t partitions;
1547
1548 uint32_t sets;
1549
1550
1551
1552
1553
1554 uint8_t lines_per_tag;
1555
1556
1557 bool self_init;
1558
1559
1560
1561
1562
1563 bool no_invd_sharing;
1564
1565
1566
1567
1568 bool inclusive;
1569
1570
1571
1572
1573 bool complex_indexing;
1574} CPUCacheInfo;
1575
1576
1577typedef struct CPUCaches {
1578 CPUCacheInfo *l1d_cache;
1579 CPUCacheInfo *l1i_cache;
1580 CPUCacheInfo *l2_cache;
1581 CPUCacheInfo *l3_cache;
1582} CPUCaches;
1583
1584typedef struct HVFX86LazyFlags {
1585 target_ulong result;
1586 target_ulong auxbits;
1587} HVFX86LazyFlags;
1588
1589typedef struct CPUArchState {
1590
1591 target_ulong regs[CPU_NB_REGS];
1592 target_ulong eip;
1593 target_ulong eflags;
1594
1595
1596
1597
1598 target_ulong cc_dst;
1599 target_ulong cc_src;
1600 target_ulong cc_src2;
1601 uint32_t cc_op;
1602 int32_t df;
1603 uint32_t hflags;
1604
1605 uint32_t hflags2;
1606
1607
1608 SegmentCache segs[6];
1609 SegmentCache ldt;
1610 SegmentCache tr;
1611 SegmentCache gdt;
1612 SegmentCache idt;
1613
1614 target_ulong cr[5];
1615
1616 bool pdptrs_valid;
1617 uint64_t pdptrs[4];
1618 int32_t a20_mask;
1619
1620 BNDReg bnd_regs[4];
1621 BNDCSReg bndcs_regs;
1622 uint64_t msr_bndcfgs;
1623 uint64_t efer;
1624
1625
1626 struct {} start_init_save;
1627
1628
1629 unsigned int fpstt;
1630 uint16_t fpus;
1631 uint16_t fpuc;
1632 uint8_t fptags[8];
1633 FPReg fpregs[8];
1634
1635 uint16_t fpop;
1636 uint16_t fpcs;
1637 uint16_t fpds;
1638 uint64_t fpip;
1639 uint64_t fpdp;
1640
1641
1642 float_status fp_status;
1643 floatx80 ft0;
1644
1645 float_status mmx_status;
1646 float_status sse_status;
1647 uint32_t mxcsr;
1648 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
1649 ZMMReg xmm_t0 QEMU_ALIGNED(16);
1650 MMXReg mmx_t0;
1651
1652 uint64_t opmask_regs[NB_OPMASK_REGS];
1653#ifdef TARGET_X86_64
1654 uint8_t xtilecfg[64];
1655 uint8_t xtiledata[8192];
1656#endif
1657
1658
1659 uint32_t sysenter_cs;
1660 target_ulong sysenter_esp;
1661 target_ulong sysenter_eip;
1662 uint64_t star;
1663
1664 uint64_t vm_hsave;
1665
1666#ifdef TARGET_X86_64
1667 target_ulong lstar;
1668 target_ulong cstar;
1669 target_ulong fmask;
1670 target_ulong kernelgsbase;
1671#endif
1672
1673 uint64_t tsc_adjust;
1674 uint64_t tsc_deadline;
1675 uint64_t tsc_aux;
1676
1677 uint64_t xcr0;
1678
1679 uint64_t mcg_status;
1680 uint64_t msr_ia32_misc_enable;
1681 uint64_t msr_ia32_feature_control;
1682 uint64_t msr_ia32_sgxlepubkeyhash[4];
1683
1684 uint64_t msr_fixed_ctr_ctrl;
1685 uint64_t msr_global_ctrl;
1686 uint64_t msr_global_status;
1687 uint64_t msr_global_ovf_ctrl;
1688 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1689 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1690 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1691
1692 uint64_t pat;
1693 uint32_t smbase;
1694 uint64_t msr_smi_count;
1695
1696 uint32_t pkru;
1697 uint32_t pkrs;
1698 uint32_t tsx_ctrl;
1699
1700 uint64_t spec_ctrl;
1701 uint64_t amd_tsc_scale_msr;
1702 uint64_t virt_ssbd;
1703
1704
1705 struct {} end_init_save;
1706
1707 uint64_t system_time_msr;
1708 uint64_t wall_clock_msr;
1709 uint64_t steal_time_msr;
1710 uint64_t async_pf_en_msr;
1711 uint64_t async_pf_int_msr;
1712 uint64_t pv_eoi_en_msr;
1713 uint64_t poll_control_msr;
1714
1715
1716 uint64_t msr_hv_hypercall;
1717 uint64_t msr_hv_guest_os_id;
1718 uint64_t msr_hv_tsc;
1719 uint64_t msr_hv_syndbg_control;
1720 uint64_t msr_hv_syndbg_status;
1721 uint64_t msr_hv_syndbg_send_page;
1722 uint64_t msr_hv_syndbg_recv_page;
1723 uint64_t msr_hv_syndbg_pending_page;
1724 uint64_t msr_hv_syndbg_options;
1725
1726
1727 uint64_t msr_hv_vapic;
1728 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1729 uint64_t msr_hv_runtime;
1730 uint64_t msr_hv_synic_control;
1731 uint64_t msr_hv_synic_evt_page;
1732 uint64_t msr_hv_synic_msg_page;
1733 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1734 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1735 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1736 uint64_t msr_hv_reenlightenment_control;
1737 uint64_t msr_hv_tsc_emulation_control;
1738 uint64_t msr_hv_tsc_emulation_status;
1739
1740 uint64_t msr_rtit_ctrl;
1741 uint64_t msr_rtit_status;
1742 uint64_t msr_rtit_output_base;
1743 uint64_t msr_rtit_output_mask;
1744 uint64_t msr_rtit_cr3_match;
1745 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1746
1747
1748 uint64_t msr_xfd;
1749 uint64_t msr_xfd_err;
1750
1751
1752 uint64_t msr_lbr_ctl;
1753 uint64_t msr_lbr_depth;
1754 LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1755
1756
1757 int error_code;
1758 int exception_is_int;
1759 target_ulong exception_next_eip;
1760 target_ulong dr[8];
1761 union {
1762 struct CPUBreakpoint *cpu_breakpoint[4];
1763 struct CPUWatchpoint *cpu_watchpoint[4];
1764 };
1765 int old_exception;
1766
1767 uint64_t vm_vmcb;
1768 uint64_t tsc_offset;
1769 uint64_t intercept;
1770 uint16_t intercept_cr_read;
1771 uint16_t intercept_cr_write;
1772 uint16_t intercept_dr_read;
1773 uint16_t intercept_dr_write;
1774 uint32_t intercept_exceptions;
1775 uint64_t nested_cr3;
1776 uint32_t nested_pg_mode;
1777 uint8_t v_tpr;
1778 uint32_t int_ctl;
1779
1780
1781 uint8_t nmi_injected;
1782 uint8_t nmi_pending;
1783
1784 uintptr_t retaddr;
1785
1786
1787 struct {} end_reset_fields;
1788
1789
1790
1791
1792
1793 uint32_t cpuid_level_func7;
1794
1795 uint32_t cpuid_min_level_func7;
1796
1797 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1798
1799 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1800
1801 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1802 uint32_t cpuid_vendor1;
1803 uint32_t cpuid_vendor2;
1804 uint32_t cpuid_vendor3;
1805 uint32_t cpuid_version;
1806 FeatureWordArray features;
1807
1808 FeatureWordArray user_features;
1809 uint32_t cpuid_model[12];
1810
1811
1812
1813
1814 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1815
1816
1817 uint64_t mtrr_fixed[11];
1818 uint64_t mtrr_deftype;
1819 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1820
1821
1822 uint32_t mp_state;
1823 int32_t exception_nr;
1824 int32_t interrupt_injected;
1825 uint8_t soft_interrupt;
1826 uint8_t exception_pending;
1827 uint8_t exception_injected;
1828 uint8_t has_error_code;
1829 uint8_t exception_has_payload;
1830 uint64_t exception_payload;
1831 uint8_t triple_fault_pending;
1832 uint32_t ins_len;
1833 uint32_t sipi_vector;
1834 bool tsc_valid;
1835 int64_t tsc_khz;
1836 int64_t user_tsc_khz;
1837 uint64_t apic_bus_freq;
1838 uint64_t tsc;
1839#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1840 void *xsave_buf;
1841 uint32_t xsave_buf_len;
1842#endif
1843#if defined(CONFIG_KVM)
1844 struct kvm_nested_state *nested_state;
1845 MemoryRegion *xen_vcpu_info_mr;
1846 void *xen_vcpu_info_hva;
1847 uint64_t xen_vcpu_info_gpa;
1848 uint64_t xen_vcpu_info_default_gpa;
1849 uint64_t xen_vcpu_time_info_gpa;
1850 uint64_t xen_vcpu_runstate_gpa;
1851 uint8_t xen_vcpu_callback_vector;
1852 bool xen_callback_asserted;
1853 uint16_t xen_virq[XEN_NR_VIRQS];
1854 uint64_t xen_singleshot_timer_ns;
1855 QEMUTimer *xen_singleshot_timer;
1856 uint64_t xen_periodic_timer_period;
1857 QEMUTimer *xen_periodic_timer;
1858 QemuMutex xen_timers_lock;
1859#endif
1860#if defined(CONFIG_HVF)
1861 HVFX86LazyFlags hvf_lflags;
1862 void *hvf_mmio_buf;
1863#endif
1864
1865 uint64_t mcg_cap;
1866 uint64_t mcg_ctl;
1867 uint64_t mcg_ext_ctl;
1868 uint64_t mce_banks[MCE_BANKS_DEF*4];
1869 uint64_t xstate_bv;
1870
1871
1872 uint16_t fpus_vmstate;
1873 uint16_t fptag_vmstate;
1874 uint16_t fpregs_format_vmstate;
1875
1876 uint64_t xss;
1877 uint32_t umwait;
1878
1879 TPRAccess tpr_access_type;
1880
1881 unsigned nr_dies;
1882} CPUX86State;
1883
1884struct kvm_msrs;
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895struct ArchCPU {
1896
1897 CPUState parent_obj;
1898
1899
1900 CPUNegativeOffsetState neg;
1901 CPUX86State env;
1902 VMChangeStateEntry *vmsentry;
1903
1904 uint64_t ucode_rev;
1905
1906 uint32_t hyperv_spinlock_attempts;
1907 char *hyperv_vendor;
1908 bool hyperv_synic_kvm_only;
1909 uint64_t hyperv_features;
1910 bool hyperv_passthrough;
1911 OnOffAuto hyperv_no_nonarch_cs;
1912 uint32_t hyperv_vendor_id[3];
1913 uint32_t hyperv_interface_id[4];
1914 uint32_t hyperv_limits[3];
1915 bool hyperv_enforce_cpuid;
1916 uint32_t hyperv_ver_id_build;
1917 uint16_t hyperv_ver_id_major;
1918 uint16_t hyperv_ver_id_minor;
1919 uint32_t hyperv_ver_id_sp;
1920 uint8_t hyperv_ver_id_sb;
1921 uint32_t hyperv_ver_id_sn;
1922
1923 bool check_cpuid;
1924 bool enforce_cpuid;
1925
1926
1927
1928
1929
1930 bool force_features;
1931 bool expose_kvm;
1932 bool expose_tcg;
1933 bool migratable;
1934 bool migrate_smi_count;
1935 bool max_features;
1936 uint32_t apic_id;
1937
1938
1939
1940 bool vmware_cpuid_freq;
1941
1942
1943 bool cache_info_passthrough;
1944
1945
1946
1947 struct {
1948 uint32_t eax;
1949 uint32_t ebx;
1950 uint32_t ecx;
1951 uint32_t edx;
1952 } mwait;
1953
1954
1955 FeatureWordArray filtered_features;
1956
1957
1958
1959
1960
1961
1962 bool enable_pmu;
1963
1964
1965
1966
1967
1968
1969
1970
1971 uint64_t lbr_fmt;
1972
1973
1974
1975
1976
1977 bool enable_lmce;
1978
1979
1980
1981
1982
1983 bool enable_l3_cache;
1984
1985
1986
1987
1988 bool legacy_cache;
1989
1990
1991 bool enable_cpuid_0xb;
1992
1993
1994 bool full_cpuid_auto_level;
1995
1996
1997 bool vendor_cpuid_only;
1998
1999
2000 bool intel_pt_auto_level;
2001
2002
2003 bool fill_mtrr_mask;
2004
2005
2006 bool host_phys_bits;
2007
2008
2009 uint8_t host_phys_bits_limit;
2010
2011
2012 bool kvm_no_smi_migration;
2013
2014
2015 bool kvm_pv_enforce_cpuid;
2016
2017
2018 uint32_t phys_bits;
2019
2020
2021
2022 struct DeviceState *apic_state;
2023 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
2024 Notifier machine_done;
2025
2026 struct kvm_msrs *kvm_msr_buf;
2027
2028 int32_t node_id;
2029 int32_t socket_id;
2030 int32_t die_id;
2031 int32_t core_id;
2032 int32_t thread_id;
2033
2034 int32_t hv_max_vps;
2035
2036 bool xen_vapic;
2037};
2038
2039
2040#ifndef CONFIG_USER_ONLY
2041extern const VMStateDescription vmstate_x86_cpu;
2042#endif
2043
2044int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
2045
2046int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
2047 int cpuid, DumpState *s);
2048int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
2049 int cpuid, DumpState *s);
2050int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2051 DumpState *s);
2052int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2053 DumpState *s);
2054
2055void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
2056 Error **errp);
2057
2058void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
2059
2060int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
2061int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
2062
2063void x86_cpu_list(void);
2064int cpu_x86_support_mca_broadcast(CPUX86State *env);
2065
2066#ifndef CONFIG_USER_ONLY
2067hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
2068 MemTxAttrs *attrs);
2069int cpu_get_pic_interrupt(CPUX86State *s);
2070
2071
2072void x86_register_ferr_irq(qemu_irq irq);
2073void fpu_check_raise_ferr_irq(CPUX86State *s);
2074void cpu_set_ignne(void);
2075void cpu_clear_ignne(void);
2076#endif
2077
2078
2079void cpu_sync_bndcs_hflags(CPUX86State *env);
2080
2081
2082
2083static inline void cpu_x86_load_seg_cache(CPUX86State *env,
2084 X86Seg seg_reg, unsigned int selector,
2085 target_ulong base,
2086 unsigned int limit,
2087 unsigned int flags)
2088{
2089 SegmentCache *sc;
2090 unsigned int new_hflags;
2091
2092 sc = &env->segs[seg_reg];
2093 sc->selector = selector;
2094 sc->base = base;
2095 sc->limit = limit;
2096 sc->flags = flags;
2097
2098
2099 {
2100 if (seg_reg == R_CS) {
2101#ifdef TARGET_X86_64
2102 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
2103
2104 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2105 env->hflags &= ~(HF_ADDSEG_MASK);
2106 } else
2107#endif
2108 {
2109
2110 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
2111 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
2112 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
2113 new_hflags;
2114 }
2115 }
2116 if (seg_reg == R_SS) {
2117 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
2118#if HF_CPL_MASK != 3
2119#error HF_CPL_MASK is hardcoded
2120#endif
2121 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
2122
2123 cpu_sync_bndcs_hflags(env);
2124 }
2125 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
2126 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
2127 if (env->hflags & HF_CS64_MASK) {
2128
2129 } else if (!(env->cr[0] & CR0_PE_MASK) ||
2130 (env->eflags & VM_MASK) ||
2131 !(env->hflags & HF_CS32_MASK)) {
2132
2133
2134
2135
2136
2137 new_hflags |= HF_ADDSEG_MASK;
2138 } else {
2139 new_hflags |= ((env->segs[R_DS].base |
2140 env->segs[R_ES].base |
2141 env->segs[R_SS].base) != 0) <<
2142 HF_ADDSEG_SHIFT;
2143 }
2144 env->hflags = (env->hflags &
2145 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
2146 }
2147}
2148
2149static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
2150 uint8_t sipi_vector)
2151{
2152 CPUState *cs = CPU(cpu);
2153 CPUX86State *env = &cpu->env;
2154
2155 env->eip = 0;
2156 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
2157 sipi_vector << 12,
2158 env->segs[R_CS].limit,
2159 env->segs[R_CS].flags);
2160 cs->halted = 0;
2161}
2162
2163int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
2164 target_ulong *base, unsigned int *limit,
2165 unsigned int *flags);
2166
2167
2168
2169
2170
2171
2172
2173void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
2174void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
2175void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
2176void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
2177void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
2178void cpu_x86_xsave(CPUX86State *s, target_ulong ptr);
2179void cpu_x86_xrstor(CPUX86State *s, target_ulong ptr);
2180
2181
2182void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
2183 uint32_t vendor2, uint32_t vendor3);
2184typedef struct PropValue {
2185 const char *prop, *value;
2186} PropValue;
2187void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
2188
2189void x86_cpu_after_reset(X86CPU *cpu);
2190
2191uint32_t cpu_x86_virtual_addr_width(CPUX86State *env);
2192
2193
2194void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2195 uint32_t *eax, uint32_t *ebx,
2196 uint32_t *ecx, uint32_t *edx);
2197void cpu_clear_apic_feature(CPUX86State *env);
2198void host_cpuid(uint32_t function, uint32_t count,
2199 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
2200
2201
2202void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
2203void cpu_sync_avx_hflag(CPUX86State *env);
2204
2205#ifndef CONFIG_USER_ONLY
2206static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2207{
2208 return !!attrs.secure;
2209}
2210
2211static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
2212{
2213 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
2214}
2215
2216
2217
2218
2219
2220void cpu_load_efer(CPUX86State *env, uint64_t val);
2221uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
2222uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
2223uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
2224uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
2225void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
2226void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
2227void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
2228void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
2229void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
2230#endif
2231
2232
2233void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
2234void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
2235void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
2236void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
2237
2238
2239uint64_t cpu_get_tsc(CPUX86State *env);
2240
2241#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
2242#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
2243#define CPU_RESOLVING_TYPE TYPE_X86_CPU
2244
2245#ifdef TARGET_X86_64
2246#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2247#else
2248#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2249#endif
2250
2251#define cpu_list x86_cpu_list
2252
2253
2254#define MMU_KSMAP_IDX 0
2255#define MMU_USER_IDX 1
2256#define MMU_KNOSMAP_IDX 2
2257#define MMU_NESTED_IDX 3
2258#define MMU_PHYS_IDX 4
2259
2260static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
2261{
2262 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
2263 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
2264 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2265}
2266
2267static inline int cpu_mmu_index_kernel(CPUX86State *env)
2268{
2269 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
2270 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
2271 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
2272}
2273
2274#define CC_DST (env->cc_dst)
2275#define CC_SRC (env->cc_src)
2276#define CC_SRC2 (env->cc_src2)
2277#define CC_OP (env->cc_op)
2278
2279#include "exec/cpu-all.h"
2280#include "svm.h"
2281
2282#if !defined(CONFIG_USER_ONLY)
2283#include "hw/i386/apic.h"
2284#endif
2285
2286static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
2287 uint64_t *cs_base, uint32_t *flags)
2288{
2289 *cs_base = env->segs[R_CS].base;
2290 *pc = *cs_base + env->eip;
2291 *flags = env->hflags |
2292 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2293}
2294
2295void do_cpu_init(X86CPU *cpu);
2296
2297#define MCE_INJECT_BROADCAST 1
2298#define MCE_INJECT_UNCOND_AO 2
2299
2300void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2301 uint64_t status, uint64_t mcg_status, uint64_t addr,
2302 uint64_t misc, int flags);
2303
2304uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
2305
2306static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2307{
2308 uint32_t eflags = env->eflags;
2309 if (tcg_enabled()) {
2310 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
2311 }
2312 return eflags;
2313}
2314
2315static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2316{
2317 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2318}
2319
2320static inline int32_t x86_get_a20_mask(CPUX86State *env)
2321{
2322 if (env->hflags & HF_SMM_MASK) {
2323 return -1;
2324 } else {
2325 return env->a20_mask;
2326 }
2327}
2328
2329static inline bool cpu_has_vmx(CPUX86State *env)
2330{
2331 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2332}
2333
2334static inline bool cpu_has_svm(CPUX86State *env)
2335{
2336 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2337}
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2356{
2357 return cpu_has_vmx(env) &&
2358 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2359}
2360
2361
2362int get_pg_mode(CPUX86State *env);
2363
2364
2365void update_fp_status(CPUX86State *env);
2366void update_mxcsr_status(CPUX86State *env);
2367void update_mxcsr_from_sse_status(CPUX86State *env);
2368
2369static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2370{
2371 env->mxcsr = mxcsr;
2372 if (tcg_enabled()) {
2373 update_mxcsr_status(env);
2374 }
2375}
2376
2377static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2378{
2379 env->fpuc = fpuc;
2380 if (tcg_enabled()) {
2381 update_fp_status(env);
2382 }
2383}
2384
2385
2386#ifdef CONFIG_USER_ONLY
2387static inline void
2388cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2389 uint64_t param, uintptr_t retaddr)
2390{ }
2391static inline bool
2392cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
2393{ return false; }
2394#else
2395void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2396 uint64_t param, uintptr_t retaddr);
2397bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type);
2398#endif
2399
2400
2401void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2402void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2403 TPRAccess access);
2404
2405
2406
2407
2408#define CPU_VERSION_LATEST -1
2409
2410
2411
2412
2413
2414#define CPU_VERSION_AUTO -2
2415
2416
2417#define CPU_VERSION_LEGACY 0
2418
2419typedef int X86CPUVersion;
2420
2421
2422
2423
2424
2425void x86_cpu_set_default_version(X86CPUVersion version);
2426
2427#ifndef CONFIG_USER_ONLY
2428
2429void do_cpu_sipi(X86CPU *cpu);
2430
2431#define APIC_DEFAULT_ADDRESS 0xfee00000
2432#define APIC_SPACE_SIZE 0x100000
2433
2434
2435void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2436
2437#endif
2438
2439
2440bool cpu_is_bsp(X86CPU *cpu);
2441
2442void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen);
2443void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen);
2444uint32_t xsave_area_size(uint64_t mask, bool compacted);
2445void x86_update_hflags(CPUX86State* env);
2446
2447static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2448{
2449 return !!(cpu->hyperv_features & BIT(feat));
2450}
2451
2452static inline uint64_t cr4_reserved_bits(CPUX86State *env)
2453{
2454 uint64_t reserved_bits = CR4_RESERVED_MASK;
2455 if (!env->features[FEAT_XSAVE]) {
2456 reserved_bits |= CR4_OSXSAVE_MASK;
2457 }
2458 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) {
2459 reserved_bits |= CR4_SMEP_MASK;
2460 }
2461 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
2462 reserved_bits |= CR4_SMAP_MASK;
2463 }
2464 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) {
2465 reserved_bits |= CR4_FSGSBASE_MASK;
2466 }
2467 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
2468 reserved_bits |= CR4_PKE_MASK;
2469 }
2470 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) {
2471 reserved_bits |= CR4_LA57_MASK;
2472 }
2473 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
2474 reserved_bits |= CR4_UMIP_MASK;
2475 }
2476 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
2477 reserved_bits |= CR4_PKS_MASK;
2478 }
2479 return reserved_bits;
2480}
2481
2482static inline bool ctl_has_irq(CPUX86State *env)
2483{
2484 uint32_t int_prio;
2485 uint32_t tpr;
2486
2487 int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
2488 tpr = env->int_ctl & V_TPR_MASK;
2489
2490 if (env->int_ctl & V_IGN_TPR_MASK) {
2491 return (env->int_ctl & V_IRQ_MASK);
2492 }
2493
2494 return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
2495}
2496
2497#if defined(TARGET_X86_64) && \
2498 defined(CONFIG_USER_ONLY) && \
2499 defined(CONFIG_LINUX)
2500# define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2501#endif
2502
2503#endif
2504