LXR qemu/target/ppc/cpu.h

   1/*
   2 *  PowerPC emulation cpu definitions for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef PPC_CPU_H
  21#define PPC_CPU_H
  22
  23#include "qemu/int128.h"
  24#include "qemu/cpu-float.h"
  25#include "exec/cpu-defs.h"
  26#include "cpu-qom.h"
  27#include "qom/object.h"
  28#include "hw/registerfields.h"
  29
  30#define TCG_GUEST_DEFAULT_MO 0
  31
  32#define TARGET_PAGE_BITS_64K 16
  33#define TARGET_PAGE_BITS_16M 24
  34
  35#if defined(TARGET_PPC64)
  36#define PPC_ELF_MACHINE     EM_PPC64
  37#else
  38#define PPC_ELF_MACHINE     EM_PPC
  39#endif
  40
  41#define PPC_BIT_NR(bit)         (63 - (bit))
  42#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
  43#define PPC_BIT32(bit)          (0x80000000 >> (bit))
  44#define PPC_BIT8(bit)           (0x80 >> (bit))
  45#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
  46#define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
  47                                 PPC_BIT32(bs))
  48#define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
  49
  50/*
  51 * QEMU version of the GETFIELD/SETFIELD macros from skiboot
  52 *
  53 * It might be better to use the existing extract64() and
  54 * deposit64() but this means that all the register definitions will
  55 * change and become incompatible with the ones found in skiboot.
  56 */
  57#define MASK_TO_LSH(m)          (__builtin_ffsll(m) - 1)
  58#define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
  59#define SETFIELD(m, v, val) \
  60        (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
  61
  62/*****************************************************************************/
  63/* Exception vectors definitions                                             */
  64enum {
  65    POWERPC_EXCP_NONE    = -1,
  66    /* The 64 first entries are used by the PowerPC embedded specification   */
  67    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
  68    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
  69    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
  70    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
  71    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
  72    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
  73    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
  74    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
  75    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
  76    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
  77    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
  78    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
  79    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
  80    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
  81    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
  82    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
  83    /* Vectors 16 to 31 are reserved                                         */
  84    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
  85    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
  86    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
  87    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
  88    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
  89    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
  90    POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
  91    POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
  92    POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
  93    /* Vectors 42 to 63 are reserved                                         */
  94    /* Exceptions defined in the PowerPC server specification                */
  95    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
  96    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
  97    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
  98    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
  99    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 100    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 101    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 102    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 103    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 104    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 105    /* 40x specific exceptions                                               */
 106    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 107    /* Vectors 75-76 are 601 specific exceptions                             */
 108    /* 602 specific exceptions                                               */
 109    POWERPC_EXCP_EMUL      = 77, /* Emulation trap exception                 */
 110    /* 602/603 specific exceptions                                           */
 111    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 112    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 113    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 114    /* Exceptions available on most PowerPC                                  */
 115    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 116    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 117    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 118    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 119    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 120    /* 7xx/74xx specific exceptions                                          */
 121    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 122    /* 74xx specific exceptions                                              */
 123    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 124    /* 970FX specific exceptions                                             */
 125    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 126    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 127    /* Freescale embedded cores specific exceptions                          */
 128    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 129    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 130    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 131    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 132    /* VSX Unavailable (Power ISA 2.06 and later)                            */
 133    POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 134    POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 135    /* Additional ISA 2.06 and later server exceptions                       */
 136    POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
 137    POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
 138    POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
 139    /* Server doorbell variants */
 140    POWERPC_EXCP_SDOOR    = 99,
 141    POWERPC_EXCP_SDOOR_HV = 100,
 142    /* ISA 3.00 additions */
 143    POWERPC_EXCP_HVIRT    = 101,
 144    POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception                     */
 145    POWERPC_EXCP_PERFM_EBB = 103,    /* Performance Monitor EBB Exception    */
 146    POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception               */
 147    /* EOL                                                                   */
 148    POWERPC_EXCP_NB       = 105,
 149    /* QEMU exceptions: special cases we want to stop translation            */
 150    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 151};
 152
 153/* Exceptions error codes                                                    */
 154enum {
 155    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 156    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 157    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 158    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 159    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 160    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 161    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 162    POWERPC_EXCP_ALIGN_INSN    = 0x07,  /* Pref. insn x-ing 64-byte boundary */
 163    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 164    /* FP exceptions                                                         */
 165    POWERPC_EXCP_FP            = 0x10,
 166    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 167    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 168    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 169    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 170    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 171    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 172    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 173    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 174    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 175    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 176    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 177    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 178    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 179    /* Invalid instruction                                                   */
 180    POWERPC_EXCP_INVAL         = 0x20,
 181    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 182    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 183    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 184    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 185    /* Privileged instruction                                                */
 186    POWERPC_EXCP_PRIV          = 0x30,
 187    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 188    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 189    /* Trap                                                                  */
 190    POWERPC_EXCP_TRAP          = 0x40,
 191};
 192
 193#define PPC_INPUT(env) ((env)->bus_model)
 194
 195/*****************************************************************************/
 196typedef struct opc_handler_t opc_handler_t;
 197
 198/*****************************************************************************/
 199/* Types used to describe some PowerPC registers etc. */
 200typedef struct DisasContext DisasContext;
 201typedef struct ppc_spr_t ppc_spr_t;
 202typedef union ppc_tlb_t ppc_tlb_t;
 203typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
 204
 205/* SPR access micro-ops generations callbacks */
 206struct ppc_spr_t {
 207    const char *name;
 208    target_ulong default_value;
 209#ifndef CONFIG_USER_ONLY
 210    unsigned int gdb_id;
 211#endif
 212#ifdef CONFIG_TCG
 213    void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 214    void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 215# ifndef CONFIG_USER_ONLY
 216    void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 217    void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 218    void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 219    void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 220# endif
 221#endif
 222#ifdef CONFIG_KVM
 223    /*
 224     * We (ab)use the fact that all the SPRs will have ids for the
 225     * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 226     * don't sync this
 227     */
 228    uint64_t one_reg_id;
 229#endif
 230};
 231
 232/* VSX/Altivec registers (128 bits) */
 233typedef union _ppc_vsr_t {
 234    uint8_t u8[16];
 235    uint16_t u16[8];
 236    uint32_t u32[4];
 237    uint64_t u64[2];
 238    int8_t s8[16];
 239    int16_t s16[8];
 240    int32_t s32[4];
 241    int64_t s64[2];
 242    float16 f16[8];
 243    float32 f32[4];
 244    float64 f64[2];
 245    float128 f128;
 246#ifdef CONFIG_INT128
 247    __uint128_t u128;
 248#endif
 249    Int128 s128;
 250} ppc_vsr_t;
 251
 252typedef ppc_vsr_t ppc_avr_t;
 253typedef ppc_vsr_t ppc_fprp_t;
 254typedef ppc_vsr_t ppc_acc_t;
 255
 256#if !defined(CONFIG_USER_ONLY)
 257/* Software TLB cache */
 258typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 259struct ppc6xx_tlb_t {
 260    target_ulong pte0;
 261    target_ulong pte1;
 262    target_ulong EPN;
 263};
 264
 265typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 266struct ppcemb_tlb_t {
 267    uint64_t RPN;
 268    target_ulong EPN;
 269    target_ulong PID;
 270    target_ulong size;
 271    uint32_t prot;
 272    uint32_t attr; /* Storage attributes */
 273};
 274
 275typedef struct ppcmas_tlb_t {
 276     uint32_t mas8;
 277     uint32_t mas1;
 278     uint64_t mas2;
 279     uint64_t mas7_3;
 280} ppcmas_tlb_t;
 281
 282union ppc_tlb_t {
 283    ppc6xx_tlb_t *tlb6;
 284    ppcemb_tlb_t *tlbe;
 285    ppcmas_tlb_t *tlbm;
 286};
 287
 288/* possible TLB variants */
 289#define TLB_NONE               0
 290#define TLB_6XX                1
 291#define TLB_EMB                2
 292#define TLB_MAS                3
 293#endif
 294
 295typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
 296
 297typedef struct ppc_slb_t ppc_slb_t;
 298struct ppc_slb_t {
 299    uint64_t esid;
 300    uint64_t vsid;
 301    const PPCHash64SegmentPageSizes *sps;
 302};
 303
 304#define MAX_SLB_ENTRIES         64
 305#define SEGMENT_SHIFT_256M      28
 306#define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 307
 308#define SEGMENT_SHIFT_1T        40
 309#define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 310
 311typedef struct ppc_v3_pate_t {
 312    uint64_t dw0;
 313    uint64_t dw1;
 314} ppc_v3_pate_t;
 315
 316/* PMU related structs and defines */
 317#define PMU_COUNTERS_NUM 6
 318typedef enum {
 319    PMU_EVENT_INVALID = 0,
 320    PMU_EVENT_INACTIVE,
 321    PMU_EVENT_CYCLES,
 322    PMU_EVENT_INSTRUCTIONS,
 323    PMU_EVENT_INSN_RUN_LATCH,
 324} PMUEventType;
 325
 326/*****************************************************************************/
 327/* Machine state register bits definition                                    */
 328#define MSR_SF   PPC_BIT_NR(0)  /* Sixty-four-bit mode                hflags */
 329#define MSR_TAG  PPC_BIT_NR(1)  /* Tag-active mode (POWERx ?)                */
 330#define MSR_ISF  PPC_BIT_NR(2)  /* Sixty-four-bit interrupt mode on 630      */
 331#define MSR_HV   PPC_BIT_NR(3)  /* hypervisor state                   hflags */
 332#define MSR_TS0  PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s)      */
 333#define MSR_TS1  PPC_BIT_NR(30)
 334#define MSR_TM   PPC_BIT_NR(31) /* Transactional Memory Available (Book3s)   */
 335#define MSR_CM   PPC_BIT_NR(32) /* Computation mode for BookE         hflags */
 336#define MSR_ICM  PPC_BIT_NR(33) /* Interrupt computation mode for BookE      */
 337#define MSR_GS   PPC_BIT_NR(35) /* guest state for BookE                     */
 338#define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE     */
 339#define MSR_VR   PPC_BIT_NR(38) /* altivec available                x hflags */
 340#define MSR_SPE  PPC_BIT_NR(38) /* SPE enable for BookE             x hflags */
 341#define MSR_VSX  PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
 342#define MSR_S    PPC_BIT_NR(41) /* Secure state                              */
 343#define MSR_KEY  PPC_BIT_NR(44) /* key bit on 603e                           */
 344#define MSR_POW  PPC_BIT_NR(45) /* Power management                          */
 345#define MSR_WE   PPC_BIT_NR(45) /* Wait State Enable on 405                  */
 346#define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603            x        */
 347#define MSR_CE   PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x    */
 348#define MSR_ILE  PPC_BIT_NR(47) /* Interrupt little-endian mode              */
 349#define MSR_EE   PPC_BIT_NR(48) /* External interrupt enable                 */
 350#define MSR_PR   PPC_BIT_NR(49) /* Problem state                      hflags */
 351#define MSR_FP   PPC_BIT_NR(50) /* Floating point available           hflags */
 352#define MSR_ME   PPC_BIT_NR(51) /* Machine check interrupt enable            */
 353#define MSR_FE0  PPC_BIT_NR(52) /* Floating point exception mode 0           */
 354#define MSR_SE   PPC_BIT_NR(53) /* Single-step trace enable         x hflags */
 355#define MSR_DWE  PPC_BIT_NR(53) /* Debug wait enable on 405         x        */
 356#define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500     x        */
 357#define MSR_BE   PPC_BIT_NR(54) /* Branch trace enable              x hflags */
 358#define MSR_DE   PPC_BIT_NR(54) /* Debug int. enable on embedded PPC   x     */
 359#define MSR_FE1  PPC_BIT_NR(55) /* Floating point exception mode 1           */
 360#define MSR_AL   PPC_BIT_NR(56) /* AL bit on POWER                           */
 361#define MSR_EP   PPC_BIT_NR(57) /* Exception prefix on 601                   */
 362#define MSR_IR   PPC_BIT_NR(58) /* Instruction relocate                      */
 363#define MSR_IS   PPC_BIT_NR(58) /* Instruction address space (BookE)         */
 364#define MSR_DR   PPC_BIT_NR(59) /* Data relocate                             */
 365#define MSR_DS   PPC_BIT_NR(59) /* Data address space (BookE)                */
 366#define MSR_PE   PPC_BIT_NR(60) /* Protection enable on 403                  */
 367#define MSR_PX   PPC_BIT_NR(61) /* Protection exclusive on 403        x      */
 368#define MSR_PMM  PPC_BIT_NR(61) /* Performance monitor mark on POWER  x      */
 369#define MSR_RI   PPC_BIT_NR(62) /* Recoverable interrupt            1        */
 370#define MSR_LE   PPC_BIT_NR(63) /* Little-endian mode               1 hflags */
 371
 372FIELD(MSR, SF, MSR_SF, 1)
 373FIELD(MSR, TAG, MSR_TAG, 1)
 374FIELD(MSR, ISF, MSR_ISF, 1)
 375#if defined(TARGET_PPC64)
 376FIELD(MSR, HV, MSR_HV, 1)
 377#define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
 378#else
 379#define FIELD_EX64_HV(storage) 0
 380#endif
 381FIELD(MSR, TS0, MSR_TS0, 1)
 382FIELD(MSR, TS1, MSR_TS1, 1)
 383FIELD(MSR, TS, MSR_TS0, 2)
 384FIELD(MSR, TM, MSR_TM, 1)
 385FIELD(MSR, CM, MSR_CM, 1)
 386FIELD(MSR, ICM, MSR_ICM, 1)
 387FIELD(MSR, GS, MSR_GS, 1)
 388FIELD(MSR, UCLE, MSR_UCLE, 1)
 389FIELD(MSR, VR, MSR_VR, 1)
 390FIELD(MSR, SPE, MSR_SPE, 1)
 391FIELD(MSR, VSX, MSR_VSX, 1)
 392FIELD(MSR, S, MSR_S, 1)
 393FIELD(MSR, KEY, MSR_KEY, 1)
 394FIELD(MSR, POW, MSR_POW, 1)
 395FIELD(MSR, WE, MSR_WE, 1)
 396FIELD(MSR, TGPR, MSR_TGPR, 1)
 397FIELD(MSR, CE, MSR_CE, 1)
 398FIELD(MSR, ILE, MSR_ILE, 1)
 399FIELD(MSR, EE, MSR_EE, 1)
 400FIELD(MSR, PR, MSR_PR, 1)
 401FIELD(MSR, FP, MSR_FP, 1)
 402FIELD(MSR, ME, MSR_ME, 1)
 403FIELD(MSR, FE0, MSR_FE0, 1)
 404FIELD(MSR, SE, MSR_SE, 1)
 405FIELD(MSR, DWE, MSR_DWE, 1)
 406FIELD(MSR, UBLE, MSR_UBLE, 1)
 407FIELD(MSR, BE, MSR_BE, 1)
 408FIELD(MSR, DE, MSR_DE, 1)
 409FIELD(MSR, FE1, MSR_FE1, 1)
 410FIELD(MSR, AL, MSR_AL, 1)
 411FIELD(MSR, EP, MSR_EP, 1)
 412FIELD(MSR, IR, MSR_IR, 1)
 413FIELD(MSR, DR, MSR_DR, 1)
 414FIELD(MSR, IS, MSR_IS, 1)
 415FIELD(MSR, DS, MSR_DS, 1)
 416FIELD(MSR, PE, MSR_PE, 1)
 417FIELD(MSR, PX, MSR_PX, 1)
 418FIELD(MSR, PMM, MSR_PMM, 1)
 419FIELD(MSR, RI, MSR_RI, 1)
 420FIELD(MSR, LE, MSR_LE, 1)
 421
 422/*
 423 * FE0 and FE1 bits are not side-by-side
 424 * so we can't combine them using FIELD()
 425 */
 426#define FIELD_EX64_FE(msr) \
 427    ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))
 428
 429/* PMU bits */
 430#define MMCR0_FC     PPC_BIT(32)         /* Freeze Counters  */
 431#define MMCR0_PMAO   PPC_BIT(56)         /* Perf Monitor Alert Ocurred */
 432#define MMCR0_PMAE   PPC_BIT(37)         /* Perf Monitor Alert Enable */
 433#define MMCR0_EBE    PPC_BIT(43)         /* Perf Monitor EBB Enable */
 434#define MMCR0_FCECE  PPC_BIT(38)         /* FC on Enabled Cond or Event */
 435#define MMCR0_PMCC0  PPC_BIT(44)         /* PMC Control bit 0 */
 436#define MMCR0_PMCC1  PPC_BIT(45)         /* PMC Control bit 1 */
 437#define MMCR0_PMCC   PPC_BITMASK(44, 45) /* PMC Control */
 438#define MMCR0_FC14   PPC_BIT(58)         /* PMC Freeze Counters 1-4 bit */
 439#define MMCR0_FC56   PPC_BIT(59)         /* PMC Freeze Counters 5-6 bit */
 440#define MMCR0_PMC1CE PPC_BIT(48)         /* MMCR0 PMC1 Condition Enabled */
 441#define MMCR0_PMCjCE PPC_BIT(49)         /* MMCR0 PMCj Condition Enabled */
 442/* MMCR0 userspace r/w mask */
 443#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
 444/* MMCR2 userspace r/w mask */
 445#define MMCR2_FC1P0  PPC_BIT(1)          /* MMCR2 FCnP0 for PMC1 */
 446#define MMCR2_FC2P0  PPC_BIT(10)         /* MMCR2 FCnP0 for PMC2 */
 447#define MMCR2_FC3P0  PPC_BIT(19)         /* MMCR2 FCnP0 for PMC3 */
 448#define MMCR2_FC4P0  PPC_BIT(28)         /* MMCR2 FCnP0 for PMC4 */
 449#define MMCR2_FC5P0  PPC_BIT(37)         /* MMCR2 FCnP0 for PMC5 */
 450#define MMCR2_FC6P0  PPC_BIT(46)         /* MMCR2 FCnP0 for PMC6 */
 451#define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
 452                         MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
 453
 454#define MMCR1_EVT_SIZE 8
 455/* extract64() does a right shift before extracting */
 456#define MMCR1_PMC1SEL_START 32
 457#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
 458#define MMCR1_PMC2SEL_START 40
 459#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
 460#define MMCR1_PMC3SEL_START 48
 461#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
 462#define MMCR1_PMC4SEL_START 56
 463#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
 464
 465/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
 466#define CTRL_RUN PPC_BIT(63)
 467
 468/* EBB/BESCR bits */
 469/* Global Enable */
 470#define BESCR_GE PPC_BIT(0)
 471/* External Event-based Exception Enable */
 472#define BESCR_EE PPC_BIT(30)
 473/* Performance Monitor Event-based Exception Enable */
 474#define BESCR_PME PPC_BIT(31)
 475/* External Event-based Exception Occurred */
 476#define BESCR_EEO PPC_BIT(62)
 477/* Performance Monitor Event-based Exception Occurred */
 478#define BESCR_PMEO PPC_BIT(63)
 479#define BESCR_INVALID PPC_BITMASK(32, 33)
 480
 481/* LPCR bits */
 482#define LPCR_VPM0         PPC_BIT(0)
 483#define LPCR_VPM1         PPC_BIT(1)
 484#define LPCR_ISL          PPC_BIT(2)
 485#define LPCR_KBV          PPC_BIT(3)
 486#define LPCR_DPFD_SHIFT   (63 - 11)
 487#define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 488#define LPCR_VRMASD_SHIFT (63 - 16)
 489#define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 490/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
 491#define LPCR_PECE_U_SHIFT (63 - 19)
 492#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
 493#define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
 494#define LPCR_RMLS_SHIFT   (63 - 37)   /* RMLS (removed in ISA v3.0) */
 495#define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 496#define LPCR_HAIL         PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
 497#define LPCR_ILE          PPC_BIT(38)
 498#define LPCR_AIL_SHIFT    (63 - 40)   /* Alternate interrupt location */
 499#define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 500#define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
 501#define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
 502#define LPCR_HR           PPC_BIT(43) /* Host Radix */
 503#define LPCR_ONL          PPC_BIT(45)
 504#define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
 505#define LPCR_P7_PECE0     PPC_BIT(49)
 506#define LPCR_P7_PECE1     PPC_BIT(50)
 507#define LPCR_P7_PECE2     PPC_BIT(51)
 508#define LPCR_P8_PECE0     PPC_BIT(47)
 509#define LPCR_P8_PECE1     PPC_BIT(48)
 510#define LPCR_P8_PECE2     PPC_BIT(49)
 511#define LPCR_P8_PECE3     PPC_BIT(50)
 512#define LPCR_P8_PECE4     PPC_BIT(51)
 513/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
 514#define LPCR_PECE_L_SHIFT (63 - 51)
 515#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
 516#define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
 517#define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
 518#define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
 519#define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
 520#define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
 521#define LPCR_MER          PPC_BIT(52)
 522#define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
 523#define LPCR_TC           PPC_BIT(54)
 524#define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
 525#define LPCR_LPES0        PPC_BIT(60)
 526#define LPCR_LPES1        PPC_BIT(61)
 527#define LPCR_RMI          PPC_BIT(62)
 528#define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
 529#define LPCR_HDICE        PPC_BIT(63)
 530
 531/* PSSCR bits */
 532#define PSSCR_ESL         PPC_BIT(42) /* Enable State Loss */
 533#define PSSCR_EC          PPC_BIT(43) /* Exit Criterion */
 534
 535/* HFSCR bits */
 536#define HFSCR_MSGP     PPC_BIT(53) /* Privileged Message Send Facilities */
 537#define HFSCR_IC_MSGP  0xA
 538
 539#define DBCR0_ICMP (1 << 27)
 540#define DBCR0_BRT (1 << 26)
 541#define DBSR_ICMP (1 << 27)
 542#define DBSR_BRT (1 << 26)
 543
 544/* Hypervisor bit is more specific */
 545#if defined(TARGET_PPC64)
 546#define MSR_HVB (1ULL << MSR_HV)
 547#else
 548#define MSR_HVB (0ULL)
 549#endif
 550
 551/* DSISR */
 552#define DSISR_NOPTE              0x40000000
 553/* Not permitted by access authority of encoded access authority */
 554#define DSISR_PROTFAULT          0x08000000
 555#define DSISR_ISSTORE            0x02000000
 556/* Not permitted by virtual page class key protection */
 557#define DSISR_AMR                0x00200000
 558/* Unsupported Radix Tree Configuration */
 559#define DSISR_R_BADCONFIG        0x00080000
 560#define DSISR_ATOMIC_RC          0x00040000
 561/* Unable to translate address of (guest) pde or process/page table entry */
 562#define DSISR_PRTABLE_FAULT      0x00020000
 563
 564/* SRR1 error code fields */
 565
 566#define SRR1_NOPTE               DSISR_NOPTE
 567/* Not permitted due to no-execute or guard bit set */
 568#define SRR1_NOEXEC_GUARD        0x10000000
 569#define SRR1_PROTFAULT           DSISR_PROTFAULT
 570#define SRR1_IAMR                DSISR_AMR
 571
 572/* SRR1[42:45] wakeup fields for System Reset Interrupt */
 573
 574#define SRR1_WAKEMASK           0x003c0000 /* reason for wakeup */
 575
 576#define SRR1_WAKEHMI            0x00280000 /* Hypervisor maintenance */
 577#define SRR1_WAKEHVI            0x00240000 /* Hypervisor Virt. Interrupt (P9) */
 578#define SRR1_WAKEEE             0x00200000 /* External interrupt */
 579#define SRR1_WAKEDEC            0x00180000 /* Decrementer interrupt */
 580#define SRR1_WAKEDBELL          0x00140000 /* Privileged doorbell */
 581#define SRR1_WAKERESET          0x00100000 /* System reset */
 582#define SRR1_WAKEHDBELL         0x000c0000 /* Hypervisor doorbell */
 583#define SRR1_WAKESCOM           0x00080000 /* SCOM not in power-saving mode */
 584
 585/* SRR1[46:47] power-saving exit mode */
 586
 587#define SRR1_WAKESTATE          0x00030000 /* Powersave exit mask */
 588
 589#define SRR1_WS_HVLOSS          0x00030000 /* HV resources not maintained */
 590#define SRR1_WS_GPRLOSS         0x00020000 /* GPRs not maintained */
 591#define SRR1_WS_NOLOSS          0x00010000 /* All resources maintained */
 592
 593/* Facility Status and Control (FSCR) bits */
 594#define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 595#define FSCR_TAR        (63 - 55) /* Target Address Register */
 596#define FSCR_SCV        (63 - 51) /* System call vectored */
 597/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 598#define FSCR_IC_MASK    (0xFFULL)
 599#define FSCR_IC_POS     (63 - 7)
 600#define FSCR_IC_DSCR_SPR3   2
 601#define FSCR_IC_PMU         3
 602#define FSCR_IC_BHRB        4
 603#define FSCR_IC_TM          5
 604#define FSCR_IC_EBB         7
 605#define FSCR_IC_TAR         8
 606#define FSCR_IC_SCV        12
 607
 608/* Exception state register bits definition                                  */
 609#define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
 610#define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
 611#define ESR_PTR   PPC_BIT(38) /* Trap                                   */
 612#define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
 613#define ESR_ST    PPC_BIT(40) /* Store Operation                        */
 614#define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
 615#define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
 616#define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
 617#define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
 618#define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
 619#define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
 620#define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
 621#define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
 622#define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
 623#define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
 624#define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
 625
 626/* Transaction EXception And Summary Register bits                           */
 627#define TEXASR_FAILURE_PERSISTENT                (63 - 7)
 628#define TEXASR_DISALLOWED                        (63 - 8)
 629#define TEXASR_NESTING_OVERFLOW                  (63 - 9)
 630#define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
 631#define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
 632#define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
 633#define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
 634#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
 635#define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
 636#define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
 637#define TEXASR_ABORT                             (63 - 31)
 638#define TEXASR_SUSPENDED                         (63 - 32)
 639#define TEXASR_PRIVILEGE_HV                      (63 - 34)
 640#define TEXASR_PRIVILEGE_PR                      (63 - 35)
 641#define TEXASR_FAILURE_SUMMARY                   (63 - 36)
 642#define TEXASR_TFIAR_EXACT                       (63 - 37)
 643#define TEXASR_ROT                               (63 - 38)
 644#define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
 645
 646enum {
 647    POWERPC_FLAG_NONE     = 0x00000000,
 648    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 649    POWERPC_FLAG_SPE      = 0x00000001,
 650    POWERPC_FLAG_VRE      = 0x00000002,
 651    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 652    POWERPC_FLAG_TGPR     = 0x00000004,
 653    POWERPC_FLAG_CE       = 0x00000008,
 654    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 655    POWERPC_FLAG_SE       = 0x00000010,
 656    POWERPC_FLAG_DWE      = 0x00000020,
 657    POWERPC_FLAG_UBLE     = 0x00000040,
 658    /* Flag for MSR bit 9 signification (BE/DE)                              */
 659    POWERPC_FLAG_BE       = 0x00000080,
 660    POWERPC_FLAG_DE       = 0x00000100,
 661    /* Flag for MSR bit 2 signification (PX/PMM)                             */
 662    POWERPC_FLAG_PX       = 0x00000200,
 663    POWERPC_FLAG_PMM      = 0x00000400,
 664    /* Flag for special features                                             */
 665    /* Decrementer clock                                                     */
 666    POWERPC_FLAG_BUS_CLK  = 0x00020000,
 667    /* Has CFAR                                                              */
 668    POWERPC_FLAG_CFAR     = 0x00040000,
 669    /* Has VSX                                                               */
 670    POWERPC_FLAG_VSX      = 0x00080000,
 671    /* Has Transaction Memory (ISA 2.07)                                     */
 672    POWERPC_FLAG_TM       = 0x00100000,
 673    /* Has SCV (ISA 3.00)                                                    */
 674    POWERPC_FLAG_SCV      = 0x00200000,
 675    /* Has >1 thread per core                                                */
 676    POWERPC_FLAG_SMT      = 0x00400000,
 677    /* Using "LPAR per core" mode  (as opposed to per-thread)                */
 678    POWERPC_FLAG_SMT_1LPAR = 0x00800000,
 679};
 680
 681/*
 682 * Bits for env->hflags.
 683 *
 684 * Most of these bits overlap with corresponding bits in MSR,
 685 * but some come from other sources.  Those that do come from
 686 * the MSR are validated in hreg_compute_hflags.
 687 */
 688enum {
 689    HFLAGS_LE = 0,   /* MSR_LE */
 690    HFLAGS_HV = 1,   /* computed from MSR_HV and other state */
 691    HFLAGS_64 = 2,   /* computed from MSR_CE and MSR_SF */
 692    HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
 693    HFLAGS_DR = 4,   /* MSR_DR */
 694    HFLAGS_HR = 5,   /* computed from SPR_LPCR[HR] */
 695    HFLAGS_SPE = 6,  /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
 696    HFLAGS_TM = 8,   /* computed from MSR_TM */
 697    HFLAGS_BE = 9,   /* MSR_BE -- from elsewhere on embedded ppc */
 698    HFLAGS_SE = 10,  /* MSR_SE -- from elsewhere on embedded ppc */
 699    HFLAGS_FP = 13,  /* MSR_FP */
 700    HFLAGS_PR = 14,  /* MSR_PR */
 701    HFLAGS_PMCC0 = 15,  /* MMCR0 PMCC bit 0 */
 702    HFLAGS_PMCC1 = 16,  /* MMCR0 PMCC bit 1 */
 703    HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
 704    HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
 705    HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
 706    HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
 707    HFLAGS_VR = 25,  /* MSR_VR if cpu has VRE */
 708
 709    HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
 710    HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
 711};
 712
 713/*****************************************************************************/
 714/* Floating point status and control register                                */
 715#define FPSCR_DRN2   PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl. */
 716#define FPSCR_DRN1   PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl. */
 717#define FPSCR_DRN0   PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl. */
 718#define FPSCR_FX     PPC_BIT_NR(32) /* Floating-point exception summary      */
 719#define FPSCR_FEX    PPC_BIT_NR(33) /* Floating-point enabled exception summ.*/
 720#define FPSCR_VX     PPC_BIT_NR(34) /* Floating-point invalid op. excp. summ.*/
 721#define FPSCR_OX     PPC_BIT_NR(35) /* Floating-point overflow exception     */
 722#define FPSCR_UX     PPC_BIT_NR(36) /* Floating-point underflow exception    */
 723#define FPSCR_ZX     PPC_BIT_NR(37) /* Floating-point zero divide exception  */
 724#define FPSCR_XX     PPC_BIT_NR(38) /* Floating-point inexact exception      */
 725#define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (sNan)*/
 726#define FPSCR_VXISI  PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf) */
 727#define FPSCR_VXIDI  PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf) */
 728#define FPSCR_VXZDZ  PPC_BIT_NR(42) /* Floating-point invalid op. excp (zero)*/
 729#define FPSCR_VXIMZ  PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf) */
 730#define FPSCR_VXVC   PPC_BIT_NR(44) /* Floating-point invalid op. excp (comp)*/
 731#define FPSCR_FR     PPC_BIT_NR(45) /* Floating-point fraction rounded       */
 732#define FPSCR_FI     PPC_BIT_NR(46) /* Floating-point fraction inexact       */
 733#define FPSCR_C      PPC_BIT_NR(47) /* Floating-point result class descriptor*/
 734#define FPSCR_FL     PPC_BIT_NR(48) /* Floating-point less than or negative  */
 735#define FPSCR_FG     PPC_BIT_NR(49) /* Floating-point greater than or neg.   */
 736#define FPSCR_FE     PPC_BIT_NR(50) /* Floating-point equal or zero          */
 737#define FPSCR_FU     PPC_BIT_NR(51) /* Floating-point unordered or NaN       */
 738#define FPSCR_FPCC   PPC_BIT_NR(51) /* Floating-point condition code         */
 739#define FPSCR_FPRF   PPC_BIT_NR(51) /* Floating-point result flags           */
 740#define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (soft)*/
 741#define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (sqrt)*/
 742#define FPSCR_VXCVI  PPC_BIT_NR(55) /* Floating-point invalid op. excp (int) */
 743#define FPSCR_VE     PPC_BIT_NR(56) /* Floating-point invalid op. excp enable*/
 744#define FPSCR_OE     PPC_BIT_NR(57) /* Floating-point overflow excp. enable  */
 745#define FPSCR_UE     PPC_BIT_NR(58) /* Floating-point underflow excp. enable */
 746#define FPSCR_ZE     PPC_BIT_NR(59) /* Floating-point zero divide excp enable*/
 747#define FPSCR_XE     PPC_BIT_NR(60) /* Floating-point inexact excp. enable   */
 748#define FPSCR_NI     PPC_BIT_NR(61) /* Floating-point non-IEEE mode          */
 749#define FPSCR_RN1    PPC_BIT_NR(62)
 750#define FPSCR_RN0    PPC_BIT_NR(63) /* Floating-point rounding control       */
 751/* Invalid operation exception summary */
 752#define FPSCR_IX     ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 753                      (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 754                      (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 755                      (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 756                      (1 << FPSCR_VXCVI))
 757
 758FIELD(FPSCR, FI, FPSCR_FI, 1)
 759
 760#define FP_DRN2         (1ull << FPSCR_DRN2)
 761#define FP_DRN1         (1ull << FPSCR_DRN1)
 762#define FP_DRN0         (1ull << FPSCR_DRN0)
 763#define FP_DRN          (FP_DRN2 | FP_DRN1 | FP_DRN0)
 764#define FP_FX           (1ull << FPSCR_FX)
 765#define FP_FEX          (1ull << FPSCR_FEX)
 766#define FP_VX           (1ull << FPSCR_VX)
 767#define FP_OX           (1ull << FPSCR_OX)
 768#define FP_UX           (1ull << FPSCR_UX)
 769#define FP_ZX           (1ull << FPSCR_ZX)
 770#define FP_XX           (1ull << FPSCR_XX)
 771#define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
 772#define FP_VXISI        (1ull << FPSCR_VXISI)
 773#define FP_VXIDI        (1ull << FPSCR_VXIDI)
 774#define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
 775#define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
 776#define FP_VXVC         (1ull << FPSCR_VXVC)
 777#define FP_FR           (1ull << FPSCR_FR)
 778#define FP_FI           (1ull << FPSCR_FI)
 779#define FP_C            (1ull << FPSCR_C)
 780#define FP_FL           (1ull << FPSCR_FL)
 781#define FP_FG           (1ull << FPSCR_FG)
 782#define FP_FE           (1ull << FPSCR_FE)
 783#define FP_FU           (1ull << FPSCR_FU)
 784#define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
 785#define FP_FPRF         (FP_C | FP_FPCC)
 786#define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
 787#define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
 788#define FP_VXCVI        (1ull << FPSCR_VXCVI)
 789#define FP_VE           (1ull << FPSCR_VE)
 790#define FP_OE           (1ull << FPSCR_OE)
 791#define FP_UE           (1ull << FPSCR_UE)
 792#define FP_ZE           (1ull << FPSCR_ZE)
 793#define FP_XE           (1ull << FPSCR_XE)
 794#define FP_NI           (1ull << FPSCR_NI)
 795#define FP_RN1          (1ull << FPSCR_RN1)
 796#define FP_RN0          (1ull << FPSCR_RN0)
 797#define FP_RN           (FP_RN1 | FP_RN0)
 798
 799#define FP_ENABLES      (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
 800#define FP_STATUS       (FP_FR | FP_FI | FP_FPRF)
 801
 802/* the exception bits which can be cleared by mcrfs - includes FX */
 803#define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
 804                          FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
 805                          FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
 806                          FP_VXSQRT | FP_VXCVI)
 807
 808/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
 809#define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) |        \
 810                           FP_FEX | FP_VX | PPC_BIT(52)))
 811
 812/*****************************************************************************/
 813/* Vector status and control register */
 814#define VSCR_NJ         16 /* Vector non-java */
 815#define VSCR_SAT        0 /* Vector saturation */
 816
 817/*****************************************************************************/
 818/* BookE e500 MMU registers */
 819
 820#define MAS0_NV_SHIFT      0
 821#define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 822
 823#define MAS0_WQ_SHIFT      12
 824#define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 825/* Write TLB entry regardless of reservation */
 826#define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 827/* Write TLB entry only already in use */
 828#define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 829/* Clear TLB entry */
 830#define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 831
 832#define MAS0_HES_SHIFT     14
 833#define MAS0_HES           (1 << MAS0_HES_SHIFT)
 834
 835#define MAS0_ESEL_SHIFT    16
 836#define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 837
 838#define MAS0_TLBSEL_SHIFT  28
 839#define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 840#define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 841#define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 842#define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 843#define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 844
 845#define MAS0_ATSEL_SHIFT   31
 846#define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 847#define MAS0_ATSEL_TLB     0
 848#define MAS0_ATSEL_LRAT    MAS0_ATSEL
 849
 850#define MAS1_TSIZE_SHIFT   7
 851#define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 852
 853#define MAS1_TS_SHIFT      12
 854#define MAS1_TS            (1 << MAS1_TS_SHIFT)
 855
 856#define MAS1_IND_SHIFT     13
 857#define MAS1_IND           (1 << MAS1_IND_SHIFT)
 858
 859#define MAS1_TID_SHIFT     16
 860#define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 861
 862#define MAS1_IPROT_SHIFT   30
 863#define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 864
 865#define MAS1_VALID_SHIFT   31
 866#define MAS1_VALID         0x80000000
 867
 868#define MAS2_EPN_SHIFT     12
 869#define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 870
 871#define MAS2_ACM_SHIFT     6
 872#define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 873
 874#define MAS2_VLE_SHIFT     5
 875#define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 876
 877#define MAS2_W_SHIFT       4
 878#define MAS2_W             (1 << MAS2_W_SHIFT)
 879
 880#define MAS2_I_SHIFT       3
 881#define MAS2_I             (1 << MAS2_I_SHIFT)
 882
 883#define MAS2_M_SHIFT       2
 884#define MAS2_M             (1 << MAS2_M_SHIFT)
 885
 886#define MAS2_G_SHIFT       1
 887#define MAS2_G             (1 << MAS2_G_SHIFT)
 888
 889#define MAS2_E_SHIFT       0
 890#define MAS2_E             (1 << MAS2_E_SHIFT)
 891
 892#define MAS3_RPN_SHIFT     12
 893#define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 894
 895#define MAS3_U0                 0x00000200
 896#define MAS3_U1                 0x00000100
 897#define MAS3_U2                 0x00000080
 898#define MAS3_U3                 0x00000040
 899#define MAS3_UX                 0x00000020
 900#define MAS3_SX                 0x00000010
 901#define MAS3_UW                 0x00000008
 902#define MAS3_SW                 0x00000004
 903#define MAS3_UR                 0x00000002
 904#define MAS3_SR                 0x00000001
 905#define MAS3_SPSIZE_SHIFT       1
 906#define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 907
 908#define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 909#define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 910#define MAS4_TIDSELD_MASK       0x00030000
 911#define MAS4_TIDSELD_PID0       0x00000000
 912#define MAS4_TIDSELD_PID1       0x00010000
 913#define MAS4_TIDSELD_PID2       0x00020000
 914#define MAS4_TIDSELD_PIDZ       0x00030000
 915#define MAS4_INDD               0x00008000      /* Default IND */
 916#define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 917#define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 918#define MAS4_ACMD               0x00000040
 919#define MAS4_VLED               0x00000020
 920#define MAS4_WD                 0x00000010
 921#define MAS4_ID                 0x00000008
 922#define MAS4_MD                 0x00000004
 923#define MAS4_GD                 0x00000002
 924#define MAS4_ED                 0x00000001
 925#define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 926#define MAS4_WIMGED_SHIFT       0
 927
 928#define MAS5_SGS                0x80000000
 929#define MAS5_SLPID_MASK         0x00000fff
 930
 931#define MAS6_SPID0              0x3fff0000
 932#define MAS6_SPID1              0x00007ffe
 933#define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 934#define MAS6_SAS                0x00000001
 935#define MAS6_SPID               MAS6_SPID0
 936#define MAS6_SIND               0x00000002      /* Indirect page */
 937#define MAS6_SIND_SHIFT         1
 938#define MAS6_SPID_MASK          0x3fff0000
 939#define MAS6_SPID_SHIFT         16
 940#define MAS6_ISIZE_MASK         0x00000f80
 941#define MAS6_ISIZE_SHIFT        7
 942
 943#define MAS7_RPN                0xffffffff
 944
 945#define MAS8_TGS                0x80000000
 946#define MAS8_VF                 0x40000000
 947#define MAS8_TLBPID             0x00000fff
 948
 949/* Bit definitions for MMUCFG */
 950#define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 951#define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 952#define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 953#define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 954#define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 955#define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 956#define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 957#define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 958#define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 959
 960/* Bit definitions for MMUCSR0 */
 961#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 962#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 963#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 964#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 965#define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 966                         MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 967#define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 968#define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 969#define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 970#define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 971
 972/* TLBnCFG encoding */
 973#define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 974#define TLBnCFG_HES             0x00002000      /* HW select supported */
 975#define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 976#define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 977#define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 978#define TLBnCFG_IND             0x00020000      /* IND entries supported */
 979#define TLBnCFG_PT              0x00040000      /* Can load from page table */
 980#define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 981#define TLBnCFG_MINSIZE_SHIFT   20
 982#define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 983#define TLBnCFG_MAXSIZE_SHIFT   16
 984#define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 985#define TLBnCFG_ASSOC_SHIFT     24
 986
 987/* TLBnPS encoding */
 988#define TLBnPS_4K               0x00000004
 989#define TLBnPS_8K               0x00000008
 990#define TLBnPS_16K              0x00000010
 991#define TLBnPS_32K              0x00000020
 992#define TLBnPS_64K              0x00000040
 993#define TLBnPS_128K             0x00000080
 994#define TLBnPS_256K             0x00000100
 995#define TLBnPS_512K             0x00000200
 996#define TLBnPS_1M               0x00000400
 997#define TLBnPS_2M               0x00000800
 998#define TLBnPS_4M               0x00001000
 999#define TLBnPS_8M               0x00002000
1000#define TLBnPS_16M              0x00004000

1001#define TLBnPS_32M              0x00008000
1002#define TLBnPS_64M              0x00010000
1003#define TLBnPS_128M             0x00020000
1004#define TLBnPS_256M             0x00040000
1005#define TLBnPS_512M             0x00080000
1006#define TLBnPS_1G               0x00100000
1007#define TLBnPS_2G               0x00200000
1008#define TLBnPS_4G               0x00400000
1009#define TLBnPS_8G               0x00800000
1010#define TLBnPS_16G              0x01000000
1011#define TLBnPS_32G              0x02000000
1012#define TLBnPS_64G              0x04000000
1013#define TLBnPS_128G             0x08000000
1014#define TLBnPS_256G             0x10000000
1015
1016/* tlbilx action encoding */
1017#define TLBILX_T_ALL                    0
1018#define TLBILX_T_TID                    1
1019#define TLBILX_T_FULLMATCH              3
1020#define TLBILX_T_CLASS0                 4
1021#define TLBILX_T_CLASS1                 5
1022#define TLBILX_T_CLASS2                 6
1023#define TLBILX_T_CLASS3                 7
1024
1025/* BookE 2.06 helper defines */
1026
1027#define BOOKE206_FLUSH_TLB0    (1 << 0)
1028#define BOOKE206_FLUSH_TLB1    (1 << 1)
1029#define BOOKE206_FLUSH_TLB2    (1 << 2)
1030#define BOOKE206_FLUSH_TLB3    (1 << 3)
1031
1032/* number of possible TLBs */
1033#define BOOKE206_MAX_TLBN      4
1034
1035#define EPID_EPID_SHIFT 0x0
1036#define EPID_EPID 0xFF
1037#define EPID_ELPID_SHIFT 0x10
1038#define EPID_ELPID 0x3F0000
1039#define EPID_EGS 0x20000000
1040#define EPID_EGS_SHIFT 29
1041#define EPID_EAS 0x40000000
1042#define EPID_EAS_SHIFT 30
1043#define EPID_EPR 0x80000000
1044#define EPID_EPR_SHIFT 31
1045/* We don't support EGS and ELPID */
1046#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
1047
1048/*****************************************************************************/
1049/* Server and Embedded Processor Control */
1050
1051#define DBELL_TYPE_SHIFT               27
1052#define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
1053#define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
1054#define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
1055#define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
1056#define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
1057#define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
1058
1059#define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
1060
1061#define DBELL_BRDCAST                  PPC_BIT(37)
1062#define DBELL_LPIDTAG_SHIFT            14
1063#define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
1064#define DBELL_PIRTAG_MASK              0x3fff
1065
1066#define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
1067
1068#define PPC_PAGE_SIZES_MAX_SZ   8
1069
1070struct ppc_radix_page_info {
1071    uint32_t count;
1072    uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1073};
1074
1075/*****************************************************************************/
1076/* Dynamic Execution Control Register */
1077
1078#define DEXCR_ASPECT(name, num)                    \
1079FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1)       \
1080FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1)  \
1081FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1)      \
1082FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \
1083
1084DEXCR_ASPECT(SBHE, 0)
1085DEXCR_ASPECT(IBRTPD, 1)
1086DEXCR_ASPECT(SRAPD, 4)
1087DEXCR_ASPECT(NPHIE, 5)
1088DEXCR_ASPECT(PHIE, 6)
1089
1090/*****************************************************************************/
1091/* The whole PowerPC CPU context */
1092
1093/*
1094 * PowerPC needs eight modes for different hypervisor/supervisor/guest
1095 * + real/paged mode combinations. The other two modes are for
1096 * external PID load/store.
1097 */
1098#define PPC_TLB_EPID_LOAD 8
1099#define PPC_TLB_EPID_STORE 9
1100
1101#define PPC_CPU_OPCODES_LEN          0x40
1102#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1103
1104struct CPUArchState {
1105    /* Most commonly used resources during translated code execution first */
1106    target_ulong gpr[32];  /* general purpose registers */
1107    target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1108    target_ulong lr;
1109    target_ulong ctr;
1110    uint32_t crf[8];       /* condition register */
1111#if defined(TARGET_PPC64)
1112    target_ulong cfar;
1113#endif
1114    target_ulong xer;      /* XER (with SO, OV, CA split out) */
1115    target_ulong so;
1116    target_ulong ov;
1117    target_ulong ca;
1118    target_ulong ov32;
1119    target_ulong ca32;
1120
1121    target_ulong reserve_addr;   /* Reservation address */
1122    target_ulong reserve_length; /* Reservation larx op size (bytes) */
1123    target_ulong reserve_val;    /* Reservation value */
1124    target_ulong reserve_val2;
1125
1126    /* These are used in supervisor mode only */
1127    target_ulong msr;      /* machine state register */
1128    target_ulong tgpr[4];  /* temporary general purpose registers, */
1129                           /* used to speed-up TLB assist handlers */
1130
1131    target_ulong nip;      /* next instruction pointer */
1132
1133    /* when a memory exception occurs, the access type is stored here */
1134    int access_type;
1135
1136#if !defined(CONFIG_USER_ONLY)
1137    /* MMU context, only relevant for full system emulation */
1138#if defined(TARGET_PPC64)
1139    ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1140#endif
1141    target_ulong sr[32];   /* segment registers */
1142    uint32_t nb_BATs;      /* number of BATs */
1143    target_ulong DBAT[2][8];
1144    target_ulong IBAT[2][8];
1145    /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1146    int32_t nb_tlb;  /* Total number of TLB */
1147    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1148    int nb_ways;     /* Number of ways in the TLB set */
1149    int last_way;    /* Last used way used to allocate TLB in a LRU way */
1150    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1151    int nb_pids;     /* Number of available PID registers */
1152    int tlb_type;    /* Type of TLB we're dealing with */
1153    ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed */
1154#ifdef CONFIG_KVM
1155    bool tlb_dirty;  /* Set to non-zero when modifying TLB */
1156    bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1157#endif /* CONFIG_KVM */
1158    uint32_t tlb_need_flush; /* Delayed flush needed */
1159#define TLB_NEED_LOCAL_FLUSH   0x1
1160#define TLB_NEED_GLOBAL_FLUSH  0x2
1161#endif
1162
1163    /* Other registers */
1164    target_ulong spr[1024]; /* special purpose registers */
1165    ppc_spr_t spr_cb[1024];
1166    /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1167    uint8_t pmc_ins_cnt;
1168    uint8_t pmc_cyc_cnt;
1169    /* Vector status and control register, minus VSCR_SAT */
1170    uint32_t vscr;
1171    /* VSX registers (including FP and AVR) */
1172    ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1173    /* Non-zero if and only if VSCR_SAT should be set */
1174    ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1175    /* SPE registers */
1176    uint64_t spe_acc;
1177    uint32_t spe_fscr;
1178    /* SPE and Altivec share status as they'll never be used simultaneously */
1179    float_status vec_status;
1180    float_status fp_status; /* Floating point execution context */
1181    target_ulong fpscr;     /* Floating point status and control register */
1182
1183    /* Internal devices resources */
1184    ppc_tb_t *tb_env;      /* Time base and decrementer */
1185    ppc_dcr_t *dcr_env;    /* Device control registers */
1186
1187    int dcache_line_size;
1188    int icache_line_size;
1189
1190    /* These resources are used during exception processing */
1191    /* CPU model definition */
1192    target_ulong msr_mask;
1193    powerpc_mmu_t mmu_model;
1194    powerpc_excp_t excp_model;
1195    powerpc_input_t bus_model;
1196    int bfd_mach;
1197    uint32_t flags;
1198    uint64_t insns_flags;
1199    uint64_t insns_flags2;
1200
1201    int error_code;
1202    uint32_t pending_interrupts;
1203#if !defined(CONFIG_USER_ONLY)
1204    uint64_t excp_stats[POWERPC_EXCP_NB];
1205    /*
1206     * This is the IRQ controller, which is implementation dependent and only
1207     * relevant when emulating a complete machine. Note that this isn't used
1208     * by recent Book3s compatible CPUs (POWER7 and newer).
1209     */
1210    uint32_t irq_input_state;
1211
1212    target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1213    target_ulong excp_prefix;
1214    target_ulong ivor_mask;
1215    target_ulong ivpr_mask;
1216    target_ulong hreset_vector;
1217    hwaddr mpic_iack;
1218    bool mpic_proxy;  /* true if the external proxy facility mode is enabled */
1219    bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1220                      /* instructions and SPRs are diallowed if MSR:HV is 0 */
1221    /*
1222     * On P7/P8/P9, set when in PM state so we need to handle resume in a
1223     * special way (such as routing some resume causes to 0x100, i.e. sreset).
1224     */
1225    bool resume_as_sreset;
1226#endif
1227
1228    /* These resources are used only in TCG */
1229    uint32_t hflags;
1230    target_ulong hflags_compat_nmsr; /* for migration compatibility */
1231
1232    /* Power management */
1233    int (*check_pow)(CPUPPCState *env);
1234
1235#if !defined(CONFIG_USER_ONLY)
1236    void *load_info;  /* holds boot loading state */
1237#endif
1238
1239    /* booke timers */
1240
1241    /*
1242     * Specifies bit locations of the Time Base used to signal a fixed timer
1243     * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1244     *
1245     * 0 selects the least significant bit, 63 selects the most significant bit
1246     */
1247    uint8_t fit_period[4];
1248    uint8_t wdt_period[4];
1249
1250    /* Transactional memory state */
1251    target_ulong tm_gpr[32];
1252    ppc_avr_t tm_vsr[64];
1253    uint64_t tm_cr;
1254    uint64_t tm_lr;
1255    uint64_t tm_ctr;
1256    uint64_t tm_fpscr;
1257    uint64_t tm_amr;
1258    uint64_t tm_ppr;
1259    uint64_t tm_vrsave;
1260    uint32_t tm_vscr;
1261    uint64_t tm_dscr;
1262    uint64_t tm_tar;
1263
1264    /*
1265     * Timers used to fire performance monitor alerts
1266     * when counting cycles.
1267     */
1268    QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1269
1270    /*
1271     * PMU base time value used by the PMU to calculate
1272     * running cycles.
1273     */
1274    uint64_t pmu_base_time;
1275};
1276
1277#define _CORE_ID(cs)                                            \
1278    (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1))
1279
1280#define THREAD_SIBLING_FOREACH(cs, cs_sibling)                  \
1281    CPU_FOREACH(cs_sibling)                                     \
1282        if (_CORE_ID(cs) == _CORE_ID(cs_sibling))
1283
1284#define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1285do {                                            \
1286    env->fit_period[0] = (a_);                  \
1287    env->fit_period[1] = (b_);                  \
1288    env->fit_period[2] = (c_);                  \
1289    env->fit_period[3] = (d_);                  \
1290 } while (0)
1291
1292#define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1293do {                                            \
1294    env->wdt_period[0] = (a_);                  \
1295    env->wdt_period[1] = (b_);                  \
1296    env->wdt_period[2] = (c_);                  \
1297    env->wdt_period[3] = (d_);                  \
1298 } while (0)
1299
1300typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1301typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1302
1303/**
1304 * PowerPCCPU:
1305 * @env: #CPUPPCState
1306 * @vcpu_id: vCPU identifier given to KVM
1307 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1308 *
1309 * A PowerPC CPU.
1310 */
1311struct ArchCPU {
1312    /*< private >*/
1313    CPUState parent_obj;
1314    /*< public >*/
1315
1316    CPUNegativeOffsetState neg;
1317    CPUPPCState env;
1318
1319    int vcpu_id;
1320    uint32_t compat_pvr;
1321    PPCVirtualHypervisor *vhyp;
1322    void *machine_data;
1323    int32_t node_id; /* NUMA node this CPU belongs to */
1324    PPCHash64Options *hash64_opts;
1325
1326    /* Those resources are used only during code translation */
1327    /* opcode handlers */
1328    opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1329
1330    /* Fields related to migration compatibility hacks */
1331    bool pre_2_8_migration;
1332    target_ulong mig_msr_mask;
1333    uint64_t mig_insns_flags;
1334    uint64_t mig_insns_flags2;
1335    uint32_t mig_nb_BATs;
1336    bool pre_2_10_migration;
1337    bool pre_3_0_migration;
1338    int32_t mig_slb_nr;
1339};
1340
1341
1342PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1343PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1344PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1345
1346#ifndef CONFIG_USER_ONLY
1347struct PPCVirtualHypervisorClass {
1348    InterfaceClass parent;
1349    bool (*cpu_in_nested)(PowerPCCPU *cpu);
1350    void (*deliver_hv_excp)(PowerPCCPU *cpu, int excp);
1351    void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1352    hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1353    const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1354                                         hwaddr ptex, int n);
1355    void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1356                        const ppc_hash_pte64_t *hptes,
1357                        hwaddr ptex, int n);
1358    void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1359    void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1360    bool (*get_pate)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
1361                     target_ulong lpid, ppc_v3_pate_t *entry);
1362    target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1363    void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1364    void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1365};
1366
1367#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1368DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1369                     PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1370
1371static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
1372{
1373    return PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp)->cpu_in_nested(cpu);
1374}
1375#endif /* CONFIG_USER_ONLY */
1376
1377void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1378int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1379int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1380int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1381int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1382#ifndef CONFIG_USER_ONLY
1383hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1384void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1385const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1386#endif
1387int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1388                               int cpuid, DumpState *s);
1389int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1390                               int cpuid, DumpState *s);
1391#ifndef CONFIG_USER_ONLY
1392void ppc_maybe_interrupt(CPUPPCState *env);
1393void ppc_cpu_do_interrupt(CPUState *cpu);
1394bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1395void ppc_cpu_do_system_reset(CPUState *cs);
1396void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1397extern const VMStateDescription vmstate_ppc_cpu;
1398#endif
1399
1400/*****************************************************************************/
1401void ppc_translate_init(void);
1402
1403#if !defined(CONFIG_USER_ONLY)
1404void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1405void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1406#endif /* !defined(CONFIG_USER_ONLY) */
1407void ppc_store_msr(CPUPPCState *env, target_ulong value);
1408
1409void ppc_cpu_list(void);
1410
1411/* Time-base and decrementer management */
1412uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1413uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1414void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1415void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1416uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1417uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1418void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1419void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1420uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1421void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1422bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1423target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1424void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1425target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1426void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1427void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1428uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1429void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1430#if !defined(CONFIG_USER_ONLY)
1431target_ulong load_40x_pit(CPUPPCState *env);
1432void store_40x_pit(CPUPPCState *env, target_ulong val);
1433void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1434void store_40x_sler(CPUPPCState *env, uint32_t val);
1435void store_40x_tcr(CPUPPCState *env, target_ulong val);
1436void store_40x_tsr(CPUPPCState *env, target_ulong val);
1437void store_booke_tcr(CPUPPCState *env, target_ulong val);
1438void store_booke_tsr(CPUPPCState *env, target_ulong val);
1439void ppc_tlb_invalidate_all(CPUPPCState *env);
1440void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1441void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1442void cpu_ppc_set_1lpar(PowerPCCPU *cpu);
1443int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
1444                     target_ulong address, uint32_t pid);
1445int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid);
1446hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
1447#endif
1448
1449void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1450void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1451                                 const char *caller, uint32_t cause);
1452
1453static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1454{
1455    uint64_t gprv;
1456
1457    gprv = env->gpr[gprn];
1458    if (env->flags & POWERPC_FLAG_SPE) {
1459        /*
1460         * If the CPU implements the SPE extension, we have to get the
1461         * high bits of the GPR from the gprh storage area
1462         */
1463        gprv &= 0xFFFFFFFFULL;
1464        gprv |= (uint64_t)env->gprh[gprn] << 32;
1465    }
1466
1467    return gprv;
1468}
1469
1470/* Device control registers */
1471int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1472int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1473
1474#define cpu_list ppc_cpu_list
1475
1476/* MMU modes definitions */
1477#define MMU_USER_IDX 0
1478static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1479{
1480#ifdef CONFIG_USER_ONLY
1481    return MMU_USER_IDX;
1482#else
1483    return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1484#endif
1485}
1486
1487/* Compatibility modes */
1488#if defined(TARGET_PPC64)
1489bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1490                      uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1491bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1492                           uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1493
1494int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1495
1496#if !defined(CONFIG_USER_ONLY)
1497int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1498#endif
1499int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1500void ppc_compat_add_property(Object *obj, const char *name,
1501                             uint32_t *compat_pvr, const char *basedesc);
1502#endif /* defined(TARGET_PPC64) */
1503
1504#include "exec/cpu-all.h"
1505
1506/*****************************************************************************/
1507/* CRF definitions */
1508#define CRF_LT_BIT    3
1509#define CRF_GT_BIT    2
1510#define CRF_EQ_BIT    1
1511#define CRF_SO_BIT    0
1512#define CRF_LT        (1 << CRF_LT_BIT)
1513#define CRF_GT        (1 << CRF_GT_BIT)
1514#define CRF_EQ        (1 << CRF_EQ_BIT)
1515#define CRF_SO        (1 << CRF_SO_BIT)
1516/* For SPE extensions */
1517#define CRF_CH        (1 << CRF_LT_BIT)
1518#define CRF_CL        (1 << CRF_GT_BIT)
1519#define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1520#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1521
1522/* XER definitions */
1523#define XER_SO  31
1524#define XER_OV  30
1525#define XER_CA  29
1526#define XER_OV32  19
1527#define XER_CA32  18
1528#define XER_CMP  8
1529#define XER_BC   0
1530#define xer_so  (env->so)
1531#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1532#define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1533
1534/* SPR definitions */
1535#define SPR_MQ                (0x000)
1536#define SPR_XER               (0x001)
1537#define SPR_LR                (0x008)
1538#define SPR_CTR               (0x009)
1539#define SPR_UAMR              (0x00D)
1540#define SPR_DSCR              (0x011)
1541#define SPR_DSISR             (0x012)
1542#define SPR_DAR               (0x013)
1543#define SPR_DECR              (0x016)
1544#define SPR_SDR1              (0x019)
1545#define SPR_SRR0              (0x01A)
1546#define SPR_SRR1              (0x01B)
1547#define SPR_CFAR              (0x01C)
1548#define SPR_AMR               (0x01D)
1549#define SPR_ACOP              (0x01F)
1550#define SPR_BOOKE_PID         (0x030)
1551#define SPR_BOOKS_PID         (0x030)
1552#define SPR_BOOKE_DECAR       (0x036)
1553#define SPR_BOOKE_CSRR0       (0x03A)
1554#define SPR_BOOKE_CSRR1       (0x03B)
1555#define SPR_BOOKE_DEAR        (0x03D)
1556#define SPR_IAMR              (0x03D)
1557#define SPR_BOOKE_ESR         (0x03E)
1558#define SPR_BOOKE_IVPR        (0x03F)
1559#define SPR_MPC_EIE           (0x050)
1560#define SPR_MPC_EID           (0x051)
1561#define SPR_MPC_NRI           (0x052)
1562#define SPR_TFHAR             (0x080)
1563#define SPR_TFIAR             (0x081)
1564#define SPR_TEXASR            (0x082)
1565#define SPR_TEXASRU           (0x083)
1566#define SPR_UCTRL             (0x088)
1567#define SPR_TIDR              (0x090)
1568#define SPR_MPC_CMPA          (0x090)
1569#define SPR_MPC_CMPB          (0x091)
1570#define SPR_MPC_CMPC          (0x092)
1571#define SPR_MPC_CMPD          (0x093)
1572#define SPR_MPC_ECR           (0x094)
1573#define SPR_MPC_DER           (0x095)
1574#define SPR_MPC_COUNTA        (0x096)
1575#define SPR_MPC_COUNTB        (0x097)
1576#define SPR_CTRL              (0x098)
1577#define SPR_MPC_CMPE          (0x098)
1578#define SPR_MPC_CMPF          (0x099)
1579#define SPR_FSCR              (0x099)
1580#define SPR_MPC_CMPG          (0x09A)
1581#define SPR_MPC_CMPH          (0x09B)
1582#define SPR_MPC_LCTRL1        (0x09C)
1583#define SPR_MPC_LCTRL2        (0x09D)
1584#define SPR_UAMOR             (0x09D)
1585#define SPR_MPC_ICTRL         (0x09E)
1586#define SPR_MPC_BAR           (0x09F)
1587#define SPR_PSPB              (0x09F)
1588#define SPR_DPDES             (0x0B0)
1589#define SPR_DAWR0             (0x0B4)
1590#define SPR_RPR               (0x0BA)
1591#define SPR_CIABR             (0x0BB)
1592#define SPR_DAWRX0            (0x0BC)
1593#define SPR_HFSCR             (0x0BE)
1594#define SPR_VRSAVE            (0x100)
1595#define SPR_USPRG0            (0x100)
1596#define SPR_USPRG1            (0x101)
1597#define SPR_USPRG2            (0x102)
1598#define SPR_USPRG3            (0x103)
1599#define SPR_USPRG4            (0x104)
1600#define SPR_USPRG5            (0x105)
1601#define SPR_USPRG6            (0x106)
1602#define SPR_USPRG7            (0x107)
1603#define SPR_VTBL              (0x10C)
1604#define SPR_VTBU              (0x10D)
1605#define SPR_SPRG0             (0x110)
1606#define SPR_SPRG1             (0x111)
1607#define SPR_SPRG2             (0x112)
1608#define SPR_SPRG3             (0x113)
1609#define SPR_SPRG4             (0x114)
1610#define SPR_SCOMC             (0x114)
1611#define SPR_SPRG5             (0x115)
1612#define SPR_SCOMD             (0x115)
1613#define SPR_SPRG6             (0x116)
1614#define SPR_SPRG7             (0x117)
1615#define SPR_ASR               (0x118)
1616#define SPR_EAR               (0x11A)
1617#define SPR_TBL               (0x11C)
1618#define SPR_TBU               (0x11D)
1619#define SPR_TBU40             (0x11E)
1620#define SPR_SVR               (0x11E)
1621#define SPR_BOOKE_PIR         (0x11E)
1622#define SPR_PVR               (0x11F)
1623#define SPR_HSPRG0            (0x130)
1624#define SPR_BOOKE_DBSR        (0x130)
1625#define SPR_HSPRG1            (0x131)
1626#define SPR_HDSISR            (0x132)
1627#define SPR_HDAR              (0x133)
1628#define SPR_BOOKE_EPCR        (0x133)
1629#define SPR_SPURR             (0x134)
1630#define SPR_BOOKE_DBCR0       (0x134)
1631#define SPR_IBCR              (0x135)
1632#define SPR_PURR              (0x135)
1633#define SPR_BOOKE_DBCR1       (0x135)
1634#define SPR_DBCR              (0x136)
1635#define SPR_HDEC              (0x136)
1636#define SPR_BOOKE_DBCR2       (0x136)
1637#define SPR_HIOR              (0x137)
1638#define SPR_MBAR              (0x137)
1639#define SPR_RMOR              (0x138)
1640#define SPR_BOOKE_IAC1        (0x138)
1641#define SPR_HRMOR             (0x139)
1642#define SPR_BOOKE_IAC2        (0x139)
1643#define SPR_HSRR0             (0x13A)
1644#define SPR_BOOKE_IAC3        (0x13A)
1645#define SPR_HSRR1             (0x13B)
1646#define SPR_BOOKE_IAC4        (0x13B)
1647#define SPR_BOOKE_DAC1        (0x13C)
1648#define SPR_MMCRH             (0x13C)
1649#define SPR_DABR2             (0x13D)
1650#define SPR_BOOKE_DAC2        (0x13D)
1651#define SPR_TFMR              (0x13D)
1652#define SPR_BOOKE_DVC1        (0x13E)
1653#define SPR_LPCR              (0x13E)
1654#define SPR_BOOKE_DVC2        (0x13F)
1655#define SPR_LPIDR             (0x13F)
1656#define SPR_BOOKE_TSR         (0x150)
1657#define SPR_HMER              (0x150)
1658#define SPR_HMEER             (0x151)
1659#define SPR_PCR               (0x152)
1660#define SPR_HEIR              (0x153)
1661#define SPR_BOOKE_LPIDR       (0x152)
1662#define SPR_BOOKE_TCR         (0x154)
1663#define SPR_BOOKE_TLB0PS      (0x158)
1664#define SPR_BOOKE_TLB1PS      (0x159)
1665#define SPR_BOOKE_TLB2PS      (0x15A)
1666#define SPR_BOOKE_TLB3PS      (0x15B)
1667#define SPR_AMOR              (0x15D)
1668#define SPR_BOOKE_MAS7_MAS3   (0x174)
1669#define SPR_BOOKE_IVOR0       (0x190)
1670#define SPR_BOOKE_IVOR1       (0x191)
1671#define SPR_BOOKE_IVOR2       (0x192)
1672#define SPR_BOOKE_IVOR3       (0x193)
1673#define SPR_BOOKE_IVOR4       (0x194)
1674#define SPR_BOOKE_IVOR5       (0x195)
1675#define SPR_BOOKE_IVOR6       (0x196)
1676#define SPR_BOOKE_IVOR7       (0x197)
1677#define SPR_BOOKE_IVOR8       (0x198)
1678#define SPR_BOOKE_IVOR9       (0x199)
1679#define SPR_BOOKE_IVOR10      (0x19A)
1680#define SPR_BOOKE_IVOR11      (0x19B)
1681#define SPR_BOOKE_IVOR12      (0x19C)
1682#define SPR_BOOKE_IVOR13      (0x19D)
1683#define SPR_BOOKE_IVOR14      (0x19E)
1684#define SPR_BOOKE_IVOR15      (0x19F)
1685#define SPR_BOOKE_IVOR38      (0x1B0)
1686#define SPR_BOOKE_IVOR39      (0x1B1)
1687#define SPR_BOOKE_IVOR40      (0x1B2)
1688#define SPR_BOOKE_IVOR41      (0x1B3)
1689#define SPR_BOOKE_IVOR42      (0x1B4)
1690#define SPR_BOOKE_GIVOR2      (0x1B8)
1691#define SPR_BOOKE_GIVOR3      (0x1B9)
1692#define SPR_BOOKE_GIVOR4      (0x1BA)
1693#define SPR_BOOKE_GIVOR8      (0x1BB)
1694#define SPR_BOOKE_GIVOR13     (0x1BC)
1695#define SPR_BOOKE_GIVOR14     (0x1BD)
1696#define SPR_TIR               (0x1BE)
1697#define SPR_UHDEXCR           (0x1C7)
1698#define SPR_PTCR              (0x1D0)
1699#define SPR_HASHKEYR          (0x1D4)
1700#define SPR_HASHPKEYR         (0x1D5)
1701#define SPR_HDEXCR            (0x1D7)
1702#define SPR_BOOKE_SPEFSCR     (0x200)
1703#define SPR_Exxx_BBEAR        (0x201)
1704#define SPR_Exxx_BBTAR        (0x202)
1705#define SPR_Exxx_L1CFG0       (0x203)
1706#define SPR_Exxx_L1CFG1       (0x204)
1707#define SPR_Exxx_NPIDR        (0x205)
1708#define SPR_ATBL              (0x20E)
1709#define SPR_ATBU              (0x20F)
1710#define SPR_IBAT0U            (0x210)
1711#define SPR_BOOKE_IVOR32      (0x210)
1712#define SPR_RCPU_MI_GRA       (0x210)
1713#define SPR_IBAT0L            (0x211)
1714#define SPR_BOOKE_IVOR33      (0x211)
1715#define SPR_IBAT1U            (0x212)
1716#define SPR_BOOKE_IVOR34      (0x212)
1717#define SPR_IBAT1L            (0x213)
1718#define SPR_BOOKE_IVOR35      (0x213)
1719#define SPR_IBAT2U            (0x214)
1720#define SPR_BOOKE_IVOR36      (0x214)
1721#define SPR_IBAT2L            (0x215)
1722#define SPR_BOOKE_IVOR37      (0x215)
1723#define SPR_IBAT3U            (0x216)
1724#define SPR_IBAT3L            (0x217)
1725#define SPR_DBAT0U            (0x218)
1726#define SPR_RCPU_L2U_GRA      (0x218)
1727#define SPR_DBAT0L            (0x219)
1728#define SPR_DBAT1U            (0x21A)
1729#define SPR_DBAT1L            (0x21B)
1730#define SPR_DBAT2U            (0x21C)
1731#define SPR_DBAT2L            (0x21D)
1732#define SPR_DBAT3U            (0x21E)
1733#define SPR_DBAT3L            (0x21F)
1734#define SPR_IBAT4U            (0x230)
1735#define SPR_RPCU_BBCMCR       (0x230)
1736#define SPR_MPC_IC_CST        (0x230)
1737#define SPR_Exxx_CTXCR        (0x230)
1738#define SPR_IBAT4L            (0x231)
1739#define SPR_MPC_IC_ADR        (0x231)
1740#define SPR_Exxx_DBCR3        (0x231)
1741#define SPR_IBAT5U            (0x232)
1742#define SPR_MPC_IC_DAT        (0x232)
1743#define SPR_Exxx_DBCNT        (0x232)
1744#define SPR_IBAT5L            (0x233)
1745#define SPR_IBAT6U            (0x234)
1746#define SPR_IBAT6L            (0x235)
1747#define SPR_IBAT7U            (0x236)
1748#define SPR_IBAT7L            (0x237)
1749#define SPR_DBAT4U            (0x238)
1750#define SPR_RCPU_L2U_MCR      (0x238)
1751#define SPR_MPC_DC_CST        (0x238)
1752#define SPR_Exxx_ALTCTXCR     (0x238)
1753#define SPR_DBAT4L            (0x239)
1754#define SPR_MPC_DC_ADR        (0x239)
1755#define SPR_DBAT5U            (0x23A)
1756#define SPR_BOOKE_MCSRR0      (0x23A)
1757#define SPR_MPC_DC_DAT        (0x23A)
1758#define SPR_DBAT5L            (0x23B)
1759#define SPR_BOOKE_MCSRR1      (0x23B)
1760#define SPR_DBAT6U            (0x23C)
1761#define SPR_BOOKE_MCSR        (0x23C)
1762#define SPR_DBAT6L            (0x23D)
1763#define SPR_Exxx_MCAR         (0x23D)
1764#define SPR_DBAT7U            (0x23E)
1765#define SPR_BOOKE_DSRR0       (0x23E)
1766#define SPR_DBAT7L            (0x23F)
1767#define SPR_BOOKE_DSRR1       (0x23F)
1768#define SPR_BOOKE_SPRG8       (0x25C)
1769#define SPR_BOOKE_SPRG9       (0x25D)
1770#define SPR_BOOKE_MAS0        (0x270)
1771#define SPR_BOOKE_MAS1        (0x271)
1772#define SPR_BOOKE_MAS2        (0x272)
1773#define SPR_BOOKE_MAS3        (0x273)
1774#define SPR_BOOKE_MAS4        (0x274)
1775#define SPR_BOOKE_MAS5        (0x275)
1776#define SPR_BOOKE_MAS6        (0x276)
1777#define SPR_BOOKE_PID1        (0x279)
1778#define SPR_BOOKE_PID2        (0x27A)
1779#define SPR_MPC_DPDR          (0x280)
1780#define SPR_MPC_IMMR          (0x288)
1781#define SPR_BOOKE_TLB0CFG     (0x2B0)
1782#define SPR_BOOKE_TLB1CFG     (0x2B1)
1783#define SPR_BOOKE_TLB2CFG     (0x2B2)
1784#define SPR_BOOKE_TLB3CFG     (0x2B3)
1785#define SPR_BOOKE_EPR         (0x2BE)
1786#define SPR_PERF0             (0x300)
1787#define SPR_RCPU_MI_RBA0      (0x300)
1788#define SPR_MPC_MI_CTR        (0x300)
1789#define SPR_POWER_USIER       (0x300)
1790#define SPR_PERF1             (0x301)
1791#define SPR_RCPU_MI_RBA1      (0x301)
1792#define SPR_POWER_UMMCR2      (0x301)
1793#define SPR_PERF2             (0x302)
1794#define SPR_RCPU_MI_RBA2      (0x302)
1795#define SPR_MPC_MI_AP         (0x302)
1796#define SPR_POWER_UMMCRA      (0x302)
1797#define SPR_PERF3             (0x303)
1798#define SPR_RCPU_MI_RBA3      (0x303)
1799#define SPR_MPC_MI_EPN        (0x303)
1800#define SPR_POWER_UPMC1       (0x303)
1801#define SPR_PERF4             (0x304)
1802#define SPR_POWER_UPMC2       (0x304)
1803#define SPR_PERF5             (0x305)
1804#define SPR_MPC_MI_TWC        (0x305)
1805#define SPR_POWER_UPMC3       (0x305)
1806#define SPR_PERF6             (0x306)
1807#define SPR_MPC_MI_RPN        (0x306)
1808#define SPR_POWER_UPMC4       (0x306)
1809#define SPR_PERF7             (0x307)
1810#define SPR_POWER_UPMC5       (0x307)
1811#define SPR_PERF8             (0x308)
1812#define SPR_RCPU_L2U_RBA0     (0x308)
1813#define SPR_MPC_MD_CTR        (0x308)
1814#define SPR_POWER_UPMC6       (0x308)
1815#define SPR_PERF9             (0x309)
1816#define SPR_RCPU_L2U_RBA1     (0x309)
1817#define SPR_MPC_MD_CASID      (0x309)
1818#define SPR_970_UPMC7         (0X309)
1819#define SPR_PERFA             (0x30A)
1820#define SPR_RCPU_L2U_RBA2     (0x30A)
1821#define SPR_MPC_MD_AP         (0x30A)
1822#define SPR_970_UPMC8         (0X30A)
1823#define SPR_PERFB             (0x30B)
1824#define SPR_RCPU_L2U_RBA3     (0x30B)
1825#define SPR_MPC_MD_EPN        (0x30B)
1826#define SPR_POWER_UMMCR0      (0X30B)
1827#define SPR_PERFC             (0x30C)
1828#define SPR_MPC_MD_TWB        (0x30C)
1829#define SPR_POWER_USIAR       (0X30C)
1830#define SPR_PERFD             (0x30D)
1831#define SPR_MPC_MD_TWC        (0x30D)
1832#define SPR_POWER_USDAR       (0X30D)
1833#define SPR_PERFE             (0x30E)
1834#define SPR_MPC_MD_RPN        (0x30E)
1835#define SPR_POWER_UMMCR1      (0X30E)
1836#define SPR_PERFF             (0x30F)
1837#define SPR_MPC_MD_TW         (0x30F)
1838#define SPR_UPERF0            (0x310)
1839#define SPR_POWER_SIER        (0x310)
1840#define SPR_UPERF1            (0x311)
1841#define SPR_POWER_MMCR2       (0x311)
1842#define SPR_UPERF2            (0x312)
1843#define SPR_POWER_MMCRA       (0X312)
1844#define SPR_UPERF3            (0x313)
1845#define SPR_POWER_PMC1        (0X313)
1846#define SPR_UPERF4            (0x314)
1847#define SPR_POWER_PMC2        (0X314)
1848#define SPR_UPERF5            (0x315)
1849#define SPR_POWER_PMC3        (0X315)
1850#define SPR_UPERF6            (0x316)
1851#define SPR_POWER_PMC4        (0X316)
1852#define SPR_UPERF7            (0x317)
1853#define SPR_POWER_PMC5        (0X317)
1854#define SPR_UPERF8            (0x318)
1855#define SPR_POWER_PMC6        (0X318)
1856#define SPR_UPERF9            (0x319)
1857#define SPR_970_PMC7          (0X319)
1858#define SPR_UPERFA            (0x31A)
1859#define SPR_970_PMC8          (0X31A)
1860#define SPR_UPERFB            (0x31B)
1861#define SPR_POWER_MMCR0       (0X31B)
1862#define SPR_UPERFC            (0x31C)
1863#define SPR_POWER_SIAR        (0X31C)
1864#define SPR_UPERFD            (0x31D)
1865#define SPR_POWER_SDAR        (0X31D)
1866#define SPR_UPERFE            (0x31E)
1867#define SPR_POWER_MMCR1       (0X31E)
1868#define SPR_UPERFF            (0x31F)
1869#define SPR_RCPU_MI_RA0       (0x320)
1870#define SPR_MPC_MI_DBCAM      (0x320)
1871#define SPR_BESCRS            (0x320)
1872#define SPR_RCPU_MI_RA1       (0x321)
1873#define SPR_MPC_MI_DBRAM0     (0x321)
1874#define SPR_BESCRSU           (0x321)
1875#define SPR_RCPU_MI_RA2       (0x322)
1876#define SPR_MPC_MI_DBRAM1     (0x322)
1877#define SPR_BESCRR            (0x322)
1878#define SPR_RCPU_MI_RA3       (0x323)
1879#define SPR_BESCRRU           (0x323)
1880#define SPR_EBBHR             (0x324)
1881#define SPR_EBBRR             (0x325)
1882#define SPR_BESCR             (0x326)
1883#define SPR_RCPU_L2U_RA0      (0x328)
1884#define SPR_MPC_MD_DBCAM      (0x328)
1885#define SPR_RCPU_L2U_RA1      (0x329)
1886#define SPR_MPC_MD_DBRAM0     (0x329)
1887#define SPR_RCPU_L2U_RA2      (0x32A)
1888#define SPR_MPC_MD_DBRAM1     (0x32A)
1889#define SPR_RCPU_L2U_RA3      (0x32B)
1890#define SPR_UDEXCR            (0x32C)
1891#define SPR_TAR               (0x32F)
1892#define SPR_ASDR              (0x330)
1893#define SPR_DEXCR             (0x33C)
1894#define SPR_IC                (0x350)
1895#define SPR_VTB               (0x351)
1896#define SPR_MMCRC             (0x353)
1897#define SPR_PSSCR             (0x357)
1898#define SPR_440_INV0          (0x370)
1899#define SPR_440_INV1          (0x371)
1900#define SPR_440_INV2          (0x372)
1901#define SPR_440_INV3          (0x373)
1902#define SPR_440_ITV0          (0x374)
1903#define SPR_440_ITV1          (0x375)
1904#define SPR_440_ITV2          (0x376)
1905#define SPR_440_ITV3          (0x377)
1906#define SPR_440_CCR1          (0x378)
1907#define SPR_TACR              (0x378)
1908#define SPR_TCSCR             (0x379)
1909#define SPR_CSIGR             (0x37a)
1910#define SPR_DCRIPR            (0x37B)
1911#define SPR_POWER_SPMC1       (0x37C)
1912#define SPR_POWER_SPMC2       (0x37D)
1913#define SPR_POWER_MMCRS       (0x37E)
1914#define SPR_WORT              (0x37F)
1915#define SPR_PPR               (0x380)
1916#define SPR_750_GQR0          (0x390)
1917#define SPR_440_DNV0          (0x390)
1918#define SPR_750_GQR1          (0x391)
1919#define SPR_440_DNV1          (0x391)
1920#define SPR_750_GQR2          (0x392)
1921#define SPR_440_DNV2          (0x392)
1922#define SPR_750_GQR3          (0x393)
1923#define SPR_440_DNV3          (0x393)
1924#define SPR_750_GQR4          (0x394)
1925#define SPR_440_DTV0          (0x394)
1926#define SPR_750_GQR5          (0x395)
1927#define SPR_440_DTV1          (0x395)
1928#define SPR_750_GQR6          (0x396)
1929#define SPR_440_DTV2          (0x396)
1930#define SPR_750_GQR7          (0x397)
1931#define SPR_440_DTV3          (0x397)
1932#define SPR_750_THRM4         (0x398)
1933#define SPR_750CL_HID2        (0x398)
1934#define SPR_440_DVLIM         (0x398)
1935#define SPR_750_WPAR          (0x399)
1936#define SPR_440_IVLIM         (0x399)
1937#define SPR_TSCR              (0x399)
1938#define SPR_750_DMAU          (0x39A)
1939#define SPR_750_DMAL          (0x39B)
1940#define SPR_440_RSTCFG        (0x39B)
1941#define SPR_BOOKE_DCDBTRL     (0x39C)
1942#define SPR_BOOKE_DCDBTRH     (0x39D)
1943#define SPR_BOOKE_ICDBTRL     (0x39E)
1944#define SPR_BOOKE_ICDBTRH     (0x39F)
1945#define SPR_74XX_UMMCR2       (0x3A0)
1946#define SPR_7XX_UPMC5         (0x3A1)
1947#define SPR_7XX_UPMC6         (0x3A2)
1948#define SPR_UBAMR             (0x3A7)
1949#define SPR_7XX_UMMCR0        (0x3A8)
1950#define SPR_7XX_UPMC1         (0x3A9)
1951#define SPR_7XX_UPMC2         (0x3AA)
1952#define SPR_7XX_USIAR         (0x3AB)
1953#define SPR_7XX_UMMCR1        (0x3AC)
1954#define SPR_7XX_UPMC3         (0x3AD)
1955#define SPR_7XX_UPMC4         (0x3AE)
1956#define SPR_USDA              (0x3AF)
1957#define SPR_40x_ZPR           (0x3B0)
1958#define SPR_BOOKE_MAS7        (0x3B0)
1959#define SPR_74XX_MMCR2        (0x3B0)
1960#define SPR_7XX_PMC5          (0x3B1)
1961#define SPR_40x_PID           (0x3B1)
1962#define SPR_7XX_PMC6          (0x3B2)
1963#define SPR_440_MMUCR         (0x3B2)
1964#define SPR_4xx_CCR0          (0x3B3)
1965#define SPR_BOOKE_EPLC        (0x3B3)
1966#define SPR_405_IAC3          (0x3B4)
1967#define SPR_BOOKE_EPSC        (0x3B4)
1968#define SPR_405_IAC4          (0x3B5)
1969#define SPR_405_DVC1          (0x3B6)
1970#define SPR_405_DVC2          (0x3B7)
1971#define SPR_BAMR              (0x3B7)
1972#define SPR_7XX_MMCR0         (0x3B8)
1973#define SPR_7XX_PMC1          (0x3B9)
1974#define SPR_40x_SGR           (0x3B9)
1975#define SPR_7XX_PMC2          (0x3BA)
1976#define SPR_40x_DCWR          (0x3BA)
1977#define SPR_7XX_SIAR          (0x3BB)
1978#define SPR_405_SLER          (0x3BB)
1979#define SPR_7XX_MMCR1         (0x3BC)
1980#define SPR_405_SU0R          (0x3BC)
1981#define SPR_401_SKR           (0x3BC)
1982#define SPR_7XX_PMC3          (0x3BD)
1983#define SPR_405_DBCR1         (0x3BD)
1984#define SPR_7XX_PMC4          (0x3BE)
1985#define SPR_SDA               (0x3BF)
1986#define SPR_403_VTBL          (0x3CC)
1987#define SPR_403_VTBU          (0x3CD)
1988#define SPR_DMISS             (0x3D0)
1989#define SPR_DCMP              (0x3D1)
1990#define SPR_HASH1             (0x3D2)
1991#define SPR_HASH2             (0x3D3)
1992#define SPR_BOOKE_ICDBDR      (0x3D3)
1993#define SPR_TLBMISS           (0x3D4)
1994#define SPR_IMISS             (0x3D4)
1995#define SPR_40x_ESR           (0x3D4)
1996#define SPR_PTEHI             (0x3D5)
1997#define SPR_ICMP              (0x3D5)
1998#define SPR_40x_DEAR          (0x3D5)
1999#define SPR_PTELO             (0x3D6)
2000#define SPR_RPA               (0x3D6)

2001#define SPR_40x_EVPR          (0x3D6)
2002#define SPR_L3PM              (0x3D7)
2003#define SPR_403_CDBCR         (0x3D7)
2004#define SPR_L3ITCR0           (0x3D8)
2005#define SPR_TCR               (0x3D8)
2006#define SPR_40x_TSR           (0x3D8)
2007#define SPR_IBR               (0x3DA)
2008#define SPR_40x_TCR           (0x3DA)
2009#define SPR_ESASRR            (0x3DB)
2010#define SPR_40x_PIT           (0x3DB)
2011#define SPR_403_TBL           (0x3DC)
2012#define SPR_403_TBU           (0x3DD)
2013#define SPR_SEBR              (0x3DE)
2014#define SPR_40x_SRR2          (0x3DE)
2015#define SPR_SER               (0x3DF)
2016#define SPR_40x_SRR3          (0x3DF)
2017#define SPR_L3OHCR            (0x3E8)
2018#define SPR_L3ITCR1           (0x3E9)
2019#define SPR_L3ITCR2           (0x3EA)
2020#define SPR_L3ITCR3           (0x3EB)
2021#define SPR_HID0              (0x3F0)
2022#define SPR_40x_DBSR          (0x3F0)
2023#define SPR_HID1              (0x3F1)
2024#define SPR_IABR              (0x3F2)
2025#define SPR_40x_DBCR0         (0x3F2)
2026#define SPR_Exxx_L1CSR0       (0x3F2)
2027#define SPR_ICTRL             (0x3F3)
2028#define SPR_HID2              (0x3F3)
2029#define SPR_750CL_HID4        (0x3F3)
2030#define SPR_Exxx_L1CSR1       (0x3F3)
2031#define SPR_440_DBDR          (0x3F3)
2032#define SPR_LDSTDB            (0x3F4)
2033#define SPR_750_TDCL          (0x3F4)
2034#define SPR_40x_IAC1          (0x3F4)
2035#define SPR_MMUCSR0           (0x3F4)
2036#define SPR_970_HID4          (0x3F4)
2037#define SPR_DABR              (0x3F5)
2038#define DABR_MASK (~(target_ulong)0x7)
2039#define SPR_Exxx_BUCSR        (0x3F5)
2040#define SPR_40x_IAC2          (0x3F5)
2041#define SPR_40x_DAC1          (0x3F6)
2042#define SPR_MSSCR0            (0x3F6)
2043#define SPR_970_HID5          (0x3F6)
2044#define SPR_MSSSR0            (0x3F7)
2045#define SPR_MSSCR1            (0x3F7)
2046#define SPR_DABRX             (0x3F7)
2047#define SPR_40x_DAC2          (0x3F7)
2048#define SPR_MMUCFG            (0x3F7)
2049#define SPR_LDSTCR            (0x3F8)
2050#define SPR_L2PMCR            (0x3F8)
2051#define SPR_750FX_HID2        (0x3F8)
2052#define SPR_Exxx_L1FINV0      (0x3F8)
2053#define SPR_L2CR              (0x3F9)
2054#define SPR_Exxx_L2CSR0       (0x3F9)
2055#define SPR_L3CR              (0x3FA)
2056#define SPR_750_TDCH          (0x3FA)
2057#define SPR_IABR2             (0x3FA)
2058#define SPR_40x_DCCR          (0x3FA)
2059#define SPR_ICTC              (0x3FB)
2060#define SPR_40x_ICCR          (0x3FB)
2061#define SPR_THRM1             (0x3FC)
2062#define SPR_403_PBL1          (0x3FC)
2063#define SPR_SP                (0x3FD)
2064#define SPR_THRM2             (0x3FD)
2065#define SPR_403_PBU1          (0x3FD)
2066#define SPR_604_HID13         (0x3FD)
2067#define SPR_LT                (0x3FE)
2068#define SPR_THRM3             (0x3FE)
2069#define SPR_RCPU_FPECR        (0x3FE)
2070#define SPR_403_PBL2          (0x3FE)
2071#define SPR_PIR               (0x3FF)
2072#define SPR_403_PBU2          (0x3FF)
2073#define SPR_604_HID15         (0x3FF)
2074#define SPR_E500_SVR          (0x3FF)
2075
2076/* Disable MAS Interrupt Updates for Hypervisor */
2077#define EPCR_DMIUH            (1 << 22)
2078/* Disable Guest TLB Management Instructions */
2079#define EPCR_DGTMI            (1 << 23)
2080/* Guest Interrupt Computation Mode */
2081#define EPCR_GICM             (1 << 24)
2082/* Interrupt Computation Mode */
2083#define EPCR_ICM              (1 << 25)
2084/* Disable Embedded Hypervisor Debug */
2085#define EPCR_DUVD             (1 << 26)
2086/* Instruction Storage Interrupt Directed to Guest State */
2087#define EPCR_ISIGS            (1 << 27)
2088/* Data Storage Interrupt Directed to Guest State */
2089#define EPCR_DSIGS            (1 << 28)
2090/* Instruction TLB Error Interrupt Directed to Guest State */
2091#define EPCR_ITLBGS           (1 << 29)
2092/* Data TLB Error Interrupt Directed to Guest State */
2093#define EPCR_DTLBGS           (1 << 30)
2094/* External Input Interrupt Directed to Guest State */
2095#define EPCR_EXTGS            (1 << 31)
2096
2097#define   L1CSR0_CPE    0x00010000  /* Data Cache Parity Enable */
2098#define   L1CSR0_CUL    0x00000400  /* (D-)Cache Unable to Lock */
2099#define   L1CSR0_DCLFR  0x00000100  /* D-Cache Lock Flash Reset */
2100#define   L1CSR0_DCFI   0x00000002  /* Data Cache Flash Invalidate */
2101#define   L1CSR0_DCE    0x00000001  /* Data Cache Enable */
2102
2103#define   L1CSR1_CPE    0x00010000  /* Instruction Cache Parity Enable */
2104#define   L1CSR1_ICUL   0x00000400  /* I-Cache Unable to Lock */
2105#define   L1CSR1_ICLFR  0x00000100  /* I-Cache Lock Flash Reset */
2106#define   L1CSR1_ICFI   0x00000002  /* Instruction Cache Flash Invalidate */
2107#define   L1CSR1_ICE    0x00000001  /* Instruction Cache Enable */
2108
2109/* E500 L2CSR0 */
2110#define E500_L2CSR0_L2FI    (1 << 21)   /* L2 cache flash invalidate */
2111#define E500_L2CSR0_L2FL    (1 << 11)   /* L2 cache flush */
2112#define E500_L2CSR0_L2LFC   (1 << 10)   /* L2 cache lock flash clear */
2113
2114/* HID0 bits */
2115#define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
2116#define HID0_DOZE           (1 << 23)           /* pre-2.06 */
2117#define HID0_NAP            (1 << 22)           /* pre-2.06 */
2118#define HID0_HILE           PPC_BIT(19) /* POWER8 */
2119#define HID0_POWER9_HILE    PPC_BIT(4)
2120
2121/*****************************************************************************/
2122/* PowerPC Instructions types definitions                                    */
2123enum {
2124    PPC_NONE           = 0x0000000000000000ULL,
2125    /* PowerPC base instructions set                                         */
2126    PPC_INSNS_BASE     = 0x0000000000000001ULL,
2127    /*   integer operations instructions                                     */
2128#define PPC_INTEGER PPC_INSNS_BASE
2129    /*   flow control instructions                                           */
2130#define PPC_FLOW    PPC_INSNS_BASE
2131    /*   virtual memory instructions                                         */
2132#define PPC_MEM     PPC_INSNS_BASE
2133    /*   ld/st with reservation instructions                                 */
2134#define PPC_RES     PPC_INSNS_BASE
2135    /*   spr/msr access instructions                                         */
2136#define PPC_MISC    PPC_INSNS_BASE
2137    /* 64 bits PowerPC instruction set                                       */
2138    PPC_64B            = 0x0000000000000020ULL,
2139    /*   New 64 bits extensions (PowerPC 2.0x)                               */
2140    PPC_64BX           = 0x0000000000000040ULL,
2141    /*   64 bits hypervisor extensions                                       */
2142    PPC_64H            = 0x0000000000000080ULL,
2143    /*   New wait instruction (PowerPC 2.0x)                                 */
2144    PPC_WAIT           = 0x0000000000000100ULL,
2145    /*   Time base mftb instruction                                          */
2146    PPC_MFTB           = 0x0000000000000200ULL,
2147
2148    /* Fixed-point unit extensions                                           */
2149    /*   isel instruction                                                    */
2150    PPC_ISEL           = 0x0000000000000800ULL,
2151    /*   popcntb instruction                                                 */
2152    PPC_POPCNTB        = 0x0000000000001000ULL,
2153    /*   string load / store                                                 */
2154    PPC_STRING         = 0x0000000000002000ULL,
2155    /*   real mode cache inhibited load / store                              */
2156    PPC_CILDST         = 0x0000000000004000ULL,
2157
2158    /* Floating-point unit extensions                                        */
2159    /*   Optional floating point instructions                                */
2160    PPC_FLOAT          = 0x0000000000010000ULL,
2161    /* New floating-point extensions (PowerPC 2.0x)                          */
2162    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2163    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2164    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2165    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2166    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2167    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2168    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2169
2170    /* Vector/SIMD extensions                                                */
2171    /*   Altivec support                                                     */
2172    PPC_ALTIVEC        = 0x0000000001000000ULL,
2173    /*   PowerPC 2.03 SPE extension                                          */
2174    PPC_SPE            = 0x0000000002000000ULL,
2175    /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2176    PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2177    /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2178    PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2179
2180    /* Optional memory control instructions                                  */
2181    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2182    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2183    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2184    /*   sync instruction                                                    */
2185    PPC_MEM_SYNC       = 0x0000000080000000ULL,
2186    /*   eieio instruction                                                   */
2187    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2188
2189    /* Cache control instructions                                            */
2190    PPC_CACHE          = 0x0000000200000000ULL,
2191    /*   icbi instruction                                                    */
2192    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2193    /*   dcbz instruction                                                    */
2194    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2195    /*   dcba instruction                                                    */
2196    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2197    /*   Freescale cache locking instructions                                */
2198    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2199
2200    /* MMU related extensions                                                */
2201    /*   external control instructions                                       */
2202    PPC_EXTERN         = 0x0000010000000000ULL,
2203    /*   segment register access instructions                                */
2204    PPC_SEGMENT        = 0x0000020000000000ULL,
2205    /*   PowerPC 6xx TLB management instructions                             */
2206    PPC_6xx_TLB        = 0x0000040000000000ULL,
2207    /*   PowerPC 40x TLB management instructions                             */
2208    PPC_40x_TLB        = 0x0000100000000000ULL,
2209    /*   segment register access instructions for PowerPC 64 "bridge"        */
2210    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2211    /*   SLB management                                                      */
2212    PPC_SLBI           = 0x0000400000000000ULL,
2213
2214    /* Embedded PowerPC dedicated instructions                               */
2215    PPC_WRTEE          = 0x0001000000000000ULL,
2216    /* PowerPC 40x exception model                                           */
2217    PPC_40x_EXCP       = 0x0002000000000000ULL,
2218    /* PowerPC 405 Mac instructions                                          */
2219    PPC_405_MAC        = 0x0004000000000000ULL,
2220    /* PowerPC 440 specific instructions                                     */
2221    PPC_440_SPEC       = 0x0008000000000000ULL,
2222    /* BookE (embedded) PowerPC specification                                */
2223    PPC_BOOKE          = 0x0010000000000000ULL,
2224    /* mfapidi instruction                                                   */
2225    PPC_MFAPIDI        = 0x0020000000000000ULL,
2226    /* tlbiva instruction                                                    */
2227    PPC_TLBIVA         = 0x0040000000000000ULL,
2228    /* tlbivax instruction                                                   */
2229    PPC_TLBIVAX        = 0x0080000000000000ULL,
2230    /* PowerPC 4xx dedicated instructions                                    */
2231    PPC_4xx_COMMON     = 0x0100000000000000ULL,
2232    /* PowerPC 40x ibct instructions                                         */
2233    PPC_40x_ICBT       = 0x0200000000000000ULL,
2234    /* rfmci is not implemented in all BookE PowerPC                         */
2235    PPC_RFMCI          = 0x0400000000000000ULL,
2236    /* rfdi instruction                                                      */
2237    PPC_RFDI           = 0x0800000000000000ULL,
2238    /* DCR accesses                                                          */
2239    PPC_DCR            = 0x1000000000000000ULL,
2240    /* DCR extended accesse                                                  */
2241    PPC_DCRX           = 0x2000000000000000ULL,
2242    /* popcntw and popcntd instructions                                      */
2243    PPC_POPCNTWD       = 0x8000000000000000ULL,
2244
2245#define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_64B \
2246                        | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2247                        | PPC_ISEL | PPC_POPCNTB \
2248                        | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2249                        | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2250                        | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2251                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2252                        | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2253                        | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2254                        | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2255                        | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2256                        | PPC_CACHE | PPC_CACHE_ICBI \
2257                        | PPC_CACHE_DCBZ \
2258                        | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2259                        | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2260                        | PPC_40x_TLB | PPC_SEGMENT_64B \
2261                        | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2262                        | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2263                        | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2264                        | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2265                        | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
2266                        | PPC_CILDST)
2267
2268    /* extended type values */
2269
2270    /* BookE 2.06 PowerPC specification                                      */
2271    PPC2_BOOKE206      = 0x0000000000000001ULL,
2272    /* VSX (extensions to Altivec / VMX)                                     */
2273    PPC2_VSX           = 0x0000000000000002ULL,
2274    /* Decimal Floating Point (DFP)                                          */
2275    PPC2_DFP           = 0x0000000000000004ULL,
2276    /* Embedded.Processor Control                                            */
2277    PPC2_PRCNTL        = 0x0000000000000008ULL,
2278    /* Byte-reversed, indexed, double-word load and store                    */
2279    PPC2_DBRX          = 0x0000000000000010ULL,
2280    /* Book I 2.05 PowerPC specification                                     */
2281    PPC2_ISA205        = 0x0000000000000020ULL,
2282    /* VSX additions in ISA 2.07                                             */
2283    PPC2_VSX207        = 0x0000000000000040ULL,
2284    /* ISA 2.06B bpermd                                                      */
2285    PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2286    /* ISA 2.06B divide extended variants                                    */
2287    PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2288    /* ISA 2.06B larx/stcx. instructions                                     */
2289    PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2290    /* ISA 2.06B floating point integer conversion                           */
2291    PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2292    /* ISA 2.06B floating point test instructions                            */
2293    PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2294    /* ISA 2.07 bctar instruction                                            */
2295    PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2296    /* ISA 2.07 load/store quadword                                          */
2297    PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2298    /* ISA 2.07 Altivec                                                      */
2299    PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2300    /* PowerISA 2.07 Book3s specification                                    */
2301    PPC2_ISA207S       = 0x0000000000008000ULL,
2302    /* Double precision floating point conversion for signed integer 64      */
2303    PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2304    /* Transactional Memory (ISA 2.07, Book II)                              */
2305    PPC2_TM            = 0x0000000000020000ULL,
2306    /* Server PM instructgions (ISA 2.06, Book III)                          */
2307    PPC2_PM_ISA206     = 0x0000000000040000ULL,
2308    /* POWER ISA 3.0                                                         */
2309    PPC2_ISA300        = 0x0000000000080000ULL,
2310    /* POWER ISA 3.1                                                         */
2311    PPC2_ISA310        = 0x0000000000100000ULL,
2312    /*   lwsync instruction                                                  */
2313    PPC2_MEM_LWSYNC    = 0x0000000000200000ULL,
2314    /* ISA 2.06 BCD assist instructions                                      */
2315    PPC2_BCDA_ISA206   = 0x0000000000400000ULL,
2316
2317#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2318                        PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2319                        PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2320                        PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2321                        PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2322                        PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2323                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2324                        PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
2325                        PPC2_BCDA_ISA206)
2326};
2327
2328/*****************************************************************************/
2329/*
2330 * Memory access type :
2331 * may be needed for precise access rights control and precise exceptions.
2332 */
2333enum {
2334    /* Type of instruction that generated the access */
2335    ACCESS_CODE  = 0x10, /* Code fetch access                */
2336    ACCESS_INT   = 0x20, /* Integer load/store access        */
2337    ACCESS_FLOAT = 0x30, /* floating point load/store access */
2338    ACCESS_RES   = 0x40, /* load/store with reservation      */
2339    ACCESS_EXT   = 0x50, /* external access                  */
2340    ACCESS_CACHE = 0x60, /* Cache manipulation               */
2341};
2342
2343/*
2344 * Hardware interrupt sources:
2345 *   all those exception can be raised simulteaneously
2346 */
2347/* Input pins definitions */
2348enum {
2349    /* 6xx bus input pins */
2350    PPC6xx_INPUT_HRESET     = 0,
2351    PPC6xx_INPUT_SRESET     = 1,
2352    PPC6xx_INPUT_CKSTP_IN   = 2,
2353    PPC6xx_INPUT_MCP        = 3,
2354    PPC6xx_INPUT_SMI        = 4,
2355    PPC6xx_INPUT_INT        = 5,
2356    PPC6xx_INPUT_TBEN       = 6,
2357    PPC6xx_INPUT_WAKEUP     = 7,
2358    PPC6xx_INPUT_NB,
2359};
2360
2361enum {
2362    /* Embedded PowerPC input pins */
2363    PPCBookE_INPUT_HRESET     = 0,
2364    PPCBookE_INPUT_SRESET     = 1,
2365    PPCBookE_INPUT_CKSTP_IN   = 2,
2366    PPCBookE_INPUT_MCP        = 3,
2367    PPCBookE_INPUT_SMI        = 4,
2368    PPCBookE_INPUT_INT        = 5,
2369    PPCBookE_INPUT_CINT       = 6,
2370    PPCBookE_INPUT_NB,
2371};
2372
2373enum {
2374    /* PowerPC E500 input pins */
2375    PPCE500_INPUT_RESET_CORE = 0,
2376    PPCE500_INPUT_MCK        = 1,
2377    PPCE500_INPUT_CINT       = 3,
2378    PPCE500_INPUT_INT        = 4,
2379    PPCE500_INPUT_DEBUG      = 6,
2380    PPCE500_INPUT_NB,
2381};
2382
2383enum {
2384    /* PowerPC 40x input pins */
2385    PPC40x_INPUT_RESET_CORE = 0,
2386    PPC40x_INPUT_RESET_CHIP = 1,
2387    PPC40x_INPUT_RESET_SYS  = 2,
2388    PPC40x_INPUT_CINT       = 3,
2389    PPC40x_INPUT_INT        = 4,
2390    PPC40x_INPUT_HALT       = 5,
2391    PPC40x_INPUT_DEBUG      = 6,
2392    PPC40x_INPUT_NB,
2393};
2394
2395enum {
2396    /* RCPU input pins */
2397    PPCRCPU_INPUT_PORESET   = 0,
2398    PPCRCPU_INPUT_HRESET    = 1,
2399    PPCRCPU_INPUT_SRESET    = 2,
2400    PPCRCPU_INPUT_IRQ0      = 3,
2401    PPCRCPU_INPUT_IRQ1      = 4,
2402    PPCRCPU_INPUT_IRQ2      = 5,
2403    PPCRCPU_INPUT_IRQ3      = 6,
2404    PPCRCPU_INPUT_IRQ4      = 7,
2405    PPCRCPU_INPUT_IRQ5      = 8,
2406    PPCRCPU_INPUT_IRQ6      = 9,
2407    PPCRCPU_INPUT_IRQ7      = 10,
2408    PPCRCPU_INPUT_NB,
2409};
2410
2411#if defined(TARGET_PPC64)
2412enum {
2413    /* PowerPC 970 input pins */
2414    PPC970_INPUT_HRESET     = 0,
2415    PPC970_INPUT_SRESET     = 1,
2416    PPC970_INPUT_CKSTP      = 2,
2417    PPC970_INPUT_TBEN       = 3,
2418    PPC970_INPUT_MCP        = 4,
2419    PPC970_INPUT_INT        = 5,
2420    PPC970_INPUT_THINT      = 6,
2421    PPC970_INPUT_NB,
2422};
2423
2424enum {
2425    /* POWER7 input pins */
2426    POWER7_INPUT_INT        = 0,
2427    /*
2428     * POWER7 probably has other inputs, but we don't care about them
2429     * for any existing machine.  We can wire these up when we need
2430     * them
2431     */
2432    POWER7_INPUT_NB,
2433};
2434
2435enum {
2436    /* POWER9 input pins */
2437    POWER9_INPUT_INT        = 0,
2438    POWER9_INPUT_HINT       = 1,
2439    POWER9_INPUT_NB,
2440};
2441#endif
2442
2443/* Hardware exceptions definitions */
2444enum {
2445    /* External hardware exception sources */
2446    PPC_INTERRUPT_RESET     = 0x00001,  /* Reset exception                    */
2447    PPC_INTERRUPT_WAKEUP    = 0x00002,  /* Wakeup exception                   */
2448    PPC_INTERRUPT_MCK       = 0x00004,  /* Machine check exception            */
2449    PPC_INTERRUPT_EXT       = 0x00008,  /* External interrupt                 */
2450    PPC_INTERRUPT_SMI       = 0x00010,  /* System management interrupt        */
2451    PPC_INTERRUPT_CEXT      = 0x00020,  /* Critical external interrupt        */
2452    PPC_INTERRUPT_DEBUG     = 0x00040,  /* External debug exception           */
2453    PPC_INTERRUPT_THERM     = 0x00080,  /* Thermal exception                  */
2454    /* Internal hardware exception sources */
2455    PPC_INTERRUPT_DECR      = 0x00100, /* Decrementer exception               */
2456    PPC_INTERRUPT_HDECR     = 0x00200, /* Hypervisor decrementer exception    */
2457    PPC_INTERRUPT_PIT       = 0x00400, /* Programmable interval timer int.    */
2458    PPC_INTERRUPT_FIT       = 0x00800, /* Fixed interval timer interrupt      */
2459    PPC_INTERRUPT_WDT       = 0x01000, /* Watchdog timer interrupt            */
2460    PPC_INTERRUPT_CDOORBELL = 0x02000, /* Critical doorbell interrupt         */
2461    PPC_INTERRUPT_DOORBELL  = 0x04000, /* Doorbell interrupt                  */
2462    PPC_INTERRUPT_PERFM     = 0x08000, /* Performance monitor interrupt       */
2463    PPC_INTERRUPT_HMI       = 0x10000, /* Hypervisor Maintenance interrupt    */
2464    PPC_INTERRUPT_HDOORBELL = 0x20000, /* Hypervisor Doorbell interrupt       */
2465    PPC_INTERRUPT_HVIRT     = 0x40000, /* Hypervisor virtualization interrupt */
2466    PPC_INTERRUPT_EBB       = 0x80000, /* Event-based Branch exception        */
2467};
2468
2469/* Processor Compatibility mask (PCR) */
2470enum {
2471    PCR_COMPAT_2_05     = PPC_BIT(62),
2472    PCR_COMPAT_2_06     = PPC_BIT(61),
2473    PCR_COMPAT_2_07     = PPC_BIT(60),
2474    PCR_COMPAT_3_00     = PPC_BIT(59),
2475    PCR_COMPAT_3_10     = PPC_BIT(58),
2476    PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2477    PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2478    PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2479};
2480
2481/* HMER/HMEER */
2482enum {
2483    HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2484    HMER_PROC_RECV_DONE         = PPC_BIT(2),
2485    HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2486    HMER_TFAC_ERROR             = PPC_BIT(4),
2487    HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2488    HMER_XSCOM_FAIL             = PPC_BIT(8),
2489    HMER_XSCOM_DONE             = PPC_BIT(9),
2490    HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2491    HMER_WARN_RISE              = PPC_BIT(14),
2492    HMER_WARN_FALL              = PPC_BIT(15),
2493    HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2494    HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2495    HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2496    HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2497};
2498
2499/*****************************************************************************/
2500
2501#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2502target_ulong cpu_read_xer(const CPUPPCState *env);
2503void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2504
2505/*
2506 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2507 * have PPC_SEGMENT_64B.
2508 */
2509#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2510
2511#ifdef CONFIG_DEBUG_TCG
2512void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2513                          uint64_t *cs_base, uint32_t *flags);
2514#else
2515static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2516                                        uint64_t *cs_base, uint32_t *flags)
2517{
2518    *pc = env->nip;
2519    *cs_base = 0;
2520    *flags = env->hflags;
2521}
2522#endif
2523
2524G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
2525G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
2526                                   uintptr_t raddr);
2527G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception,
2528                                    uint32_t error_code);
2529G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2530                                       uint32_t error_code, uintptr_t raddr);
2531
2532/* PERFM EBB helper*/
2533#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2534void raise_ebb_perfm_exception(CPUPPCState *env);
2535#endif
2536
2537#if !defined(CONFIG_USER_ONLY)
2538static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2539{
2540    uintptr_t tlbml = (uintptr_t)tlbm;
2541    uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2542
2543    return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2544}
2545
2546static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2547{
2548    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2549    int r = tlbncfg & TLBnCFG_N_ENTRY;
2550    return r;
2551}
2552
2553static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2554{
2555    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2556    int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2557    return r;
2558}
2559
2560static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2561{
2562    int id = booke206_tlbm_id(env, tlbm);
2563    int end = 0;
2564    int i;
2565
2566    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2567        end += booke206_tlb_size(env, i);
2568        if (id < end) {
2569            return i;
2570        }
2571    }
2572
2573    cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2574    return 0;
2575}
2576
2577static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2578{
2579    int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2580    int tlbid = booke206_tlbm_id(env, tlb);
2581    return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2582}
2583
2584static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2585                                              target_ulong ea, int way)
2586{
2587    int r;
2588    uint32_t ways = booke206_tlb_ways(env, tlbn);
2589    int ways_bits = ctz32(ways);
2590    int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2591    int i;
2592
2593    way &= ways - 1;
2594    ea >>= MAS2_EPN_SHIFT;
2595    ea &= (1 << (tlb_bits - ways_bits)) - 1;
2596    r = (ea << ways_bits) | way;
2597
2598    if (r >= booke206_tlb_size(env, tlbn)) {
2599        return NULL;
2600    }
2601
2602    /* bump up to tlbn index */
2603    for (i = 0; i < tlbn; i++) {
2604        r += booke206_tlb_size(env, i);
2605    }
2606
2607    return &env->tlb.tlbm[r];
2608}
2609
2610/* returns bitmap of supported page sizes for a given TLB */
2611static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2612{
2613    uint32_t ret = 0;
2614
2615    if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2616        /* MAV2 */
2617        ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2618    } else {
2619        uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2620        uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2621        uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2622        int i;
2623        for (i = min; i <= max; i++) {
2624            ret |= (1 << (i << 1));
2625        }
2626    }
2627
2628    return ret;
2629}
2630
2631static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2632                                            ppcmas_tlb_t *tlb)
2633{
2634    uint8_t i;
2635    int32_t tsize = -1;
2636
2637    for (i = 0; i < 32; i++) {
2638        if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2639            if (tsize == -1) {
2640                tsize = i;
2641            } else {
2642                return;
2643            }
2644        }
2645    }
2646
2647    /* TLBnPS unimplemented? Odd.. */
2648    assert(tsize != -1);
2649    tlb->mas1 &= ~MAS1_TSIZE_MASK;
2650    tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2651}
2652
2653#endif
2654
2655static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2656{
2657    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2658        return msr & (1ULL << MSR_CM);
2659    }
2660
2661    return msr & (1ULL << MSR_SF);
2662}
2663
2664/**
2665 * Check whether register rx is in the range between start and
2666 * start + nregs (as needed by the LSWX and LSWI instructions)
2667 */
2668static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2669{
2670    return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2671           (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2672}
2673
2674/* Accessors for FP, VMX and VSX registers */
2675#if HOST_BIG_ENDIAN
2676#define VsrB(i) u8[i]
2677#define VsrSB(i) s8[i]
2678#define VsrH(i) u16[i]
2679#define VsrSH(i) s16[i]
2680#define VsrW(i) u32[i]
2681#define VsrSW(i) s32[i]
2682#define VsrD(i) u64[i]
2683#define VsrSD(i) s64[i]
2684#define VsrHF(i) f16[i]
2685#define VsrSF(i) f32[i]
2686#define VsrDF(i) f64[i]
2687#else
2688#define VsrB(i) u8[15 - (i)]
2689#define VsrSB(i) s8[15 - (i)]
2690#define VsrH(i) u16[7 - (i)]
2691#define VsrSH(i) s16[7 - (i)]
2692#define VsrW(i) u32[3 - (i)]
2693#define VsrSW(i) s32[3 - (i)]
2694#define VsrD(i) u64[1 - (i)]
2695#define VsrSD(i) s64[1 - (i)]
2696#define VsrHF(i) f16[7 - (i)]
2697#define VsrSF(i) f32[3 - (i)]
2698#define VsrDF(i) f64[1 - (i)]
2699#endif
2700
2701static inline int vsr64_offset(int i, bool high)
2702{
2703    return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2704}
2705
2706static inline int vsr_full_offset(int i)
2707{
2708    return offsetof(CPUPPCState, vsr[i].u64[0]);
2709}
2710
2711static inline int acc_full_offset(int i)
2712{
2713    return vsr_full_offset(i * 4);
2714}
2715
2716static inline int fpr_offset(int i)
2717{
2718    return vsr64_offset(i, true);
2719}
2720
2721static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2722{
2723    return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2724}
2725
2726static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2727{
2728    return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2729}
2730
2731static inline long avr64_offset(int i, bool high)
2732{
2733    return vsr64_offset(i + 32, high);
2734}
2735
2736static inline int avr_full_offset(int i)
2737{
2738    return vsr_full_offset(i + 32);
2739}
2740
2741static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2742{
2743    return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2744}
2745
2746static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2747{
2748    /* We can test whether the SPR is defined by checking for a valid name */
2749    return cpu->env.spr_cb[spr].name != NULL;
2750}
2751
2752#if !defined(CONFIG_USER_ONLY)
2753static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
2754{
2755    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2756    CPUPPCState *env = &cpu->env;
2757    bool ile;
2758
2759    if (hv && env->has_hv_mode) {
2760        if (is_isa300(pcc)) {
2761            ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
2762        } else {
2763            ile = !!(env->spr[SPR_HID0] & HID0_HILE);
2764        }
2765
2766    } else if (pcc->lpcr_mask & LPCR_ILE) {
2767        ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
2768    } else {
2769        ile = FIELD_EX64(env->msr, MSR, ILE);
2770    }
2771
2772    return ile;
2773}
2774#endif
2775
2776void dump_mmu(CPUPPCState *env);
2777
2778void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2779void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
2780uint32_t ppc_get_vscr(CPUPPCState *env);
2781void ppc_set_cr(CPUPPCState *env, uint64_t cr);
2782uint64_t ppc_get_cr(const CPUPPCState *env);
2783
2784/*****************************************************************************/
2785/* Power management enable checks                                            */
2786static inline int check_pow_none(CPUPPCState *env)
2787{
2788    return 0;
2789}
2790
2791static inline int check_pow_nocheck(CPUPPCState *env)
2792{
2793    return 1;
2794}
2795
2796/*****************************************************************************/
2797/* PowerPC implementations definitions                                       */
2798
2799#define POWERPC_FAMILY(_name)                                               \
2800    static void                                                             \
2801    glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2802                                                                            \
2803    static const TypeInfo                                                   \
2804    glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
2805        .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
2806        .parent = TYPE_POWERPC_CPU,                                         \
2807        .abstract = true,                                                   \
2808        .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
2809    };                                                                      \
2810                                                                            \
2811    static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
2812    {                                                                       \
2813        type_register_static(                                               \
2814            &glue(glue(ppc_, _name), _cpu_family_type_info));               \
2815    }                                                                       \
2816                                                                            \
2817    type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
2818                                                                            \
2819    static void glue(glue(ppc_, _name), _cpu_family_class_init)
2820
2821
2822#endif /* PPC_CPU_H */
2823