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19#include "qemu/osdep.h"
20#include "qemu/qemu-print.h"
21#include "qapi/error.h"
22#include "cpu.h"
23#include "migration/vmstate.h"
24#include "exec/exec-all.h"
25#include "hw/loader.h"
26#include "fpu/softfloat.h"
27#include "tcg/debug-assert.h"
28
29static void rx_cpu_set_pc(CPUState *cs, vaddr value)
30{
31 RXCPU *cpu = RX_CPU(cs);
32
33 cpu->env.pc = value;
34}
35
36static vaddr rx_cpu_get_pc(CPUState *cs)
37{
38 RXCPU *cpu = RX_CPU(cs);
39
40 return cpu->env.pc;
41}
42
43static void rx_cpu_synchronize_from_tb(CPUState *cs,
44 const TranslationBlock *tb)
45{
46 RXCPU *cpu = RX_CPU(cs);
47
48 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
49 cpu->env.pc = tb->pc;
50}
51
52static void rx_restore_state_to_opc(CPUState *cs,
53 const TranslationBlock *tb,
54 const uint64_t *data)
55{
56 RXCPU *cpu = RX_CPU(cs);
57
58 cpu->env.pc = data[0];
59}
60
61static bool rx_cpu_has_work(CPUState *cs)
62{
63 return cs->interrupt_request &
64 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
65}
66
67static void rx_cpu_reset_hold(Object *obj)
68{
69 RXCPU *cpu = RX_CPU(obj);
70 RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
71 CPURXState *env = &cpu->env;
72 uint32_t *resetvec;
73
74 if (rcc->parent_phases.hold) {
75 rcc->parent_phases.hold(obj);
76 }
77
78 memset(env, 0, offsetof(CPURXState, end_reset_fields));
79
80 resetvec = rom_ptr(0xfffffffc, 4);
81 if (resetvec) {
82
83 env->pc = ldl_p(resetvec);
84 }
85 rx_cpu_unpack_psw(env, 0, 1);
86 env->regs[0] = env->isp = env->usp = 0;
87 env->fpsw = 0;
88 set_flush_to_zero(1, &env->fp_status);
89 set_flush_inputs_to_zero(1, &env->fp_status);
90}
91
92static void rx_cpu_list_entry(gpointer data, gpointer user_data)
93{
94 ObjectClass *oc = data;
95
96 qemu_printf(" %s\n", object_class_get_name(oc));
97}
98
99void rx_cpu_list(void)
100{
101 GSList *list;
102 list = object_class_get_list_sorted(TYPE_RX_CPU, false);
103 qemu_printf("Available CPUs:\n");
104 g_slist_foreach(list, rx_cpu_list_entry, NULL);
105 g_slist_free(list);
106}
107
108static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
109{
110 ObjectClass *oc;
111 char *typename;
112
113 oc = object_class_by_name(cpu_model);
114 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
115 !object_class_is_abstract(oc)) {
116 return oc;
117 }
118 typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
119 oc = object_class_by_name(typename);
120 g_free(typename);
121 if (oc != NULL && object_class_is_abstract(oc)) {
122 oc = NULL;
123 }
124
125 return oc;
126}
127
128static void rx_cpu_realize(DeviceState *dev, Error **errp)
129{
130 CPUState *cs = CPU(dev);
131 RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
132 Error *local_err = NULL;
133
134 cpu_exec_realizefn(cs, &local_err);
135 if (local_err != NULL) {
136 error_propagate(errp, local_err);
137 return;
138 }
139
140 qemu_init_vcpu(cs);
141 cpu_reset(cs);
142
143 rcc->parent_realize(dev, errp);
144}
145
146static void rx_cpu_set_irq(void *opaque, int no, int request)
147{
148 RXCPU *cpu = opaque;
149 CPUState *cs = CPU(cpu);
150 int irq = request & 0xff;
151
152 static const int mask[] = {
153 [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
154 [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
155 };
156 if (irq) {
157 cpu->env.req_irq = irq;
158 cpu->env.req_ipl = (request >> 8) & 0x0f;
159 cpu_interrupt(cs, mask[no]);
160 } else {
161 cpu_reset_interrupt(cs, mask[no]);
162 }
163}
164
165static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
166{
167 info->mach = bfd_mach_rx;
168 info->print_insn = print_insn_rx;
169}
170
171static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
172 MMUAccessType access_type, int mmu_idx,
173 bool probe, uintptr_t retaddr)
174{
175 uint32_t address, physical, prot;
176
177
178 address = physical = addr & TARGET_PAGE_MASK;
179 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
180 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
181 return true;
182}
183
184static void rx_cpu_init(Object *obj)
185{
186 CPUState *cs = CPU(obj);
187 RXCPU *cpu = RX_CPU(obj);
188 CPURXState *env = &cpu->env;
189
190 cpu_set_cpustate_pointers(cpu);
191 cs->env_ptr = env;
192 qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
193}
194
195#ifndef CONFIG_USER_ONLY
196#include "hw/core/sysemu-cpu-ops.h"
197
198static const struct SysemuCPUOps rx_sysemu_ops = {
199 .get_phys_page_debug = rx_cpu_get_phys_page_debug,
200};
201#endif
202
203#include "hw/core/tcg-cpu-ops.h"
204
205static const struct TCGCPUOps rx_tcg_ops = {
206 .initialize = rx_translate_init,
207 .synchronize_from_tb = rx_cpu_synchronize_from_tb,
208 .restore_state_to_opc = rx_restore_state_to_opc,
209 .tlb_fill = rx_cpu_tlb_fill,
210
211#ifndef CONFIG_USER_ONLY
212 .cpu_exec_interrupt = rx_cpu_exec_interrupt,
213 .do_interrupt = rx_cpu_do_interrupt,
214#endif
215};
216
217static void rx_cpu_class_init(ObjectClass *klass, void *data)
218{
219 DeviceClass *dc = DEVICE_CLASS(klass);
220 CPUClass *cc = CPU_CLASS(klass);
221 RXCPUClass *rcc = RX_CPU_CLASS(klass);
222 ResettableClass *rc = RESETTABLE_CLASS(klass);
223
224 device_class_set_parent_realize(dc, rx_cpu_realize,
225 &rcc->parent_realize);
226 resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL,
227 &rcc->parent_phases);
228
229 cc->class_by_name = rx_cpu_class_by_name;
230 cc->has_work = rx_cpu_has_work;
231 cc->dump_state = rx_cpu_dump_state;
232 cc->set_pc = rx_cpu_set_pc;
233 cc->get_pc = rx_cpu_get_pc;
234
235#ifndef CONFIG_USER_ONLY
236 cc->sysemu_ops = &rx_sysemu_ops;
237#endif
238 cc->gdb_read_register = rx_cpu_gdb_read_register;
239 cc->gdb_write_register = rx_cpu_gdb_write_register;
240 cc->disas_set_info = rx_cpu_disas_set_info;
241
242 cc->gdb_num_core_regs = 26;
243 cc->gdb_core_xml_file = "rx-core.xml";
244 cc->tcg_ops = &rx_tcg_ops;
245}
246
247static const TypeInfo rx_cpu_info = {
248 .name = TYPE_RX_CPU,
249 .parent = TYPE_CPU,
250 .instance_size = sizeof(RXCPU),
251 .instance_init = rx_cpu_init,
252 .abstract = true,
253 .class_size = sizeof(RXCPUClass),
254 .class_init = rx_cpu_class_init,
255};
256
257static const TypeInfo rx62n_rx_cpu_info = {
258 .name = TYPE_RX62N_CPU,
259 .parent = TYPE_RX_CPU,
260};
261
262static void rx_cpu_register_types(void)
263{
264 type_register_static(&rx_cpu_info);
265 type_register_static(&rx62n_rx_cpu_info);
266}
267
268type_init(rx_cpu_register_types)
269
