qemu/hw/acpi/pcihp.c
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   1/*
   2 * QEMU<->ACPI BIOS PCI hotplug interface
   3 *
   4 * QEMU supports PCI hotplug via ACPI. This module
   5 * implements the interface between QEMU and the ACPI BIOS.
   6 * Interface specification - see docs/specs/acpi_pci_hotplug.txt
   7 *
   8 * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9 * Copyright (c) 2006 Fabrice Bellard
  10 *
  11 * This library is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU Lesser General Public
  13 * License version 2 as published by the Free Software Foundation.
  14 *
  15 * This library is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18 * Lesser General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU Lesser General Public
  21 * License along with this library; if not, see <http://www.gnu.org/licenses/>
  22 *
  23 * Contributions after 2012-01-13 are licensed under the terms of the
  24 * GNU GPL, version 2 or (at your option) any later version.
  25 */
  26
  27#include "qemu/osdep.h"
  28#include "hw/acpi/pcihp.h"
  29
  30#include "hw/hw.h"
  31#include "hw/i386/pc.h"
  32#include "hw/pci/pci.h"
  33#include "hw/acpi/acpi.h"
  34#include "sysemu/sysemu.h"
  35#include "exec/ioport.h"
  36#include "exec/address-spaces.h"
  37#include "hw/pci/pci_bus.h"
  38#include "qapi/error.h"
  39#include "qom/qom-qobject.h"
  40#include "qapi/qmp/qint.h"
  41
  42//#define DEBUG
  43
  44#ifdef DEBUG
  45# define ACPI_PCIHP_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  46#else
  47# define ACPI_PCIHP_DPRINTF(format, ...)     do { } while (0)
  48#endif
  49
  50#define ACPI_PCIHP_ADDR 0xae00
  51#define ACPI_PCIHP_SIZE 0x0014
  52#define ACPI_PCIHP_LEGACY_SIZE 0x000f
  53#define PCI_UP_BASE 0x0000
  54#define PCI_DOWN_BASE 0x0004
  55#define PCI_EJ_BASE 0x0008
  56#define PCI_RMV_BASE 0x000c
  57#define PCI_SEL_BASE 0x0010
  58
  59typedef struct AcpiPciHpFind {
  60    int bsel;
  61    PCIBus *bus;
  62} AcpiPciHpFind;
  63
  64static int acpi_pcihp_get_bsel(PCIBus *bus)
  65{
  66    Error *local_err = NULL;
  67    int64_t bsel = object_property_get_int(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
  68                                           &local_err);
  69
  70    if (local_err || bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
  71        if (local_err) {
  72            error_free(local_err);
  73        }
  74        return -1;
  75    } else {
  76        return bsel;
  77    }
  78}
  79
  80static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
  81{
  82    AcpiPciHpFind *find = opaque;
  83    if (find->bsel == acpi_pcihp_get_bsel(bus)) {
  84        find->bus = bus;
  85    }
  86}
  87
  88static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
  89{
  90    AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
  91
  92    if (bsel < 0) {
  93        return NULL;
  94    }
  95
  96    pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
  97
  98    /* Make bsel 0 eject root bus if bsel property is not set,
  99     * for compatibility with non acpi setups.
 100     * TODO: really needed?
 101     */
 102    if (!bsel && !find.bus) {
 103        find.bus = s->root;
 104    }
 105    return find.bus;
 106}
 107
 108static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
 109{
 110    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 111    DeviceClass *dc = DEVICE_GET_CLASS(dev);
 112    /*
 113     * ACPI doesn't allow hotplug of bridge devices.  Don't allow
 114     * hot-unplug of bridge devices unless they were added by hotplug
 115     * (and so, not described by acpi).
 116     */
 117    return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable;
 118}
 119
 120static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
 121{
 122    BusChild *kid, *next;
 123    int slot = ctz32(slots);
 124    PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
 125
 126    if (!bus) {
 127        return;
 128    }
 129
 130    /* Mark request as complete */
 131    s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
 132    s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
 133
 134    QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
 135        DeviceState *qdev = kid->child;
 136        PCIDevice *dev = PCI_DEVICE(qdev);
 137        if (PCI_SLOT(dev->devfn) == slot) {
 138            if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
 139                object_unparent(OBJECT(qdev));
 140            }
 141        }
 142    }
 143}
 144
 145static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
 146{
 147    BusChild *kid, *next;
 148    PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
 149
 150    /* Execute any pending removes during reset */
 151    while (s->acpi_pcihp_pci_status[bsel].down) {
 152        acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
 153    }
 154
 155    s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
 156
 157    if (!bus) {
 158        return;
 159    }
 160    QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
 161        DeviceState *qdev = kid->child;
 162        PCIDevice *pdev = PCI_DEVICE(qdev);
 163        int slot = PCI_SLOT(pdev->devfn);
 164
 165        if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
 166            s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
 167        }
 168    }
 169}
 170
 171static void acpi_pcihp_update(AcpiPciHpState *s)
 172{
 173    int i;
 174
 175    for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
 176        acpi_pcihp_update_hotplug_bus(s, i);
 177    }
 178}
 179
 180void acpi_pcihp_reset(AcpiPciHpState *s)
 181{
 182    acpi_pcihp_update(s);
 183}
 184
 185void acpi_pcihp_device_plug_cb(ACPIREGS *ar, qemu_irq irq, AcpiPciHpState *s,
 186                               DeviceState *dev, Error **errp)
 187{
 188    PCIDevice *pdev = PCI_DEVICE(dev);
 189    int slot = PCI_SLOT(pdev->devfn);
 190    int bsel = acpi_pcihp_get_bsel(pdev->bus);
 191    if (bsel < 0) {
 192        error_setg(errp, "Unsupported bus. Bus doesn't have property '"
 193                   ACPI_PCIHP_PROP_BSEL "' set");
 194        return;
 195    }
 196
 197    /* Don't send event when device is enabled during qemu machine creation:
 198     * it is present on boot, no hotplug event is necessary. We do send an
 199     * event when the device is disabled later. */
 200    if (!dev->hotplugged) {
 201        return;
 202    }
 203
 204    s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
 205
 206    acpi_send_gpe_event(ar, irq, ACPI_PCI_HOTPLUG_STATUS);
 207}
 208
 209void acpi_pcihp_device_unplug_cb(ACPIREGS *ar, qemu_irq irq, AcpiPciHpState *s,
 210                                 DeviceState *dev, Error **errp)
 211{
 212    PCIDevice *pdev = PCI_DEVICE(dev);
 213    int slot = PCI_SLOT(pdev->devfn);
 214    int bsel = acpi_pcihp_get_bsel(pdev->bus);
 215    if (bsel < 0) {
 216        error_setg(errp, "Unsupported bus. Bus doesn't have property '"
 217                   ACPI_PCIHP_PROP_BSEL "' set");
 218        return;
 219    }
 220
 221    s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
 222
 223    acpi_send_gpe_event(ar, irq, ACPI_PCI_HOTPLUG_STATUS);
 224}
 225
 226static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
 227{
 228    AcpiPciHpState *s = opaque;
 229    uint32_t val = 0;
 230    int bsel = s->hotplug_select;
 231
 232    if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
 233        return 0;
 234    }
 235
 236    switch (addr) {
 237    case PCI_UP_BASE:
 238        val = s->acpi_pcihp_pci_status[bsel].up;
 239        if (!s->legacy_piix) {
 240            s->acpi_pcihp_pci_status[bsel].up = 0;
 241        }
 242        ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
 243        break;
 244    case PCI_DOWN_BASE:
 245        val = s->acpi_pcihp_pci_status[bsel].down;
 246        ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
 247        break;
 248    case PCI_EJ_BASE:
 249        /* No feature defined yet */
 250        ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
 251        break;
 252    case PCI_RMV_BASE:
 253        val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
 254        ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
 255        break;
 256    case PCI_SEL_BASE:
 257        val = s->hotplug_select;
 258        ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
 259    default:
 260        break;
 261    }
 262
 263    return val;
 264}
 265
 266static void pci_write(void *opaque, hwaddr addr, uint64_t data,
 267                      unsigned int size)
 268{
 269    AcpiPciHpState *s = opaque;
 270    switch (addr) {
 271    case PCI_EJ_BASE:
 272        if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
 273            break;
 274        }
 275        acpi_pcihp_eject_slot(s, s->hotplug_select, data);
 276        ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
 277                      addr, data);
 278        break;
 279    case PCI_SEL_BASE:
 280        s->hotplug_select = data;
 281        ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
 282                      addr, data);
 283    default:
 284        break;
 285    }
 286}
 287
 288static const MemoryRegionOps acpi_pcihp_io_ops = {
 289    .read = pci_read,
 290    .write = pci_write,
 291    .endianness = DEVICE_LITTLE_ENDIAN,
 292    .valid = {
 293        .min_access_size = 4,
 294        .max_access_size = 4,
 295    },
 296};
 297
 298void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
 299                     MemoryRegion *address_space_io, bool bridges_enabled)
 300{
 301    s->io_len = ACPI_PCIHP_SIZE;
 302    s->io_base = ACPI_PCIHP_ADDR;
 303
 304    s->root= root_bus;
 305    s->legacy_piix = !bridges_enabled;
 306
 307    if (s->legacy_piix) {
 308        unsigned *bus_bsel = g_malloc(sizeof *bus_bsel);
 309
 310        s->io_len = ACPI_PCIHP_LEGACY_SIZE;
 311
 312        *bus_bsel = ACPI_PCIHP_BSEL_DEFAULT;
 313        object_property_add_uint32_ptr(OBJECT(root_bus), ACPI_PCIHP_PROP_BSEL,
 314                                       bus_bsel, NULL);
 315    }
 316
 317    memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
 318                          "acpi-pci-hotplug", s->io_len);
 319    memory_region_add_subregion(address_space_io, s->io_base, &s->io);
 320
 321    object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
 322                                   &error_abort);
 323    object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
 324                                   &error_abort);
 325}
 326
 327const VMStateDescription vmstate_acpi_pcihp_pci_status = {
 328    .name = "acpi_pcihp_pci_status",
 329    .version_id = 1,
 330    .minimum_version_id = 1,
 331    .fields = (VMStateField[]) {
 332        VMSTATE_UINT32(up, AcpiPciHpPciStatus),
 333        VMSTATE_UINT32(down, AcpiPciHpPciStatus),
 334        VMSTATE_END_OF_LIST()
 335    }
 336};
 337