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22#include "qemu/osdep.h"
23#include "qapi/error.h"
24#include "qemu-common.h"
25#include "cpu.h"
26#include "hw/arm/fsl-imx31.h"
27#include "sysemu/sysemu.h"
28#include "exec/address-spaces.h"
29#include "hw/boards.h"
30#include "sysemu/char.h"
31
32static void fsl_imx31_init(Object *obj)
33{
34 FslIMX31State *s = FSL_IMX31(obj);
35 int i;
36
37 object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
38
39 object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
40 qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
41
42 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
43 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
44
45 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
46 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
47 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
48 }
49
50 object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
51 qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
52
53 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
54 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
55 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
56 }
57
58 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
59 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
60 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
61 }
62
63 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
64 object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
65 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
66 }
67}
68
69static void fsl_imx31_realize(DeviceState *dev, Error **errp)
70{
71 FslIMX31State *s = FSL_IMX31(dev);
72 uint16_t i;
73 Error *err = NULL;
74
75 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
76 if (err) {
77 error_propagate(errp, err);
78 return;
79 }
80
81 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
82 if (err) {
83 error_propagate(errp, err);
84 return;
85 }
86 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
87 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
88 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
89 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
90 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
91
92 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
93 if (err) {
94 error_propagate(errp, err);
95 return;
96 }
97 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
98
99
100 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
101 static const struct {
102 hwaddr addr;
103 unsigned int irq;
104 } serial_table[FSL_IMX31_NUM_UARTS] = {
105 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
106 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
107 };
108
109 if (i < MAX_SERIAL_PORTS) {
110 CharDriverState *chr;
111
112 chr = serial_hds[i];
113
114 if (!chr) {
115 char label[20];
116 snprintf(label, sizeof(label), "imx31.uart%d", i);
117 chr = qemu_chr_new(label, "null", NULL);
118 }
119
120 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
121 }
122
123 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
124 if (err) {
125 error_propagate(errp, err);
126 return;
127 }
128
129 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
130 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
131 qdev_get_gpio_in(DEVICE(&s->avic),
132 serial_table[i].irq));
133 }
134
135 s->gpt.ccm = IMX_CCM(&s->ccm);
136
137 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
138 if (err) {
139 error_propagate(errp, err);
140 return;
141 }
142
143 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
144 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
145 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
146
147
148 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
149 static const struct {
150 hwaddr addr;
151 unsigned int irq;
152 } epit_table[FSL_IMX31_NUM_EPITS] = {
153 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
154 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
155 };
156
157 s->epit[i].ccm = IMX_CCM(&s->ccm);
158
159 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
160 if (err) {
161 error_propagate(errp, err);
162 return;
163 }
164
165 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
166 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
167 qdev_get_gpio_in(DEVICE(&s->avic),
168 epit_table[i].irq));
169 }
170
171
172 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
173 static const struct {
174 hwaddr addr;
175 unsigned int irq;
176 } i2c_table[FSL_IMX31_NUM_I2CS] = {
177 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
178 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
179 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
180 };
181
182
183 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
184 if (err) {
185 error_propagate(errp, err);
186 return;
187 }
188
189 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
190
191 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
192 qdev_get_gpio_in(DEVICE(&s->avic),
193 i2c_table[i].irq));
194 }
195
196
197 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
198 static const struct {
199 hwaddr addr;
200 unsigned int irq;
201 } gpio_table[FSL_IMX31_NUM_GPIOS] = {
202 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
203 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
204 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
205 };
206
207 object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
208 &error_abort);
209 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
210 if (err) {
211 error_propagate(errp, err);
212 return;
213 }
214 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
215
216 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
217 qdev_get_gpio_in(DEVICE(&s->avic),
218 gpio_table[i].irq));
219 }
220
221
222 memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL,
223 "imx31.secure_rom",
224 FSL_IMX31_SECURE_ROM_SIZE, &err);
225 if (err) {
226 error_propagate(errp, err);
227 return;
228 }
229 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
230 &s->secure_rom);
231
232
233 memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx31.rom",
234 FSL_IMX31_ROM_SIZE, &err);
235 if (err) {
236 error_propagate(errp, err);
237 return;
238 }
239 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
240 &s->rom);
241
242
243 memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
244 &err);
245 if (err) {
246 error_propagate(errp, err);
247 return;
248 }
249 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
250 &s->iram);
251 vmstate_register_ram_global(&s->iram);
252
253
254 memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
255 &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
256 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
257 &s->iram_alias);
258}
259
260static void fsl_imx31_class_init(ObjectClass *oc, void *data)
261{
262 DeviceClass *dc = DEVICE_CLASS(oc);
263
264 dc->realize = fsl_imx31_realize;
265
266
267
268
269
270 dc->cannot_destroy_with_object_finalize_yet = true;
271 dc->desc = "i.MX31 SOC";
272}
273
274static const TypeInfo fsl_imx31_type_info = {
275 .name = TYPE_FSL_IMX31,
276 .parent = TYPE_DEVICE,
277 .instance_size = sizeof(FslIMX31State),
278 .instance_init = fsl_imx31_init,
279 .class_init = fsl_imx31_class_init,
280};
281
282static void fsl_imx31_register_types(void)
283{
284 type_register_static(&fsl_imx31_type_info);
285}
286
287type_init(fsl_imx31_register_types)
288
