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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "qemu/cutils.h"
24#include "sysemu/sysemu.h"
25#include "hw/arm/omap.h"
26#include "hw/arm/arm.h"
27#include "hw/irq.h"
28#include "ui/console.h"
29#include "hw/boards.h"
30#include "hw/i2c/i2c.h"
31#include "hw/devices.h"
32#include "hw/block/flash.h"
33#include "hw/hw.h"
34#include "hw/bt.h"
35#include "hw/loader.h"
36#include "sysemu/block-backend.h"
37#include "hw/sysbus.h"
38#include "exec/address-spaces.h"
39
40
41struct n800_s {
42 struct omap_mpu_state_s *mpu;
43
44 struct rfbi_chip_s blizzard;
45 struct {
46 void *opaque;
47 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
48 uWireSlave *chip;
49 } ts;
50
51 int keymap[0x80];
52 DeviceState *kbd;
53
54 DeviceState *usb;
55 void *retu;
56 void *tahvo;
57 DeviceState *nand;
58};
59
60
61#define N8X0_TUSB_ENABLE_GPIO 0
62#define N800_MMC2_WP_GPIO 8
63#define N800_UNKNOWN_GPIO0 9
64#define N810_MMC2_VIOSD_GPIO 9
65#define N810_HEADSET_AMP_GPIO 10
66#define N800_CAM_TURN_GPIO 12
67#define N810_GPS_RESET_GPIO 12
68#define N800_BLIZZARD_POWERDOWN_GPIO 15
69#define N800_MMC1_WP_GPIO 23
70#define N810_MMC2_VSD_GPIO 23
71#define N8X0_ONENAND_GPIO 26
72#define N810_BLIZZARD_RESET_GPIO 30
73#define N800_UNKNOWN_GPIO2 53
74#define N8X0_TUSB_INT_GPIO 58
75#define N8X0_BT_WKUP_GPIO 61
76#define N8X0_STI_GPIO 62
77#define N8X0_CBUS_SEL_GPIO 64
78#define N8X0_CBUS_DAT_GPIO 65
79#define N8X0_CBUS_CLK_GPIO 66
80#define N8X0_WLAN_IRQ_GPIO 87
81#define N8X0_BT_RESET_GPIO 92
82#define N8X0_TEA5761_CS_GPIO 93
83#define N800_UNKNOWN_GPIO 94
84#define N810_TSC_RESET_GPIO 94
85#define N800_CAM_ACT_GPIO 95
86#define N810_GPS_WAKEUP_GPIO 95
87#define N8X0_MMC_CS_GPIO 96
88#define N8X0_WLAN_PWR_GPIO 97
89#define N8X0_BT_HOST_WKUP_GPIO 98
90#define N810_SPEAKER_AMP_GPIO 101
91#define N810_KB_LOCK_GPIO 102
92#define N800_TSC_TS_GPIO 103
93#define N810_TSC_TS_GPIO 106
94#define N8X0_HEADPHONE_GPIO 107
95#define N8X0_RETU_GPIO 108
96#define N800_TSC_KP_IRQ_GPIO 109
97#define N810_KEYBOARD_GPIO 109
98#define N800_BAT_COVER_GPIO 110
99#define N810_SLIDE_GPIO 110
100#define N8X0_TAHVO_GPIO 111
101#define N800_UNKNOWN_GPIO4 112
102#define N810_SLEEPX_LED_GPIO 112
103#define N800_TSC_RESET_GPIO 118
104#define N810_AIC33_RESET_GPIO 118
105#define N800_TSC_UNKNOWN_GPIO 119
106#define N8X0_TMP105_GPIO 125
107
108
109#define BT_UART 0
110#define XLDR_LL_UART 1
111
112
113#define N810_TLV320AIC33_ADDR 0x18
114#define N8X0_TCM825x_ADDR 0x29
115#define N810_LP5521_ADDR 0x32
116#define N810_TSL2563_ADDR 0x3d
117#define N810_LM8323_ADDR 0x45
118
119#define N8X0_TMP105_ADDR 0x48
120#define N8X0_MENELAUS_ADDR 0x72
121
122
123#define N8X0_ONENAND_CS 0
124#define N8X0_USB_ASYNC_CS 1
125#define N8X0_USB_SYNC_CS 4
126
127#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
128
129static void n800_mmc_cs_cb(void *opaque, int line, int level)
130{
131
132
133 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
134}
135
136static void n8x0_gpio_setup(struct n800_s *s)
137{
138 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO,
139 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0));
140 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
141}
142
143#define MAEMO_CAL_HEADER(...) \
144 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
145 __VA_ARGS__, \
146 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
147
148static const uint8_t n8x0_cal_wlan_mac[] = {
149 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
150 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
151 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
153 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
154 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
155};
156
157static const uint8_t n8x0_cal_bt_id[] = {
158 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
159 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
160 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
161 N8X0_BD_ADDR,
162};
163
164static void n8x0_nand_setup(struct n800_s *s)
165{
166 char *otp_region;
167 DriveInfo *dinfo;
168
169 s->nand = qdev_create(NULL, "onenand");
170 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
171
172 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
173 qdev_prop_set_uint16(s->nand, "version_id", 0);
174 qdev_prop_set_int32(s->nand, "shift", 1);
175 dinfo = drive_get(IF_MTD, 0, 0);
176 if (dinfo) {
177 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
178 &error_fatal);
179 }
180 qdev_init_nofail(s->nand);
181 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
182 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
183 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
184 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
185 otp_region = onenand_raw_otp(s->nand);
186
187 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
188 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
189
190}
191
192static qemu_irq n8x0_system_powerdown;
193
194static void n8x0_powerdown_req(Notifier *n, void *opaque)
195{
196 qemu_irq_raise(n8x0_system_powerdown);
197}
198
199static Notifier n8x0_system_powerdown_notifier = {
200 .notify = n8x0_powerdown_req
201};
202
203static void n8x0_i2c_setup(struct n800_s *s)
204{
205 DeviceState *dev;
206 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
207 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
208
209
210 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
211 qdev_connect_gpio_out(dev, 3,
212 qdev_get_gpio_in(s->mpu->ih[0],
213 OMAP_INT_24XX_SYS_NIRQ));
214
215 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
216 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
217
218
219 dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
220 qdev_connect_gpio_out(dev, 0, tmp_irq);
221}
222
223
224static MouseTransformInfo n800_pointercal = {
225 .x = 800,
226 .y = 480,
227 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
228};
229
230static MouseTransformInfo n810_pointercal = {
231 .x = 800,
232 .y = 480,
233 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
234};
235
236#define RETU_KEYCODE 61
237
238static void n800_key_event(void *opaque, int keycode)
239{
240 struct n800_s *s = (struct n800_s *) opaque;
241 int code = s->keymap[keycode & 0x7f];
242
243 if (code == -1) {
244 if ((keycode & 0x7f) == RETU_KEYCODE) {
245 retu_key_event(s->retu, !(keycode & 0x80));
246 }
247 return;
248 }
249
250 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
251}
252
253static const int n800_keys[16] = {
254 -1,
255 72,
256 63,
257 -1,
258 75,
259 28,
260 77,
261 -1,
262 1,
263 80,
264 62,
265 -1,
266 66,
267 64,
268 65,
269 -1,
270};
271
272static void n800_tsc_kbd_setup(struct n800_s *s)
273{
274 int i;
275
276
277
278 qemu_irq penirq = NULL;
279 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
280 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
281
282 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
283 s->ts.opaque = s->ts.chip->opaque;
284 s->ts.txrx = tsc210x_txrx;
285
286 for (i = 0; i < 0x80; i++) {
287 s->keymap[i] = -1;
288 }
289 for (i = 0; i < 0x10; i++) {
290 if (n800_keys[i] >= 0) {
291 s->keymap[n800_keys[i]] = i;
292 }
293 }
294
295 qemu_add_kbd_event_handler(n800_key_event, s);
296
297 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
298}
299
300static void n810_tsc_setup(struct n800_s *s)
301{
302 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
303
304 s->ts.opaque = tsc2005_init(pintdav);
305 s->ts.txrx = tsc2005_txrx;
306
307 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
308}
309
310
311static void n810_key_event(void *opaque, int keycode)
312{
313 struct n800_s *s = (struct n800_s *) opaque;
314 int code = s->keymap[keycode & 0x7f];
315
316 if (code == -1) {
317 if ((keycode & 0x7f) == RETU_KEYCODE) {
318 retu_key_event(s->retu, !(keycode & 0x80));
319 }
320 return;
321 }
322
323 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
324}
325
326#define M 0
327
328static int n810_keys[0x80] = {
329 [0x01] = 16,
330 [0x02] = 37,
331 [0x03] = 24,
332 [0x04] = 25,
333 [0x05] = 14,
334 [0x06] = 30,
335 [0x07] = 31,
336 [0x08] = 32,
337 [0x09] = 33,
338 [0x0a] = 34,
339 [0x0b] = 35,
340 [0x0c] = 36,
341
342 [0x11] = 17,
343 [0x12] = 62,
344 [0x13] = 38,
345 [0x14] = 40,
346 [0x16] = 44,
347 [0x17] = 45,
348 [0x18] = 46,
349 [0x19] = 47,
350 [0x1a] = 48,
351 [0x1b] = 49,
352 [0x1c] = 42,
353 [0x1f] = 65,
354
355 [0x21] = 18,
356 [0x22] = 39,
357 [0x23] = 12,
358 [0x24] = 13,
359 [0x2b] = 56,
360 [0x2c] = 50,
361 [0x2f] = 66,
362
363 [0x31] = 19,
364 [0x32] = 29 | M,
365 [0x34] = 57,
366 [0x35] = 51,
367 [0x37] = 72 | M,
368 [0x3c] = 82 | M,
369 [0x3f] = 64,
370
371 [0x41] = 20,
372 [0x44] = 52,
373 [0x46] = 77 | M,
374 [0x4f] = 63,
375 [0x51] = 21,
376 [0x53] = 80 | M,
377 [0x55] = 28,
378 [0x5f] = 1,
379
380 [0x61] = 22,
381 [0x64] = 75 | M,
382
383 [0x71] = 23,
384#if 0
385 [0x75] = 28 | M,
386#else
387 [0x75] = 15,
388#endif
389};
390
391#undef M
392
393static void n810_kbd_setup(struct n800_s *s)
394{
395 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
396 int i;
397
398 for (i = 0; i < 0x80; i++) {
399 s->keymap[i] = -1;
400 }
401 for (i = 0; i < 0x80; i++) {
402 if (n810_keys[i] > 0) {
403 s->keymap[n810_keys[i]] = i;
404 }
405 }
406
407 qemu_add_kbd_event_handler(n810_key_event, s);
408
409
410
411 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
412 "lm8323", N810_LM8323_ADDR);
413 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
414}
415
416
417struct mipid_s {
418 int resp[4];
419 int param[4];
420 int p;
421 int pm;
422 int cmd;
423
424 int sleep;
425 int booster;
426 int te;
427 int selfcheck;
428 int partial;
429 int normal;
430 int vscr;
431 int invert;
432 int onoff;
433 int gamma;
434 uint32_t id;
435};
436
437static void mipid_reset(struct mipid_s *s)
438{
439 s->pm = 0;
440 s->cmd = 0;
441
442 s->sleep = 1;
443 s->booster = 0;
444 s->selfcheck =
445 (1 << 7) |
446 (1 << 5) |
447 (1 << 4);
448 s->te = 0;
449 s->partial = 0;
450 s->normal = 1;
451 s->vscr = 0;
452 s->invert = 0;
453 s->onoff = 1;
454 s->gamma = 0;
455}
456
457static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
458{
459 struct mipid_s *s = (struct mipid_s *) opaque;
460 uint8_t ret;
461
462 if (len > 9) {
463 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
464 }
465
466 if (s->p >= ARRAY_SIZE(s->resp)) {
467 ret = 0;
468 } else {
469 ret = s->resp[s->p++];
470 }
471 if (s->pm-- > 0) {
472 s->param[s->pm] = cmd;
473 } else {
474 s->cmd = cmd;
475 }
476
477 switch (s->cmd) {
478 case 0x00:
479 break;
480
481 case 0x01:
482 mipid_reset(s);
483 break;
484
485 case 0x02:
486 s->booster = 0;
487 break;
488 case 0x03:
489 s->booster = 1;
490 break;
491
492 case 0x04:
493 s->p = 0;
494 s->resp[0] = (s->id >> 16) & 0xff;
495 s->resp[1] = (s->id >> 8) & 0xff;
496 s->resp[2] = (s->id >> 0) & 0xff;
497 break;
498
499 case 0x06:
500 case 0x07:
501
502
503 case 0x08:
504 s->p = 0;
505
506 s->resp[0] = 0x01;
507 break;
508
509 case 0x09:
510 s->p = 0;
511 s->resp[0] = s->booster << 7;
512 s->resp[1] = (5 << 4) | (s->partial << 2) |
513 (s->sleep << 1) | s->normal;
514 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
515 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
516 s->resp[3] = s->gamma << 6;
517 break;
518
519 case 0x0a:
520 s->p = 0;
521 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
522 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
523 break;
524 case 0x0b:
525 s->p = 0;
526 s->resp[0] = 0;
527 break;
528 case 0x0c:
529 s->p = 0;
530 s->resp[0] = 5;
531 break;
532 case 0x0d:
533 s->p = 0;
534 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
535 break;
536 case 0x0e:
537 s->p = 0;
538 s->resp[0] = s->te << 7;
539 break;
540 case 0x0f:
541 s->p = 0;
542 s->resp[0] = s->selfcheck;
543 break;
544
545 case 0x10:
546 s->sleep = 1;
547 break;
548 case 0x11:
549 s->sleep = 0;
550 s->selfcheck ^= 1 << 6;
551 break;
552
553 case 0x12:
554 s->partial = 1;
555 s->normal = 0;
556 s->vscr = 0;
557 break;
558 case 0x13:
559 s->partial = 0;
560 s->normal = 1;
561 s->vscr = 0;
562 break;
563
564 case 0x20:
565 s->invert = 0;
566 break;
567 case 0x21:
568 s->invert = 1;
569 break;
570
571 case 0x22:
572 case 0x23:
573 goto bad_cmd;
574
575 case 0x25:
576 if (s->pm < 0) {
577 s->pm = 1;
578 }
579 goto bad_cmd;
580
581 case 0x26:
582 if (!s->pm) {
583 s->gamma = ctz32(s->param[0] & 0xf);
584 if (s->gamma == 32) {
585 s->gamma = -1;
586 }
587 } else if (s->pm < 0) {
588 s->pm = 1;
589 }
590 break;
591
592 case 0x28:
593 s->onoff = 0;
594 break;
595 case 0x29:
596 s->onoff = 1;
597 break;
598
599 case 0x2a:
600 case 0x2b:
601 case 0x2c:
602 case 0x2d:
603 case 0x2e:
604 case 0x30:
605 case 0x33:
606 goto bad_cmd;
607
608 case 0x34:
609 s->te = 0;
610 break;
611 case 0x35:
612 if (!s->pm) {
613 s->te = 1;
614 } else if (s->pm < 0) {
615 s->pm = 1;
616 }
617 break;
618
619 case 0x36:
620 goto bad_cmd;
621
622 case 0x37:
623 s->partial = 0;
624 s->normal = 0;
625 s->vscr = 1;
626 break;
627
628 case 0x38:
629 case 0x39:
630 case 0x3a:
631 goto bad_cmd;
632
633 case 0xb0:
634 case 0xb1:
635 if (s->pm < 0) {
636 s->pm = 2;
637 }
638 break;
639
640 case 0xb4:
641 break;
642
643 case 0xb5:
644 case 0xb6:
645 case 0xb7:
646 case 0xb8:
647 case 0xba:
648 case 0xbb:
649 goto bad_cmd;
650
651 case 0xbd:
652 s->p = 0;
653 s->resp[0] = 0;
654 s->resp[1] = 1;
655 break;
656
657 case 0xc2:
658 if (s->pm < 0) {
659 s->pm = 2;
660 }
661 break;
662
663 case 0xc6:
664 case 0xc7:
665 case 0xd0:
666 case 0xd1:
667 case 0xd4:
668 case 0xd5:
669 goto bad_cmd;
670
671 case 0xda:
672 s->p = 0;
673 s->resp[0] = (s->id >> 16) & 0xff;
674 break;
675 case 0xdb:
676 s->p = 0;
677 s->resp[0] = (s->id >> 8) & 0xff;
678 break;
679 case 0xdc:
680 s->p = 0;
681 s->resp[0] = (s->id >> 0) & 0xff;
682 break;
683
684 default:
685 bad_cmd:
686 qemu_log_mask(LOG_GUEST_ERROR,
687 "%s: unknown command %02x\n", __func__, s->cmd);
688 break;
689 }
690
691 return ret;
692}
693
694static void *mipid_init(void)
695{
696 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
697
698 s->id = 0x838f03;
699 mipid_reset(s);
700
701 return s;
702}
703
704static void n8x0_spi_setup(struct n800_s *s)
705{
706 void *tsc = s->ts.opaque;
707 void *mipid = mipid_init();
708
709 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
710 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
711}
712
713
714
715static void n800_dss_init(struct rfbi_chip_s *chip)
716{
717 uint8_t *fb_blank;
718
719 chip->write(chip->opaque, 0, 0x2a);
720 chip->write(chip->opaque, 1, 0x64);
721 chip->write(chip->opaque, 0, 0x2c);
722 chip->write(chip->opaque, 1, 0x1e);
723 chip->write(chip->opaque, 0, 0x2e);
724 chip->write(chip->opaque, 1, 0xe0);
725 chip->write(chip->opaque, 0, 0x30);
726 chip->write(chip->opaque, 1, 0x01);
727 chip->write(chip->opaque, 0, 0x32);
728 chip->write(chip->opaque, 1, 0x06);
729 chip->write(chip->opaque, 0, 0x68);
730 chip->write(chip->opaque, 1, 1);
731
732 chip->write(chip->opaque, 0, 0x6c);
733 chip->write(chip->opaque, 1, 0x00);
734 chip->write(chip->opaque, 1, 0x00);
735 chip->write(chip->opaque, 1, 0x00);
736 chip->write(chip->opaque, 1, 0x00);
737 chip->write(chip->opaque, 1, 0x1f);
738 chip->write(chip->opaque, 1, 0x03);
739 chip->write(chip->opaque, 1, 0xdf);
740 chip->write(chip->opaque, 1, 0x01);
741 chip->write(chip->opaque, 1, 0x00);
742 chip->write(chip->opaque, 1, 0x00);
743 chip->write(chip->opaque, 1, 0x00);
744 chip->write(chip->opaque, 1, 0x00);
745 chip->write(chip->opaque, 1, 0x1f);
746 chip->write(chip->opaque, 1, 0x03);
747 chip->write(chip->opaque, 1, 0xdf);
748 chip->write(chip->opaque, 1, 0x01);
749 chip->write(chip->opaque, 1, 0x01);
750 chip->write(chip->opaque, 1, 0x01);
751
752 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
753
754 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
755 g_free(fb_blank);
756}
757
758static void n8x0_dss_setup(struct n800_s *s)
759{
760 s->blizzard.opaque = s1d13745_init(NULL);
761 s->blizzard.block = s1d13745_write_block;
762 s->blizzard.write = s1d13745_write;
763 s->blizzard.read = s1d13745_read;
764
765 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
766}
767
768static void n8x0_cbus_setup(struct n800_s *s)
769{
770 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
771 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
772 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
773
774 CBus *cbus = cbus_init(dat_out);
775
776 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
777 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
778 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
779
780 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
781 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
782}
783
784static void n8x0_uart_setup(struct n800_s *s)
785{
786 CharDriverState *radio = uart_hci_init(
787 qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
788
789 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
790 csrhci_pins_get(radio)[csrhci_pin_reset]);
791 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
792 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
793
794 omap_uart_attach(s->mpu->uart[BT_UART], radio);
795}
796
797static void n8x0_usb_setup(struct n800_s *s)
798{
799 SysBusDevice *dev;
800 s->usb = qdev_create(NULL, "tusb6010");
801 dev = SYS_BUS_DEVICE(s->usb);
802 qdev_init_nofail(s->usb);
803 sysbus_connect_irq(dev, 0,
804 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
805
806 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
807 sysbus_mmio_get_region(dev, 0));
808 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
809 sysbus_mmio_get_region(dev, 1));
810 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
811 qdev_get_gpio_in(s->usb, 0));
812}
813
814
815
816
817static uint32_t n800_pinout[104] = {
818 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
819 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
820 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
821 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
822 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
823 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
824 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
825 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
826 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
827 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
828 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
829 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
830 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
831 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
832 0x00000000, 0x00000038, 0x00340000, 0x00000000,
833 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
834 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
835 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
836 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
837 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
838 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
839 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
840 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
841 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
842 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
843 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
844};
845
846static void n800_setup_nolo_tags(void *sram_base)
847{
848 int i;
849 uint32_t *p = sram_base + 0x8000;
850 uint32_t *v = sram_base + 0xa000;
851
852 memset(p, 0, 0x3000);
853
854 strcpy((void *) (p + 0), "QEMU N800");
855
856 strcpy((void *) (p + 8), "F5");
857
858 stl_p(p + 10, 0x04f70000);
859 strcpy((void *) (p + 9), "RX-34");
860
861
862 stl_p(p + 12, 0x80);
863
864
865 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000);
866
867
868 p = sram_base + 0x9000;
869#define ADD_TAG(tag, len) \
870 stw_p((uint16_t *) p + 0, tag); \
871 stw_p((uint16_t *) p + 1, len); p++; \
872 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
873
874
875 ADD_TAG(0x6e01, 414);
876 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) {
877 stl_p(v++, n800_pinout[i]);
878 }
879
880
881 ADD_TAG(0x6e05, 1);
882 stl_p(v++, 2);
883
884
885 ADD_TAG(0x6e02, 4);
886 stl_p(v++, XLDR_LL_UART);
887
888#if 0
889
890 ADD_TAG(0x6e03, 6);
891 stw_p((uint16_t *) v + 0, 65);
892 stw_p((uint16_t *) v + 1, 66);
893 stw_p((uint16_t *) v + 2, 64);
894 v += 2;
895#endif
896
897
898 ADD_TAG(0x6e0a, 4);
899 stw_p((uint16_t *) v + 0, 111);
900 stw_p((uint16_t *) v + 1, 108);
901 v++;
902
903
904 ADD_TAG(0x6e04, 4);
905 stw_p((uint16_t *) v + 0, 30);
906 stw_p((uint16_t *) v + 1, 24);
907 v++;
908
909#if 0
910
911 ADD_TAG(0x6e06, 2);
912 stw_p((uint16_t *) (v++), 15);
913#endif
914
915
916 ADD_TAG(0x6e07, 4);
917 stl_p(v++, 0x00720000);
918
919
920 ADD_TAG(0x6e0b, 6);
921 stw_p((uint16_t *) v + 0, 94);
922 stw_p((uint16_t *) v + 1, 23);
923 stw_p((uint16_t *) v + 2, 0);
924 v += 2;
925
926
927 ADD_TAG(0x6e0c, 80);
928 strcpy((void *) v, "bat_cover"); v += 3;
929 stw_p((uint16_t *) v + 0, 110);
930 stw_p((uint16_t *) v + 1, 1);
931 v += 2;
932 strcpy((void *) v, "cam_act"); v += 3;
933 stw_p((uint16_t *) v + 0, 95);
934 stw_p((uint16_t *) v + 1, 32);
935 v += 2;
936 strcpy((void *) v, "cam_turn"); v += 3;
937 stw_p((uint16_t *) v + 0, 12);
938 stw_p((uint16_t *) v + 1, 33);
939 v += 2;
940 strcpy((void *) v, "headphone"); v += 3;
941 stw_p((uint16_t *) v + 0, 107);
942 stw_p((uint16_t *) v + 1, 17);
943 v += 2;
944
945
946 ADD_TAG(0x6e0e, 12);
947 stl_p(v++, 0x5c623d01);
948 stl_p(v++, 0x00000201);
949 stl_p(v++, 0x00000000);
950
951
952 ADD_TAG(0x6e0f, 8);
953 stl_p(v++, 0x00610025);
954 stl_p(v++, 0xffff0057);
955
956
957 ADD_TAG(0x6e10, 12);
958 stl_p(v++, 0xffff000f);
959 stl_p(v++, 0xffffffff);
960 stl_p(v++, 0x00000060);
961
962
963 ADD_TAG(0x6e11, 10);
964 stl_p(v++, 0x00000401);
965 stl_p(v++, 0x0002003a);
966 stl_p(v++, 0x00000002);
967
968
969 ADD_TAG(0x6e12, 2);
970 stl_p(v++, 93);
971
972#if 0
973
974 ADD_TAG(6e09, 0);
975
976
977 ADD_TAG(6e12, 0);
978#endif
979
980
981 stl_p(p++, 0x00000000);
982 stl_p(p++, 0x00000000);
983}
984
985
986
987static void n800_gpmc_init(struct n800_s *s)
988{
989 uint32_t config7 =
990 (0xf << 8) |
991 (1 << 6) |
992 (4 << 0);
993
994 cpu_physical_memory_write(0x6800a078,
995 &config7, sizeof(config7));
996}
997
998
999static void n8x0_boot_init(void *opaque)
1000{
1001 struct n800_s *s = (struct n800_s *) opaque;
1002 uint32_t buf;
1003
1004
1005#define omap_writel(addr, val) \
1006 buf = (val); \
1007 cpu_physical_memory_write(addr, &buf, sizeof(buf))
1008
1009 omap_writel(0x48008060, 0x41);
1010 omap_writel(0x48008070, 1);
1011 omap_writel(0x48008078, 0);
1012 omap_writel(0x48008090, 0);
1013 omap_writel(0x48008094, 0);
1014 omap_writel(0x48008098, 0);
1015 omap_writel(0x48008140, 2);
1016 omap_writel(0x48008148, 0);
1017 omap_writel(0x48008158, 1);
1018 omap_writel(0x480081c8, 0x15);
1019 omap_writel(0x480081d4, 0x1d4);
1020 omap_writel(0x480081d8, 0);
1021 omap_writel(0x480081dc, 0);
1022 omap_writel(0x480081e0, 0xc);
1023 omap_writel(0x48008200, 0x047e7ff7);
1024 omap_writel(0x48008204, 0x00000004);
1025 omap_writel(0x48008210, 0x047e7ff1);
1026 omap_writel(0x48008214, 0x00000004);
1027 omap_writel(0x4800821c, 0x00000000);
1028 omap_writel(0x48008230, 0);
1029 omap_writel(0x48008234, 0);
1030 omap_writel(0x48008238, 7);
1031 omap_writel(0x4800823c, 0);
1032 omap_writel(0x48008240, 0x04360626);
1033 omap_writel(0x48008244, 0x00000014);
1034 omap_writel(0x48008248, 0);
1035 omap_writel(0x48008300, 0x00000000);
1036 omap_writel(0x48008310, 0x00000000);
1037 omap_writel(0x48008340, 0x00000001);
1038 omap_writel(0x48008400, 0x00000004);
1039 omap_writel(0x48008410, 0x00000004);
1040 omap_writel(0x48008440, 0x00000000);
1041 omap_writel(0x48008500, 0x000000cf);
1042 omap_writel(0x48008530, 0x0000000c);
1043 omap_writel(0x48008540,
1044 (0x78 << 12) | (6 << 8));
1045 omap_writel(0x48008544, 2);
1046
1047
1048 n800_gpmc_init(s);
1049
1050
1051 n800_dss_init(&s->blizzard);
1052
1053
1054 s->mpu->cpu->env.GE = 0x5;
1055
1056
1057 if (s->kbd) {
1058 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
1059 }
1060}
1061
1062#define OMAP_TAG_NOKIA_BT 0x4e01
1063#define OMAP_TAG_WLAN_CX3110X 0x4e02
1064#define OMAP_TAG_CBUS 0x4e03
1065#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1066
1067static struct omap_gpiosw_info_s {
1068 const char *name;
1069 int line;
1070 int type;
1071} n800_gpiosw_info[] = {
1072 {
1073 "bat_cover", N800_BAT_COVER_GPIO,
1074 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1075 }, {
1076 "cam_act", N800_CAM_ACT_GPIO,
1077 OMAP_GPIOSW_TYPE_ACTIVITY,
1078 }, {
1079 "cam_turn", N800_CAM_TURN_GPIO,
1080 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1081 }, {
1082 "headphone", N8X0_HEADPHONE_GPIO,
1083 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1084 },
1085 { NULL }
1086}, n810_gpiosw_info[] = {
1087 {
1088 "gps_reset", N810_GPS_RESET_GPIO,
1089 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1090 }, {
1091 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1092 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1093 }, {
1094 "headphone", N8X0_HEADPHONE_GPIO,
1095 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1096 }, {
1097 "kb_lock", N810_KB_LOCK_GPIO,
1098 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1099 }, {
1100 "sleepx_led", N810_SLEEPX_LED_GPIO,
1101 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1102 }, {
1103 "slide", N810_SLIDE_GPIO,
1104 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1105 },
1106 { NULL }
1107};
1108
1109static struct omap_partition_info_s {
1110 uint32_t offset;
1111 uint32_t size;
1112 int mask;
1113 const char *name;
1114} n800_part_info[] = {
1115 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1116 { 0x00020000, 0x00060000, 0x0, "config" },
1117 { 0x00080000, 0x00200000, 0x0, "kernel" },
1118 { 0x00280000, 0x00200000, 0x3, "initfs" },
1119 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1120
1121 { 0, 0, 0, NULL }
1122}, n810_part_info[] = {
1123 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1124 { 0x00020000, 0x00060000, 0x0, "config" },
1125 { 0x00080000, 0x00220000, 0x0, "kernel" },
1126 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1127 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1128
1129 { 0, 0, 0, NULL }
1130};
1131
1132static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1133
1134static int n8x0_atag_setup(void *p, int model)
1135{
1136 uint8_t *b;
1137 uint16_t *w;
1138 uint32_t *l;
1139 struct omap_gpiosw_info_s *gpiosw;
1140 struct omap_partition_info_s *partition;
1141 const char *tag;
1142
1143 w = p;
1144
1145 stw_p(w++, OMAP_TAG_UART);
1146 stw_p(w++, 4);
1147 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0));
1148 w++;
1149
1150#if 0
1151 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE);
1152 stw_p(w++, 4);
1153 stw_p(w++, XLDR_LL_UART + 1);
1154 stw_p(w++, 115200);
1155#endif
1156
1157 stw_p(w++, OMAP_TAG_LCD);
1158 stw_p(w++, 36);
1159 strcpy((void *) w, "QEMU LCD panel");
1160 w += 8;
1161 strcpy((void *) w, "blizzard");
1162 w += 8;
1163 stw_p(w++, N810_BLIZZARD_RESET_GPIO);
1164 stw_p(w++, 24);
1165
1166 stw_p(w++, OMAP_TAG_CBUS);
1167 stw_p(w++, 8);
1168 stw_p(w++, N8X0_CBUS_CLK_GPIO);
1169 stw_p(w++, N8X0_CBUS_DAT_GPIO);
1170 stw_p(w++, N8X0_CBUS_SEL_GPIO);
1171 w++;
1172
1173 stw_p(w++, OMAP_TAG_EM_ASIC_BB5);
1174 stw_p(w++, 4);
1175 stw_p(w++, N8X0_RETU_GPIO);
1176 stw_p(w++, N8X0_TAHVO_GPIO);
1177
1178 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1179 for (; gpiosw->name; gpiosw++) {
1180 stw_p(w++, OMAP_TAG_GPIO_SWITCH);
1181 stw_p(w++, 20);
1182 strcpy((void *) w, gpiosw->name);
1183 w += 6;
1184 stw_p(w++, gpiosw->line);
1185 stw_p(w++, gpiosw->type);
1186 stw_p(w++, 0);
1187 stw_p(w++, 0);
1188 }
1189
1190 stw_p(w++, OMAP_TAG_NOKIA_BT);
1191 stw_p(w++, 12);
1192 b = (void *) w;
1193 stb_p(b++, 0x01);
1194 stb_p(b++, N8X0_BT_WKUP_GPIO);
1195 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO);
1196 stb_p(b++, N8X0_BT_RESET_GPIO);
1197 stb_p(b++, BT_UART + 1);
1198 memcpy(b, &n8x0_bd_addr, 6);
1199 b += 6;
1200 stb_p(b++, 0x02);
1201 w = (void *) b;
1202
1203 stw_p(w++, OMAP_TAG_WLAN_CX3110X);
1204 stw_p(w++, 8);
1205 stw_p(w++, 0x25);
1206 stw_p(w++, N8X0_WLAN_PWR_GPIO);
1207 stw_p(w++, N8X0_WLAN_IRQ_GPIO);
1208 stw_p(w++, -1);
1209
1210 stw_p(w++, OMAP_TAG_MMC);
1211 stw_p(w++, 16);
1212 if (model == 810) {
1213 stw_p(w++, 0x23f);
1214 stw_p(w++, -1);
1215 stw_p(w++, -1);
1216 stw_p(w++, -1);
1217 stw_p(w++, 0x240);
1218 stw_p(w++, 0xc000);
1219 stw_p(w++, 0x0248);
1220 stw_p(w++, 0xc000);
1221 } else {
1222 stw_p(w++, 0xf);
1223 stw_p(w++, -1);
1224 stw_p(w++, -1);
1225 stw_p(w++, -1);
1226 stw_p(w++, 0);
1227 stw_p(w++, 0);
1228 stw_p(w++, 0);
1229 stw_p(w++, 0);
1230 }
1231
1232 stw_p(w++, OMAP_TAG_TEA5761);
1233 stw_p(w++, 4);
1234 stw_p(w++, N8X0_TEA5761_CS_GPIO);
1235 w++;
1236
1237 partition = (model == 810) ? n810_part_info : n800_part_info;
1238 for (; partition->name; partition++) {
1239 stw_p(w++, OMAP_TAG_PARTITION);
1240 stw_p(w++, 28);
1241 strcpy((void *) w, partition->name);
1242 l = (void *) (w + 8);
1243 stl_p(l++, partition->size);
1244 stl_p(l++, partition->offset);
1245 stl_p(l++, partition->mask);
1246 w = (void *) l;
1247 }
1248
1249 stw_p(w++, OMAP_TAG_BOOT_REASON);
1250 stw_p(w++, 12);
1251#if 0
1252 strcpy((void *) w, "por");
1253 strcpy((void *) w, "charger");
1254 strcpy((void *) w, "32wd_to");
1255 strcpy((void *) w, "sw_rst");
1256 strcpy((void *) w, "mbus");
1257 strcpy((void *) w, "unknown");
1258 strcpy((void *) w, "swdg_to");
1259 strcpy((void *) w, "sec_vio");
1260 strcpy((void *) w, "pwr_key");
1261 strcpy((void *) w, "rtc_alarm");
1262#else
1263 strcpy((void *) w, "pwr_key");
1264#endif
1265 w += 6;
1266
1267 tag = (model == 810) ? "RX-44" : "RX-34";
1268 stw_p(w++, OMAP_TAG_VERSION_STR);
1269 stw_p(w++, 24);
1270 strcpy((void *) w, "product");
1271 w += 6;
1272 strcpy((void *) w, tag);
1273 w += 6;
1274
1275 stw_p(w++, OMAP_TAG_VERSION_STR);
1276 stw_p(w++, 24);
1277 strcpy((void *) w, "hw-build");
1278 w += 6;
1279 strcpy((void *) w, "QEMU ");
1280 pstrcat((void *) w, 12, qemu_hw_version());
1281 w += 6;
1282
1283 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1284 stw_p(w++, OMAP_TAG_VERSION_STR);
1285 stw_p(w++, 24);
1286 strcpy((void *) w, "nolo");
1287 w += 6;
1288 strcpy((void *) w, tag);
1289 w += 6;
1290
1291 return (void *) w - p;
1292}
1293
1294static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1295{
1296 return n8x0_atag_setup(p, 800);
1297}
1298
1299static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1300{
1301 return n8x0_atag_setup(p, 810);
1302}
1303
1304static void n8x0_init(MachineState *machine,
1305 struct arm_boot_info *binfo, int model)
1306{
1307 MemoryRegion *sysmem = get_system_memory();
1308 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1309 int sdram_size = binfo->ram_size;
1310
1311 s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338 n8x0_gpio_setup(s);
1339 n8x0_nand_setup(s);
1340 n8x0_i2c_setup(s);
1341 if (model == 800) {
1342 n800_tsc_kbd_setup(s);
1343 } else if (model == 810) {
1344 n810_tsc_setup(s);
1345 n810_kbd_setup(s);
1346 }
1347 n8x0_spi_setup(s);
1348 n8x0_dss_setup(s);
1349 n8x0_cbus_setup(s);
1350 n8x0_uart_setup(s);
1351 if (usb_enabled()) {
1352 n8x0_usb_setup(s);
1353 }
1354
1355 if (machine->kernel_filename) {
1356
1357 binfo->kernel_filename = machine->kernel_filename;
1358 binfo->kernel_cmdline = machine->kernel_cmdline;
1359 binfo->initrd_filename = machine->initrd_filename;
1360 arm_load_kernel(s->mpu->cpu, binfo);
1361
1362 qemu_register_reset(n8x0_boot_init, s);
1363 }
1364
1365 if (option_rom[0].name &&
1366 (machine->boot_order[0] == 'n' || !machine->kernel_filename)) {
1367 uint8_t nolo_tags[0x10000];
1368
1369 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380 load_image_targphys(option_rom[0].name,
1381 OMAP2_Q2_BASE + 0x400000,
1382 sdram_size - 0x400000);
1383
1384 n800_setup_nolo_tags(nolo_tags);
1385 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1386 }
1387}
1388
1389static struct arm_boot_info n800_binfo = {
1390 .loader_start = OMAP2_Q2_BASE,
1391
1392 .ram_size = 0x08000000,
1393 .board_id = 0x4f7,
1394 .atag_board = n800_atag_setup,
1395};
1396
1397static struct arm_boot_info n810_binfo = {
1398 .loader_start = OMAP2_Q2_BASE,
1399
1400 .ram_size = 0x08000000,
1401
1402
1403
1404 .board_id = 0x60c,
1405 .atag_board = n810_atag_setup,
1406};
1407
1408static void n800_init(MachineState *machine)
1409{
1410 n8x0_init(machine, &n800_binfo, 800);
1411}
1412
1413static void n810_init(MachineState *machine)
1414{
1415 n8x0_init(machine, &n810_binfo, 810);
1416}
1417
1418static void n800_class_init(ObjectClass *oc, void *data)
1419{
1420 MachineClass *mc = MACHINE_CLASS(oc);
1421
1422 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)";
1423 mc->init = n800_init;
1424 mc->default_boot_order = "";
1425}
1426
1427static const TypeInfo n800_type = {
1428 .name = MACHINE_TYPE_NAME("n800"),
1429 .parent = TYPE_MACHINE,
1430 .class_init = n800_class_init,
1431};
1432
1433static void n810_class_init(ObjectClass *oc, void *data)
1434{
1435 MachineClass *mc = MACHINE_CLASS(oc);
1436
1437 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)";
1438 mc->init = n810_init;
1439 mc->default_boot_order = "";
1440}
1441
1442static const TypeInfo n810_type = {
1443 .name = MACHINE_TYPE_NAME("n810"),
1444 .parent = TYPE_MACHINE,
1445 .class_init = n810_class_init,
1446};
1447
1448static void nseries_machine_init(void)
1449{
1450 type_register_static(&n800_type);
1451 type_register_static(&n810_type);
1452}
1453
1454type_init(nseries_machine_init)
1455