LXR qemu/hw/arm/stm32f205

   1/*
   2 * STM32F205 SoC
   3 *
   4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "qapi/error.h"
  27#include "qemu-common.h"
  28#include "cpu.h"
  29#include "hw/arm/arm.h"
  30#include "exec/address-spaces.h"
  31#include "hw/arm/stm32f205_soc.h"
  32
  33/* At the moment only Timer 2 to 5 are modelled */
  34static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
  35    0x40000800, 0x40000C00 };
  36static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
  37    0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
  38
  39static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
  40static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
  41
  42static void stm32f205_soc_initfn(Object *obj)
  43{
  44    STM32F205State *s = STM32F205_SOC(obj);
  45    int i;
  46
  47    object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
  48    qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
  49
  50    for (i = 0; i < STM_NUM_USARTS; i++) {
  51        object_initialize(&s->usart[i], sizeof(s->usart[i]),
  52                          TYPE_STM32F2XX_USART);
  53        qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
  54    }
  55
  56    for (i = 0; i < STM_NUM_TIMERS; i++) {
  57        object_initialize(&s->timer[i], sizeof(s->timer[i]),
  58                          TYPE_STM32F2XX_TIMER);
  59        qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
  60    }
  61}
  62
  63static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
  64{
  65    STM32F205State *s = STM32F205_SOC(dev_soc);
  66    DeviceState *syscfgdev, *usartdev, *timerdev, *nvic;
  67    SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
  68    Error *err = NULL;
  69    int i;
  70
  71    MemoryRegion *system_memory = get_system_memory();
  72    MemoryRegion *sram = g_new(MemoryRegion, 1);
  73    MemoryRegion *flash = g_new(MemoryRegion, 1);
  74    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
  75
  76    memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
  77                           &error_fatal);
  78    memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
  79                             flash, 0, FLASH_SIZE);
  80
  81    vmstate_register_ram_global(flash);
  82
  83    memory_region_set_readonly(flash, true);
  84    memory_region_set_readonly(flash_alias, true);
  85
  86    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
  87    memory_region_add_subregion(system_memory, 0, flash_alias);
  88
  89    memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
  90                           &error_fatal);
  91    vmstate_register_ram_global(sram);
  92    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
  93
  94    nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
  95                       s->kernel_filename, s->cpu_model);
  96
  97    /* System configuration controller */
  98    syscfgdev = DEVICE(&s->syscfg);
  99    object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
 100    if (err != NULL) {
 101        error_propagate(errp, err);
 102        return;
 103    }
 104    syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
 105    sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
 106    sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71));
 107
 108    /* Attach UART (uses USART registers) and USART controllers */
 109    for (i = 0; i < STM_NUM_USARTS; i++) {
 110        usartdev = DEVICE(&(s->usart[i]));
 111        object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
 112        if (err != NULL) {
 113            error_propagate(errp, err);
 114            return;
 115        }
 116        usartbusdev = SYS_BUS_DEVICE(usartdev);
 117        sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
 118        sysbus_connect_irq(usartbusdev, 0,
 119                           qdev_get_gpio_in(nvic, usart_irq[i]));
 120    }
 121
 122    /* Timer 2 to 5 */
 123    for (i = 0; i < STM_NUM_TIMERS; i++) {
 124        timerdev = DEVICE(&(s->timer[i]));
 125        qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
 126        object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
 127        if (err != NULL) {
 128            error_propagate(errp, err);
 129            return;
 130        }
 131        timerbusdev = SYS_BUS_DEVICE(timerdev);
 132        sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
 133        sysbus_connect_irq(timerbusdev, 0,
 134                           qdev_get_gpio_in(nvic, timer_irq[i]));
 135    }
 136}
 137
 138static Property stm32f205_soc_properties[] = {
 139    DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
 140    DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
 141    DEFINE_PROP_END_OF_LIST(),
 142};
 143
 144static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
 145{
 146    DeviceClass *dc = DEVICE_CLASS(klass);
 147
 148    dc->realize = stm32f205_soc_realize;
 149    dc->props = stm32f205_soc_properties;
 150}
 151
 152static const TypeInfo stm32f205_soc_info = {
 153    .name          = TYPE_STM32F205_SOC,
 154    .parent        = TYPE_SYS_BUS_DEVICE,
 155    .instance_size = sizeof(STM32F205State),
 156    .instance_init = stm32f205_soc_initfn,
 157    .class_init    = stm32f205_soc_class_init,
 158};
 159
 160static void stm32f205_soc_types(void)
 161{
 162    type_register_static(&stm32f205_soc_info);
 163}
 164
 165type_init(stm32f205_soc_types)
 166