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30#include "qemu/osdep.h"
31#include "cpu.h"
32#include "hw/boards.h"
33#include "hw/sysbus.h"
34#include "strongarm.h"
35#include "qemu/error-report.h"
36#include "hw/arm/arm.h"
37#include "sysemu/char.h"
38#include "sysemu/sysemu.h"
39#include "hw/ssi/ssi.h"
40#include "qemu/cutils.h"
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60
61#ifdef DEBUG
62# define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
63#else
64# define DPRINTF(format, ...) do { } while (0)
65#endif
66
67static struct {
68 hwaddr io_base;
69 int irq;
70} sa_serial[] = {
71 { 0x80010000, SA_PIC_UART1 },
72 { 0x80030000, SA_PIC_UART2 },
73 { 0x80050000, SA_PIC_UART3 },
74 { 0, 0 }
75};
76
77
78
79#define TYPE_STRONGARM_PIC "strongarm_pic"
80#define STRONGARM_PIC(obj) \
81 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
82
83typedef struct StrongARMPICState {
84 SysBusDevice parent_obj;
85
86 MemoryRegion iomem;
87 qemu_irq irq;
88 qemu_irq fiq;
89
90 uint32_t pending;
91 uint32_t enabled;
92 uint32_t is_fiq;
93 uint32_t int_idle;
94} StrongARMPICState;
95
96#define ICIP 0x00
97#define ICMR 0x04
98#define ICLR 0x08
99#define ICFP 0x10
100#define ICPR 0x20
101#define ICCR 0x0c
102
103#define SA_PIC_SRCS 32
104
105
106static void strongarm_pic_update(void *opaque)
107{
108 StrongARMPICState *s = opaque;
109
110
111 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
112 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
113}
114
115static void strongarm_pic_set_irq(void *opaque, int irq, int level)
116{
117 StrongARMPICState *s = opaque;
118
119 if (level) {
120 s->pending |= 1 << irq;
121 } else {
122 s->pending &= ~(1 << irq);
123 }
124
125 strongarm_pic_update(s);
126}
127
128static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
129 unsigned size)
130{
131 StrongARMPICState *s = opaque;
132
133 switch (offset) {
134 case ICIP:
135 return s->pending & ~s->is_fiq & s->enabled;
136 case ICMR:
137 return s->enabled;
138 case ICLR:
139 return s->is_fiq;
140 case ICCR:
141 return s->int_idle == 0;
142 case ICFP:
143 return s->pending & s->is_fiq & s->enabled;
144 case ICPR:
145 return s->pending;
146 default:
147 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
148 __func__, offset);
149 return 0;
150 }
151}
152
153static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
154 uint64_t value, unsigned size)
155{
156 StrongARMPICState *s = opaque;
157
158 switch (offset) {
159 case ICMR:
160 s->enabled = value;
161 break;
162 case ICLR:
163 s->is_fiq = value;
164 break;
165 case ICCR:
166 s->int_idle = (value & 1) ? 0 : ~0;
167 break;
168 default:
169 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
170 __func__, offset);
171 break;
172 }
173 strongarm_pic_update(s);
174}
175
176static const MemoryRegionOps strongarm_pic_ops = {
177 .read = strongarm_pic_mem_read,
178 .write = strongarm_pic_mem_write,
179 .endianness = DEVICE_NATIVE_ENDIAN,
180};
181
182static int strongarm_pic_initfn(SysBusDevice *sbd)
183{
184 DeviceState *dev = DEVICE(sbd);
185 StrongARMPICState *s = STRONGARM_PIC(dev);
186
187 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
188 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s,
189 "pic", 0x1000);
190 sysbus_init_mmio(sbd, &s->iomem);
191 sysbus_init_irq(sbd, &s->irq);
192 sysbus_init_irq(sbd, &s->fiq);
193
194 return 0;
195}
196
197static int strongarm_pic_post_load(void *opaque, int version_id)
198{
199 strongarm_pic_update(opaque);
200 return 0;
201}
202
203static VMStateDescription vmstate_strongarm_pic_regs = {
204 .name = "strongarm_pic",
205 .version_id = 0,
206 .minimum_version_id = 0,
207 .post_load = strongarm_pic_post_load,
208 .fields = (VMStateField[]) {
209 VMSTATE_UINT32(pending, StrongARMPICState),
210 VMSTATE_UINT32(enabled, StrongARMPICState),
211 VMSTATE_UINT32(is_fiq, StrongARMPICState),
212 VMSTATE_UINT32(int_idle, StrongARMPICState),
213 VMSTATE_END_OF_LIST(),
214 },
215};
216
217static void strongarm_pic_class_init(ObjectClass *klass, void *data)
218{
219 DeviceClass *dc = DEVICE_CLASS(klass);
220 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
221
222 k->init = strongarm_pic_initfn;
223 dc->desc = "StrongARM PIC";
224 dc->vmsd = &vmstate_strongarm_pic_regs;
225}
226
227static const TypeInfo strongarm_pic_info = {
228 .name = TYPE_STRONGARM_PIC,
229 .parent = TYPE_SYS_BUS_DEVICE,
230 .instance_size = sizeof(StrongARMPICState),
231 .class_init = strongarm_pic_class_init,
232};
233
234
235#define RTAR 0x00
236#define RCNR 0x04
237#define RTTR 0x08
238#define RTSR 0x10
239
240#define RTSR_AL (1 << 0)
241#define RTSR_HZ (1 << 1)
242#define RTSR_ALE (1 << 2)
243#define RTSR_HZE (1 << 3)
244
245
246
247
248
249#define TYPE_STRONGARM_RTC "strongarm-rtc"
250#define STRONGARM_RTC(obj) \
251 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
252
253typedef struct StrongARMRTCState {
254 SysBusDevice parent_obj;
255
256 MemoryRegion iomem;
257 uint32_t rttr;
258 uint32_t rtsr;
259 uint32_t rtar;
260 uint32_t last_rcnr;
261 int64_t last_hz;
262 QEMUTimer *rtc_alarm;
263 QEMUTimer *rtc_hz;
264 qemu_irq rtc_irq;
265 qemu_irq rtc_hz_irq;
266} StrongARMRTCState;
267
268static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
269{
270 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
271 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
272}
273
274static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
275{
276 int64_t rt = qemu_clock_get_ms(rtc_clock);
277 s->last_rcnr += ((rt - s->last_hz) << 15) /
278 (1000 * ((s->rttr & 0xffff) + 1));
279 s->last_hz = rt;
280}
281
282static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
283{
284 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
285 timer_mod(s->rtc_hz, s->last_hz + 1000);
286 } else {
287 timer_del(s->rtc_hz);
288 }
289
290 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
291 timer_mod(s->rtc_alarm, s->last_hz +
292 (((s->rtar - s->last_rcnr) * 1000 *
293 ((s->rttr & 0xffff) + 1)) >> 15));
294 } else {
295 timer_del(s->rtc_alarm);
296 }
297}
298
299static inline void strongarm_rtc_alarm_tick(void *opaque)
300{
301 StrongARMRTCState *s = opaque;
302 s->rtsr |= RTSR_AL;
303 strongarm_rtc_timer_update(s);
304 strongarm_rtc_int_update(s);
305}
306
307static inline void strongarm_rtc_hz_tick(void *opaque)
308{
309 StrongARMRTCState *s = opaque;
310 s->rtsr |= RTSR_HZ;
311 strongarm_rtc_timer_update(s);
312 strongarm_rtc_int_update(s);
313}
314
315static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
316 unsigned size)
317{
318 StrongARMRTCState *s = opaque;
319
320 switch (addr) {
321 case RTTR:
322 return s->rttr;
323 case RTSR:
324 return s->rtsr;
325 case RTAR:
326 return s->rtar;
327 case RCNR:
328 return s->last_rcnr +
329 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
330 (1000 * ((s->rttr & 0xffff) + 1));
331 default:
332 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
333 return 0;
334 }
335}
336
337static void strongarm_rtc_write(void *opaque, hwaddr addr,
338 uint64_t value, unsigned size)
339{
340 StrongARMRTCState *s = opaque;
341 uint32_t old_rtsr;
342
343 switch (addr) {
344 case RTTR:
345 strongarm_rtc_hzupdate(s);
346 s->rttr = value;
347 strongarm_rtc_timer_update(s);
348 break;
349
350 case RTSR:
351 old_rtsr = s->rtsr;
352 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
353 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
354
355 if (s->rtsr != old_rtsr) {
356 strongarm_rtc_timer_update(s);
357 }
358
359 strongarm_rtc_int_update(s);
360 break;
361
362 case RTAR:
363 s->rtar = value;
364 strongarm_rtc_timer_update(s);
365 break;
366
367 case RCNR:
368 strongarm_rtc_hzupdate(s);
369 s->last_rcnr = value;
370 strongarm_rtc_timer_update(s);
371 break;
372
373 default:
374 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
375 }
376}
377
378static const MemoryRegionOps strongarm_rtc_ops = {
379 .read = strongarm_rtc_read,
380 .write = strongarm_rtc_write,
381 .endianness = DEVICE_NATIVE_ENDIAN,
382};
383
384static int strongarm_rtc_init(SysBusDevice *dev)
385{
386 StrongARMRTCState *s = STRONGARM_RTC(dev);
387 struct tm tm;
388
389 s->rttr = 0x0;
390 s->rtsr = 0;
391
392 qemu_get_timedate(&tm, 0);
393
394 s->last_rcnr = (uint32_t) mktimegm(&tm);
395 s->last_hz = qemu_clock_get_ms(rtc_clock);
396
397 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
398 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
399
400 sysbus_init_irq(dev, &s->rtc_irq);
401 sysbus_init_irq(dev, &s->rtc_hz_irq);
402
403 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s,
404 "rtc", 0x10000);
405 sysbus_init_mmio(dev, &s->iomem);
406
407 return 0;
408}
409
410static void strongarm_rtc_pre_save(void *opaque)
411{
412 StrongARMRTCState *s = opaque;
413
414 strongarm_rtc_hzupdate(s);
415}
416
417static int strongarm_rtc_post_load(void *opaque, int version_id)
418{
419 StrongARMRTCState *s = opaque;
420
421 strongarm_rtc_timer_update(s);
422 strongarm_rtc_int_update(s);
423
424 return 0;
425}
426
427static const VMStateDescription vmstate_strongarm_rtc_regs = {
428 .name = "strongarm-rtc",
429 .version_id = 0,
430 .minimum_version_id = 0,
431 .pre_save = strongarm_rtc_pre_save,
432 .post_load = strongarm_rtc_post_load,
433 .fields = (VMStateField[]) {
434 VMSTATE_UINT32(rttr, StrongARMRTCState),
435 VMSTATE_UINT32(rtsr, StrongARMRTCState),
436 VMSTATE_UINT32(rtar, StrongARMRTCState),
437 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
438 VMSTATE_INT64(last_hz, StrongARMRTCState),
439 VMSTATE_END_OF_LIST(),
440 },
441};
442
443static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
444{
445 DeviceClass *dc = DEVICE_CLASS(klass);
446 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
447
448 k->init = strongarm_rtc_init;
449 dc->desc = "StrongARM RTC Controller";
450 dc->vmsd = &vmstate_strongarm_rtc_regs;
451}
452
453static const TypeInfo strongarm_rtc_sysbus_info = {
454 .name = TYPE_STRONGARM_RTC,
455 .parent = TYPE_SYS_BUS_DEVICE,
456 .instance_size = sizeof(StrongARMRTCState),
457 .class_init = strongarm_rtc_sysbus_class_init,
458};
459
460
461#define GPLR 0x00
462#define GPDR 0x04
463#define GPSR 0x08
464#define GPCR 0x0c
465#define GRER 0x10
466#define GFER 0x14
467#define GEDR 0x18
468#define GAFR 0x1c
469
470#define TYPE_STRONGARM_GPIO "strongarm-gpio"
471#define STRONGARM_GPIO(obj) \
472 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
473
474typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
475struct StrongARMGPIOInfo {
476 SysBusDevice busdev;
477 MemoryRegion iomem;
478 qemu_irq handler[28];
479 qemu_irq irqs[11];
480 qemu_irq irqX;
481
482 uint32_t ilevel;
483 uint32_t olevel;
484 uint32_t dir;
485 uint32_t rising;
486 uint32_t falling;
487 uint32_t status;
488 uint32_t gafr;
489
490 uint32_t prev_level;
491};
492
493
494static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
495{
496 int i;
497 for (i = 0; i < 11; i++) {
498 qemu_set_irq(s->irqs[i], s->status & (1 << i));
499 }
500
501 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
502}
503
504static void strongarm_gpio_set(void *opaque, int line, int level)
505{
506 StrongARMGPIOInfo *s = opaque;
507 uint32_t mask;
508
509 mask = 1 << line;
510
511 if (level) {
512 s->status |= s->rising & mask &
513 ~s->ilevel & ~s->dir;
514 s->ilevel |= mask;
515 } else {
516 s->status |= s->falling & mask &
517 s->ilevel & ~s->dir;
518 s->ilevel &= ~mask;
519 }
520
521 if (s->status & mask) {
522 strongarm_gpio_irq_update(s);
523 }
524}
525
526static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
527{
528 uint32_t level, diff;
529 int bit;
530
531 level = s->olevel & s->dir;
532
533 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
534 bit = ctz32(diff);
535 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
536 }
537
538 s->prev_level = level;
539}
540
541static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
542 unsigned size)
543{
544 StrongARMGPIOInfo *s = opaque;
545
546 switch (offset) {
547 case GPDR:
548 return s->dir;
549
550 case GPSR:
551 qemu_log_mask(LOG_GUEST_ERROR,
552 "strongarm GPIO: read from write only register GPSR\n");
553 return 0;
554
555 case GPCR:
556 qemu_log_mask(LOG_GUEST_ERROR,
557 "strongarm GPIO: read from write only register GPCR\n");
558 return 0;
559
560 case GRER:
561 return s->rising;
562
563 case GFER:
564 return s->falling;
565
566 case GAFR:
567 return s->gafr;
568
569 case GPLR:
570 return (s->olevel & s->dir) |
571 (s->ilevel & ~s->dir);
572
573 case GEDR:
574 return s->status;
575
576 default:
577 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
578 }
579
580 return 0;
581}
582
583static void strongarm_gpio_write(void *opaque, hwaddr offset,
584 uint64_t value, unsigned size)
585{
586 StrongARMGPIOInfo *s = opaque;
587
588 switch (offset) {
589 case GPDR:
590 s->dir = value;
591 strongarm_gpio_handler_update(s);
592 break;
593
594 case GPSR:
595 s->olevel |= value;
596 strongarm_gpio_handler_update(s);
597 break;
598
599 case GPCR:
600 s->olevel &= ~value;
601 strongarm_gpio_handler_update(s);
602 break;
603
604 case GRER:
605 s->rising = value;
606 break;
607
608 case GFER:
609 s->falling = value;
610 break;
611
612 case GAFR:
613 s->gafr = value;
614 break;
615
616 case GEDR:
617 s->status &= ~value;
618 strongarm_gpio_irq_update(s);
619 break;
620
621 default:
622 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
623 }
624}
625
626static const MemoryRegionOps strongarm_gpio_ops = {
627 .read = strongarm_gpio_read,
628 .write = strongarm_gpio_write,
629 .endianness = DEVICE_NATIVE_ENDIAN,
630};
631
632static DeviceState *strongarm_gpio_init(hwaddr base,
633 DeviceState *pic)
634{
635 DeviceState *dev;
636 int i;
637
638 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
639 qdev_init_nofail(dev);
640
641 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
642 for (i = 0; i < 12; i++)
643 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
644 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
645
646 return dev;
647}
648
649static int strongarm_gpio_initfn(SysBusDevice *sbd)
650{
651 DeviceState *dev = DEVICE(sbd);
652 StrongARMGPIOInfo *s = STRONGARM_GPIO(dev);
653 int i;
654
655 qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
656 qdev_init_gpio_out(dev, s->handler, 28);
657
658 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s,
659 "gpio", 0x1000);
660
661 sysbus_init_mmio(sbd, &s->iomem);
662 for (i = 0; i < 11; i++) {
663 sysbus_init_irq(sbd, &s->irqs[i]);
664 }
665 sysbus_init_irq(sbd, &s->irqX);
666
667 return 0;
668}
669
670static const VMStateDescription vmstate_strongarm_gpio_regs = {
671 .name = "strongarm-gpio",
672 .version_id = 0,
673 .minimum_version_id = 0,
674 .fields = (VMStateField[]) {
675 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
676 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
677 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
678 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
679 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
680 VMSTATE_UINT32(status, StrongARMGPIOInfo),
681 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
682 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo),
683 VMSTATE_END_OF_LIST(),
684 },
685};
686
687static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
688{
689 DeviceClass *dc = DEVICE_CLASS(klass);
690 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
691
692 k->init = strongarm_gpio_initfn;
693 dc->desc = "StrongARM GPIO controller";
694 dc->vmsd = &vmstate_strongarm_gpio_regs;
695}
696
697static const TypeInfo strongarm_gpio_info = {
698 .name = TYPE_STRONGARM_GPIO,
699 .parent = TYPE_SYS_BUS_DEVICE,
700 .instance_size = sizeof(StrongARMGPIOInfo),
701 .class_init = strongarm_gpio_class_init,
702};
703
704
705#define PPDR 0x00
706#define PPSR 0x04
707#define PPAR 0x08
708#define PSDR 0x0c
709#define PPFR 0x10
710
711#define TYPE_STRONGARM_PPC "strongarm-ppc"
712#define STRONGARM_PPC(obj) \
713 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
714
715typedef struct StrongARMPPCInfo StrongARMPPCInfo;
716struct StrongARMPPCInfo {
717 SysBusDevice parent_obj;
718
719 MemoryRegion iomem;
720 qemu_irq handler[28];
721
722 uint32_t ilevel;
723 uint32_t olevel;
724 uint32_t dir;
725 uint32_t ppar;
726 uint32_t psdr;
727 uint32_t ppfr;
728
729 uint32_t prev_level;
730};
731
732static void strongarm_ppc_set(void *opaque, int line, int level)
733{
734 StrongARMPPCInfo *s = opaque;
735
736 if (level) {
737 s->ilevel |= 1 << line;
738 } else {
739 s->ilevel &= ~(1 << line);
740 }
741}
742
743static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
744{
745 uint32_t level, diff;
746 int bit;
747
748 level = s->olevel & s->dir;
749
750 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
751 bit = ctz32(diff);
752 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
753 }
754
755 s->prev_level = level;
756}
757
758static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
759 unsigned size)
760{
761 StrongARMPPCInfo *s = opaque;
762
763 switch (offset) {
764 case PPDR:
765 return s->dir | ~0x3fffff;
766
767 case PPSR:
768 return (s->olevel & s->dir) |
769 (s->ilevel & ~s->dir) |
770 ~0x3fffff;
771
772 case PPAR:
773 return s->ppar | ~0x41000;
774
775 case PSDR:
776 return s->psdr;
777
778 case PPFR:
779 return s->ppfr | ~0x7f001;
780
781 default:
782 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
783 }
784
785 return 0;
786}
787
788static void strongarm_ppc_write(void *opaque, hwaddr offset,
789 uint64_t value, unsigned size)
790{
791 StrongARMPPCInfo *s = opaque;
792
793 switch (offset) {
794 case PPDR:
795 s->dir = value & 0x3fffff;
796 strongarm_ppc_handler_update(s);
797 break;
798
799 case PPSR:
800 s->olevel = value & s->dir & 0x3fffff;
801 strongarm_ppc_handler_update(s);
802 break;
803
804 case PPAR:
805 s->ppar = value & 0x41000;
806 break;
807
808 case PSDR:
809 s->psdr = value & 0x3fffff;
810 break;
811
812 case PPFR:
813 s->ppfr = value & 0x7f001;
814 break;
815
816 default:
817 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
818 }
819}
820
821static const MemoryRegionOps strongarm_ppc_ops = {
822 .read = strongarm_ppc_read,
823 .write = strongarm_ppc_write,
824 .endianness = DEVICE_NATIVE_ENDIAN,
825};
826
827static int strongarm_ppc_init(SysBusDevice *sbd)
828{
829 DeviceState *dev = DEVICE(sbd);
830 StrongARMPPCInfo *s = STRONGARM_PPC(dev);
831
832 qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
833 qdev_init_gpio_out(dev, s->handler, 22);
834
835 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s,
836 "ppc", 0x1000);
837
838 sysbus_init_mmio(sbd, &s->iomem);
839
840 return 0;
841}
842
843static const VMStateDescription vmstate_strongarm_ppc_regs = {
844 .name = "strongarm-ppc",
845 .version_id = 0,
846 .minimum_version_id = 0,
847 .fields = (VMStateField[]) {
848 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
849 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
850 VMSTATE_UINT32(dir, StrongARMPPCInfo),
851 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
852 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
853 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
854 VMSTATE_UINT32(prev_level, StrongARMPPCInfo),
855 VMSTATE_END_OF_LIST(),
856 },
857};
858
859static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
860{
861 DeviceClass *dc = DEVICE_CLASS(klass);
862 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
863
864 k->init = strongarm_ppc_init;
865 dc->desc = "StrongARM PPC controller";
866 dc->vmsd = &vmstate_strongarm_ppc_regs;
867}
868
869static const TypeInfo strongarm_ppc_info = {
870 .name = TYPE_STRONGARM_PPC,
871 .parent = TYPE_SYS_BUS_DEVICE,
872 .instance_size = sizeof(StrongARMPPCInfo),
873 .class_init = strongarm_ppc_class_init,
874};
875
876
877#define UTCR0 0x00
878#define UTCR1 0x04
879#define UTCR2 0x08
880#define UTCR3 0x0c
881#define UTDR 0x14
882#define UTSR0 0x1c
883#define UTSR1 0x20
884
885#define UTCR0_PE (1 << 0)
886#define UTCR0_OES (1 << 1)
887#define UTCR0_SBS (1 << 2)
888#define UTCR0_DSS (1 << 3)
889
890#define UTCR3_RXE (1 << 0)
891#define UTCR3_TXE (1 << 1)
892#define UTCR3_BRK (1 << 2)
893#define UTCR3_RIE (1 << 3)
894#define UTCR3_TIE (1 << 4)
895#define UTCR3_LBM (1 << 5)
896
897#define UTSR0_TFS (1 << 0)
898#define UTSR0_RFS (1 << 1)
899#define UTSR0_RID (1 << 2)
900#define UTSR0_RBB (1 << 3)
901#define UTSR0_REB (1 << 4)
902#define UTSR0_EIF (1 << 5)
903
904#define UTSR1_RNE (1 << 1)
905#define UTSR1_TNF (1 << 2)
906#define UTSR1_PRE (1 << 3)
907#define UTSR1_FRE (1 << 4)
908#define UTSR1_ROR (1 << 5)
909
910#define RX_FIFO_PRE (1 << 8)
911#define RX_FIFO_FRE (1 << 9)
912#define RX_FIFO_ROR (1 << 10)
913
914#define TYPE_STRONGARM_UART "strongarm-uart"
915#define STRONGARM_UART(obj) \
916 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
917
918typedef struct StrongARMUARTState {
919 SysBusDevice parent_obj;
920
921 MemoryRegion iomem;
922 CharDriverState *chr;
923 qemu_irq irq;
924
925 uint8_t utcr0;
926 uint16_t brd;
927 uint8_t utcr3;
928 uint8_t utsr0;
929 uint8_t utsr1;
930
931 uint8_t tx_fifo[8];
932 uint8_t tx_start;
933 uint8_t tx_len;
934 uint16_t rx_fifo[12];
935 uint8_t rx_start;
936 uint8_t rx_len;
937
938 uint64_t char_transmit_time;
939 bool wait_break_end;
940 QEMUTimer *rx_timeout_timer;
941 QEMUTimer *tx_timer;
942} StrongARMUARTState;
943
944static void strongarm_uart_update_status(StrongARMUARTState *s)
945{
946 uint16_t utsr1 = 0;
947
948 if (s->tx_len != 8) {
949 utsr1 |= UTSR1_TNF;
950 }
951
952 if (s->rx_len != 0) {
953 uint16_t ent = s->rx_fifo[s->rx_start];
954
955 utsr1 |= UTSR1_RNE;
956 if (ent & RX_FIFO_PRE) {
957 s->utsr1 |= UTSR1_PRE;
958 }
959 if (ent & RX_FIFO_FRE) {
960 s->utsr1 |= UTSR1_FRE;
961 }
962 if (ent & RX_FIFO_ROR) {
963 s->utsr1 |= UTSR1_ROR;
964 }
965 }
966
967 s->utsr1 = utsr1;
968}
969
970static void strongarm_uart_update_int_status(StrongARMUARTState *s)
971{
972 uint16_t utsr0 = s->utsr0 &
973 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
974 int i;
975
976 if ((s->utcr3 & UTCR3_TXE) &&
977 (s->utcr3 & UTCR3_TIE) &&
978 s->tx_len <= 4) {
979 utsr0 |= UTSR0_TFS;
980 }
981
982 if ((s->utcr3 & UTCR3_RXE) &&
983 (s->utcr3 & UTCR3_RIE) &&
984 s->rx_len > 4) {
985 utsr0 |= UTSR0_RFS;
986 }
987
988 for (i = 0; i < s->rx_len && i < 4; i++)
989 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
990 utsr0 |= UTSR0_EIF;
991 break;
992 }
993
994 s->utsr0 = utsr0;
995 qemu_set_irq(s->irq, utsr0);
996}
997
998static void strongarm_uart_update_parameters(StrongARMUARTState *s)
999{
1000 int speed, parity, data_bits, stop_bits, frame_size;
1001 QEMUSerialSetParams ssp;
1002
1003
1004 frame_size = 1;
1005 if (s->utcr0 & UTCR0_PE) {
1006
1007 frame_size++;
1008 if (s->utcr0 & UTCR0_OES) {
1009 parity = 'E';
1010 } else {
1011 parity = 'O';
1012 }
1013 } else {
1014 parity = 'N';
1015 }
1016 if (s->utcr0 & UTCR0_SBS) {
1017 stop_bits = 2;
1018 } else {
1019 stop_bits = 1;
1020 }
1021
1022 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
1023 frame_size += data_bits + stop_bits;
1024 speed = 3686400 / 16 / (s->brd + 1);
1025 ssp.speed = speed;
1026 ssp.parity = parity;
1027 ssp.data_bits = data_bits;
1028 ssp.stop_bits = stop_bits;
1029 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size;
1030 if (s->chr) {
1031 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1032 }
1033
1034 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1035 speed, parity, data_bits, stop_bits);
1036}
1037
1038static void strongarm_uart_rx_to(void *opaque)
1039{
1040 StrongARMUARTState *s = opaque;
1041
1042 if (s->rx_len) {
1043 s->utsr0 |= UTSR0_RID;
1044 strongarm_uart_update_int_status(s);
1045 }
1046}
1047
1048static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1049{
1050 if ((s->utcr3 & UTCR3_RXE) == 0) {
1051
1052 return;
1053 }
1054
1055 if (s->wait_break_end) {
1056 s->utsr0 |= UTSR0_REB;
1057 s->wait_break_end = false;
1058 }
1059
1060 if (s->rx_len < 12) {
1061 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1062 s->rx_len++;
1063 } else
1064 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1065}
1066
1067static int strongarm_uart_can_receive(void *opaque)
1068{
1069 StrongARMUARTState *s = opaque;
1070
1071 if (s->rx_len == 12) {
1072 return 0;
1073 }
1074
1075 if (s->rx_len < 8) {
1076 return 8 - s->rx_len;
1077 }
1078 return 1;
1079}
1080
1081static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1082{
1083 StrongARMUARTState *s = opaque;
1084 int i;
1085
1086 for (i = 0; i < size; i++) {
1087 strongarm_uart_rx_push(s, buf[i]);
1088 }
1089
1090
1091 timer_mod(s->rx_timeout_timer,
1092 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1093
1094 strongarm_uart_update_status(s);
1095 strongarm_uart_update_int_status(s);
1096}
1097
1098static void strongarm_uart_event(void *opaque, int event)
1099{
1100 StrongARMUARTState *s = opaque;
1101 if (event == CHR_EVENT_BREAK) {
1102 s->utsr0 |= UTSR0_RBB;
1103 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1104 s->wait_break_end = true;
1105 strongarm_uart_update_status(s);
1106 strongarm_uart_update_int_status(s);
1107 }
1108}
1109
1110static void strongarm_uart_tx(void *opaque)
1111{
1112 StrongARMUARTState *s = opaque;
1113 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1114
1115 if (s->utcr3 & UTCR3_LBM) {
1116 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1117 } else if (s->chr) {
1118 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1119 }
1120
1121 s->tx_start = (s->tx_start + 1) % 8;
1122 s->tx_len--;
1123 if (s->tx_len) {
1124 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1125 }
1126 strongarm_uart_update_status(s);
1127 strongarm_uart_update_int_status(s);
1128}
1129
1130static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1131 unsigned size)
1132{
1133 StrongARMUARTState *s = opaque;
1134 uint16_t ret;
1135
1136 switch (addr) {
1137 case UTCR0:
1138 return s->utcr0;
1139
1140 case UTCR1:
1141 return s->brd >> 8;
1142
1143 case UTCR2:
1144 return s->brd & 0xff;
1145
1146 case UTCR3:
1147 return s->utcr3;
1148
1149 case UTDR:
1150 if (s->rx_len != 0) {
1151 ret = s->rx_fifo[s->rx_start];
1152 s->rx_start = (s->rx_start + 1) % 12;
1153 s->rx_len--;
1154 strongarm_uart_update_status(s);
1155 strongarm_uart_update_int_status(s);
1156 return ret;
1157 }
1158 return 0;
1159
1160 case UTSR0:
1161 return s->utsr0;
1162
1163 case UTSR1:
1164 return s->utsr1;
1165
1166 default:
1167 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1168 return 0;
1169 }
1170}
1171
1172static void strongarm_uart_write(void *opaque, hwaddr addr,
1173 uint64_t value, unsigned size)
1174{
1175 StrongARMUARTState *s = opaque;
1176
1177 switch (addr) {
1178 case UTCR0:
1179 s->utcr0 = value & 0x7f;
1180 strongarm_uart_update_parameters(s);
1181 break;
1182
1183 case UTCR1:
1184 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1185 strongarm_uart_update_parameters(s);
1186 break;
1187
1188 case UTCR2:
1189 s->brd = (s->brd & 0xf00) | (value & 0xff);
1190 strongarm_uart_update_parameters(s);
1191 break;
1192
1193 case UTCR3:
1194 s->utcr3 = value & 0x3f;
1195 if ((s->utcr3 & UTCR3_RXE) == 0) {
1196 s->rx_len = 0;
1197 }
1198 if ((s->utcr3 & UTCR3_TXE) == 0) {
1199 s->tx_len = 0;
1200 }
1201 strongarm_uart_update_status(s);
1202 strongarm_uart_update_int_status(s);
1203 break;
1204
1205 case UTDR:
1206 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1207 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1208 s->tx_len++;
1209 strongarm_uart_update_status(s);
1210 strongarm_uart_update_int_status(s);
1211 if (s->tx_len == 1) {
1212 strongarm_uart_tx(s);
1213 }
1214 }
1215 break;
1216
1217 case UTSR0:
1218 s->utsr0 = s->utsr0 & ~(value &
1219 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1220 strongarm_uart_update_int_status(s);
1221 break;
1222
1223 default:
1224 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1225 }
1226}
1227
1228static const MemoryRegionOps strongarm_uart_ops = {
1229 .read = strongarm_uart_read,
1230 .write = strongarm_uart_write,
1231 .endianness = DEVICE_NATIVE_ENDIAN,
1232};
1233
1234static int strongarm_uart_init(SysBusDevice *dev)
1235{
1236 StrongARMUARTState *s = STRONGARM_UART(dev);
1237
1238 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s,
1239 "uart", 0x10000);
1240 sysbus_init_mmio(dev, &s->iomem);
1241 sysbus_init_irq(dev, &s->irq);
1242
1243 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
1244 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
1245
1246 if (s->chr) {
1247 qemu_chr_add_handlers(s->chr,
1248 strongarm_uart_can_receive,
1249 strongarm_uart_receive,
1250 strongarm_uart_event,
1251 s);
1252 }
1253
1254 return 0;
1255}
1256
1257static void strongarm_uart_reset(DeviceState *dev)
1258{
1259 StrongARMUARTState *s = STRONGARM_UART(dev);
1260
1261 s->utcr0 = UTCR0_DSS;
1262 s->brd = 23;
1263
1264 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1265
1266 s->rx_len = s->tx_len = 0;
1267
1268 strongarm_uart_update_parameters(s);
1269 strongarm_uart_update_status(s);
1270 strongarm_uart_update_int_status(s);
1271}
1272
1273static int strongarm_uart_post_load(void *opaque, int version_id)
1274{
1275 StrongARMUARTState *s = opaque;
1276
1277 strongarm_uart_update_parameters(s);
1278 strongarm_uart_update_status(s);
1279 strongarm_uart_update_int_status(s);
1280
1281
1282 if (s->tx_len) {
1283 strongarm_uart_tx(s);
1284 }
1285
1286
1287 if (s->rx_len) {
1288 timer_mod(s->rx_timeout_timer,
1289 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1290 }
1291
1292 return 0;
1293}
1294
1295static const VMStateDescription vmstate_strongarm_uart_regs = {
1296 .name = "strongarm-uart",
1297 .version_id = 0,
1298 .minimum_version_id = 0,
1299 .post_load = strongarm_uart_post_load,
1300 .fields = (VMStateField[]) {
1301 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1302 VMSTATE_UINT16(brd, StrongARMUARTState),
1303 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1304 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1305 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1306 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1307 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1308 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1309 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1310 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1311 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1312 VMSTATE_END_OF_LIST(),
1313 },
1314};
1315
1316static Property strongarm_uart_properties[] = {
1317 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1318 DEFINE_PROP_END_OF_LIST(),
1319};
1320
1321static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1322{
1323 DeviceClass *dc = DEVICE_CLASS(klass);
1324 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1325
1326 k->init = strongarm_uart_init;
1327 dc->desc = "StrongARM UART controller";
1328 dc->reset = strongarm_uart_reset;
1329 dc->vmsd = &vmstate_strongarm_uart_regs;
1330 dc->props = strongarm_uart_properties;
1331}
1332
1333static const TypeInfo strongarm_uart_info = {
1334 .name = TYPE_STRONGARM_UART,
1335 .parent = TYPE_SYS_BUS_DEVICE,
1336 .instance_size = sizeof(StrongARMUARTState),
1337 .class_init = strongarm_uart_class_init,
1338};
1339
1340
1341
1342#define TYPE_STRONGARM_SSP "strongarm-ssp"
1343#define STRONGARM_SSP(obj) \
1344 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1345
1346typedef struct StrongARMSSPState {
1347 SysBusDevice parent_obj;
1348
1349 MemoryRegion iomem;
1350 qemu_irq irq;
1351 SSIBus *bus;
1352
1353 uint16_t sscr[2];
1354 uint16_t sssr;
1355
1356 uint16_t rx_fifo[8];
1357 uint8_t rx_level;
1358 uint8_t rx_start;
1359} StrongARMSSPState;
1360
1361#define SSCR0 0x60
1362#define SSCR1 0x64
1363#define SSDR 0x6c
1364#define SSSR 0x74
1365
1366
1367#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1368#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1369#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1370#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1371#define SSCR0_SSE (1 << 7)
1372#define SSCR0_DSS(x) (((x) & 0xf) + 1)
1373#define SSCR1_RIE (1 << 0)
1374#define SSCR1_TIE (1 << 1)
1375#define SSCR1_LBM (1 << 2)
1376#define SSSR_TNF (1 << 2)
1377#define SSSR_RNE (1 << 3)
1378#define SSSR_TFS (1 << 5)
1379#define SSSR_RFS (1 << 6)
1380#define SSSR_ROR (1 << 7)
1381#define SSSR_RW 0x0080
1382
1383static void strongarm_ssp_int_update(StrongARMSSPState *s)
1384{
1385 int level = 0;
1386
1387 level |= (s->sssr & SSSR_ROR);
1388 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1389 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1390 qemu_set_irq(s->irq, level);
1391}
1392
1393static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1394{
1395 s->sssr &= ~SSSR_TFS;
1396 s->sssr &= ~SSSR_TNF;
1397 if (s->sscr[0] & SSCR0_SSE) {
1398 if (s->rx_level >= 4) {
1399 s->sssr |= SSSR_RFS;
1400 } else {
1401 s->sssr &= ~SSSR_RFS;
1402 }
1403 if (s->rx_level) {
1404 s->sssr |= SSSR_RNE;
1405 } else {
1406 s->sssr &= ~SSSR_RNE;
1407 }
1408
1409
1410 s->sssr |= SSSR_TFS;
1411 s->sssr |= SSSR_TNF;
1412 }
1413
1414 strongarm_ssp_int_update(s);
1415}
1416
1417static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1418 unsigned size)
1419{
1420 StrongARMSSPState *s = opaque;
1421 uint32_t retval;
1422
1423 switch (addr) {
1424 case SSCR0:
1425 return s->sscr[0];
1426 case SSCR1:
1427 return s->sscr[1];
1428 case SSSR:
1429 return s->sssr;
1430 case SSDR:
1431 if (~s->sscr[0] & SSCR0_SSE) {
1432 return 0xffffffff;
1433 }
1434 if (s->rx_level < 1) {
1435 printf("%s: SSP Rx Underrun\n", __func__);
1436 return 0xffffffff;
1437 }
1438 s->rx_level--;
1439 retval = s->rx_fifo[s->rx_start++];
1440 s->rx_start &= 0x7;
1441 strongarm_ssp_fifo_update(s);
1442 return retval;
1443 default:
1444 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1445 break;
1446 }
1447 return 0;
1448}
1449
1450static void strongarm_ssp_write(void *opaque, hwaddr addr,
1451 uint64_t value, unsigned size)
1452{
1453 StrongARMSSPState *s = opaque;
1454
1455 switch (addr) {
1456 case SSCR0:
1457 s->sscr[0] = value & 0xffbf;
1458 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1459 printf("%s: Wrong data size: %i bits\n", __func__,
1460 (int)SSCR0_DSS(value));
1461 }
1462 if (!(value & SSCR0_SSE)) {
1463 s->sssr = 0;
1464 s->rx_level = 0;
1465 }
1466 strongarm_ssp_fifo_update(s);
1467 break;
1468
1469 case SSCR1:
1470 s->sscr[1] = value & 0x2f;
1471 if (value & SSCR1_LBM) {
1472 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1473 }
1474 strongarm_ssp_fifo_update(s);
1475 break;
1476
1477 case SSSR:
1478 s->sssr &= ~(value & SSSR_RW);
1479 strongarm_ssp_int_update(s);
1480 break;
1481
1482 case SSDR:
1483 if (SSCR0_UWIRE(s->sscr[0])) {
1484 value &= 0xff;
1485 } else
1486
1487 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1488
1489
1490
1491
1492 if (s->sscr[0] & SSCR0_SSE) {
1493 uint32_t readval;
1494 if (s->sscr[1] & SSCR1_LBM) {
1495 readval = value;
1496 } else {
1497 readval = ssi_transfer(s->bus, value);
1498 }
1499
1500 if (s->rx_level < 0x08) {
1501 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1502 } else {
1503 s->sssr |= SSSR_ROR;
1504 }
1505 }
1506 strongarm_ssp_fifo_update(s);
1507 break;
1508
1509 default:
1510 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1511 break;
1512 }
1513}
1514
1515static const MemoryRegionOps strongarm_ssp_ops = {
1516 .read = strongarm_ssp_read,
1517 .write = strongarm_ssp_write,
1518 .endianness = DEVICE_NATIVE_ENDIAN,
1519};
1520
1521static int strongarm_ssp_post_load(void *opaque, int version_id)
1522{
1523 StrongARMSSPState *s = opaque;
1524
1525 strongarm_ssp_fifo_update(s);
1526
1527 return 0;
1528}
1529
1530static int strongarm_ssp_init(SysBusDevice *sbd)
1531{
1532 DeviceState *dev = DEVICE(sbd);
1533 StrongARMSSPState *s = STRONGARM_SSP(dev);
1534
1535 sysbus_init_irq(sbd, &s->irq);
1536
1537 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s,
1538 "ssp", 0x1000);
1539 sysbus_init_mmio(sbd, &s->iomem);
1540
1541 s->bus = ssi_create_bus(dev, "ssi");
1542 return 0;
1543}
1544
1545static void strongarm_ssp_reset(DeviceState *dev)
1546{
1547 StrongARMSSPState *s = STRONGARM_SSP(dev);
1548
1549 s->sssr = 0x03;
1550 s->rx_start = 0;
1551 s->rx_level = 0;
1552}
1553
1554static const VMStateDescription vmstate_strongarm_ssp_regs = {
1555 .name = "strongarm-ssp",
1556 .version_id = 0,
1557 .minimum_version_id = 0,
1558 .post_load = strongarm_ssp_post_load,
1559 .fields = (VMStateField[]) {
1560 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1561 VMSTATE_UINT16(sssr, StrongARMSSPState),
1562 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1563 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1564 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1565 VMSTATE_END_OF_LIST(),
1566 },
1567};
1568
1569static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1570{
1571 DeviceClass *dc = DEVICE_CLASS(klass);
1572 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1573
1574 k->init = strongarm_ssp_init;
1575 dc->desc = "StrongARM SSP controller";
1576 dc->reset = strongarm_ssp_reset;
1577 dc->vmsd = &vmstate_strongarm_ssp_regs;
1578}
1579
1580static const TypeInfo strongarm_ssp_info = {
1581 .name = TYPE_STRONGARM_SSP,
1582 .parent = TYPE_SYS_BUS_DEVICE,
1583 .instance_size = sizeof(StrongARMSSPState),
1584 .class_init = strongarm_ssp_class_init,
1585};
1586
1587
1588StrongARMState *sa1110_init(MemoryRegion *sysmem,
1589 unsigned int sdram_size, const char *rev)
1590{
1591 StrongARMState *s;
1592 int i;
1593
1594 s = g_new0(StrongARMState, 1);
1595
1596 if (!rev) {
1597 rev = "sa1110-b5";
1598 }
1599
1600 if (strncmp(rev, "sa1110", 6)) {
1601 error_report("Machine requires a SA1110 processor.");
1602 exit(1);
1603 }
1604
1605 s->cpu = cpu_arm_init(rev);
1606
1607 if (!s->cpu) {
1608 error_report("Unable to find CPU definition");
1609 exit(1);
1610 }
1611
1612 memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
1613 sdram_size);
1614 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1615
1616 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1617 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
1618 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
1619 NULL);
1620
1621 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1622 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1623 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1624 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1625 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1626 NULL);
1627
1628 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
1629 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1630
1631 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1632
1633 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
1634
1635 for (i = 0; sa_serial[i].io_base; i++) {
1636 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
1637 qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1638 qdev_init_nofail(dev);
1639 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1640 sa_serial[i].io_base);
1641 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1642 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1643 }
1644
1645 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
1646 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1647 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1648
1649 return s;
1650}
1651
1652static void strongarm_register_types(void)
1653{
1654 type_register_static(&strongarm_pic_info);
1655 type_register_static(&strongarm_rtc_sysbus_info);
1656 type_register_static(&strongarm_gpio_info);
1657 type_register_static(&strongarm_ppc_info);
1658 type_register_static(&strongarm_uart_info);
1659 type_register_static(&strongarm_ssp_info);
1660}
1661
1662type_init(strongarm_register_types)
1663
