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31#include "qemu/osdep.h"
32#include "qapi/error.h"
33#include "hw/sysbus.h"
34#include "hw/arm/arm.h"
35#include "hw/arm/primecell.h"
36#include "hw/arm/virt.h"
37#include "hw/devices.h"
38#include "net/net.h"
39#include "sysemu/block-backend.h"
40#include "sysemu/device_tree.h"
41#include "sysemu/sysemu.h"
42#include "sysemu/kvm.h"
43#include "hw/boards.h"
44#include "hw/loader.h"
45#include "exec/address-spaces.h"
46#include "qemu/bitops.h"
47#include "qemu/error-report.h"
48#include "hw/pci-host/gpex.h"
49#include "hw/arm/virt-acpi-build.h"
50#include "hw/arm/sysbus-fdt.h"
51#include "hw/platform-bus.h"
52#include "hw/arm/fdt.h"
53#include "hw/intc/arm_gic_common.h"
54#include "kvm_arm.h"
55#include "hw/smbios/smbios.h"
56#include "qapi/visitor.h"
57#include "standard-headers/linux/input.h"
58
59
60#define NUM_IRQS 256
61
62#define PLATFORM_BUS_NUM_IRQS 64
63
64static ARMPlatformBusSystemParams platform_bus_params;
65
66typedef struct VirtBoardInfo {
67 struct arm_boot_info bootinfo;
68 const char *cpu_model;
69 const MemMapEntry *memmap;
70 const int *irqmap;
71 int smp_cpus;
72 void *fdt;
73 int fdt_size;
74 uint32_t clock_phandle;
75 uint32_t gic_phandle;
76 uint32_t v2m_phandle;
77 bool using_psci;
78} VirtBoardInfo;
79
80typedef struct {
81 MachineClass parent;
82 VirtBoardInfo *daughterboard;
83} VirtMachineClass;
84
85typedef struct {
86 MachineState parent;
87 bool secure;
88 bool highmem;
89 int32_t gic_version;
90} VirtMachineState;
91
92#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
93#define VIRT_MACHINE(obj) \
94 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
95#define VIRT_MACHINE_GET_CLASS(obj) \
96 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
97#define VIRT_MACHINE_CLASS(klass) \
98 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
99
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112
113
114#define RAMLIMIT_GB 255
115#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
116
117
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126
127
128
129static const MemMapEntry a15memmap[] = {
130
131 [VIRT_FLASH] = { 0, 0x08000000 },
132 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
133
134 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
135 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
136 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
137
138 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
139
140 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
141 [VIRT_UART] = { 0x09000000, 0x00001000 },
142 [VIRT_RTC] = { 0x09010000, 0x00001000 },
143 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
144 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
145 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
146 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
147
148 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
149 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
150 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
151 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
152 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
153 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
154
155 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
156};
157
158static const int a15irqmap[] = {
159 [VIRT_UART] = 1,
160 [VIRT_RTC] = 2,
161 [VIRT_PCIE] = 3,
162 [VIRT_GPIO] = 7,
163 [VIRT_SECURE_UART] = 8,
164 [VIRT_MMIO] = 16,
165 [VIRT_GIC_V2M] = 48,
166 [VIRT_PLATFORM_BUS] = 112,
167};
168
169static VirtBoardInfo machines[] = {
170 {
171 .cpu_model = "cortex-a15",
172 .memmap = a15memmap,
173 .irqmap = a15irqmap,
174 },
175 {
176 .cpu_model = "cortex-a53",
177 .memmap = a15memmap,
178 .irqmap = a15irqmap,
179 },
180 {
181 .cpu_model = "cortex-a57",
182 .memmap = a15memmap,
183 .irqmap = a15irqmap,
184 },
185 {
186 .cpu_model = "host",
187 .memmap = a15memmap,
188 .irqmap = a15irqmap,
189 },
190};
191
192static VirtBoardInfo *find_machine_info(const char *cpu)
193{
194 int i;
195
196 for (i = 0; i < ARRAY_SIZE(machines); i++) {
197 if (strcmp(cpu, machines[i].cpu_model) == 0) {
198 return &machines[i];
199 }
200 }
201 return NULL;
202}
203
204static void create_fdt(VirtBoardInfo *vbi)
205{
206 void *fdt = create_device_tree(&vbi->fdt_size);
207
208 if (!fdt) {
209 error_report("create_device_tree() failed");
210 exit(1);
211 }
212
213 vbi->fdt = fdt;
214
215
216 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
217 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
218 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
219
220
221
222
223
224 qemu_fdt_add_subnode(fdt, "/chosen");
225 qemu_fdt_add_subnode(fdt, "/memory");
226 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
227
228
229
230
231
232
233 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt);
234 qemu_fdt_add_subnode(fdt, "/apb-pclk");
235 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
236 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
237 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
238 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
239 "clk24mhz");
240 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle);
241
242}
243
244static void fdt_add_psci_node(const VirtBoardInfo *vbi)
245{
246 uint32_t cpu_suspend_fn;
247 uint32_t cpu_off_fn;
248 uint32_t cpu_on_fn;
249 uint32_t migrate_fn;
250 void *fdt = vbi->fdt;
251 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
252
253 if (!vbi->using_psci) {
254 return;
255 }
256
257 qemu_fdt_add_subnode(fdt, "/psci");
258 if (armcpu->psci_version == 2) {
259 const char comp[] = "arm,psci-0.2\0arm,psci";
260 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
261
262 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
263 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
264 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
265 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
266 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
267 } else {
268 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
269 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
270 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
271 }
272 } else {
273 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
274
275 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
276 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
277 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
278 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
279 }
280
281
282
283
284
285
286 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc");
287
288 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
289 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
290 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
291 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
292}
293
294static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, int gictype)
295{
296
297
298
299
300 ARMCPU *armcpu;
301 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
302
303 if (gictype == 2) {
304 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
305 GIC_FDT_IRQ_PPI_CPU_WIDTH,
306 (1 << vbi->smp_cpus) - 1);
307 }
308
309 qemu_fdt_add_subnode(vbi->fdt, "/timer");
310
311 armcpu = ARM_CPU(qemu_get_cpu(0));
312 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
313 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
314 qemu_fdt_setprop(vbi->fdt, "/timer", "compatible",
315 compat, sizeof(compat));
316 } else {
317 qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible",
318 "arm,armv7-timer");
319 }
320 qemu_fdt_setprop(vbi->fdt, "/timer", "always-on", NULL, 0);
321 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts",
322 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
323 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
324 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
325 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
326}
327
328static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
329{
330 int cpu;
331 int addr_cells = 1;
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346 for (cpu = 0; cpu < vbi->smp_cpus; cpu++) {
347 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
348
349 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
350 addr_cells = 2;
351 break;
352 }
353 }
354
355 qemu_fdt_add_subnode(vbi->fdt, "/cpus");
356 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells);
357 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0);
358
359 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) {
360 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
361 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
362
363 qemu_fdt_add_subnode(vbi->fdt, nodename);
364 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu");
365 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible",
366 armcpu->dtb_compatible);
367
368 if (vbi->using_psci && vbi->smp_cpus > 1) {
369 qemu_fdt_setprop_string(vbi->fdt, nodename,
370 "enable-method", "psci");
371 }
372
373 if (addr_cells == 2) {
374 qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg",
375 armcpu->mp_affinity);
376 } else {
377 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg",
378 armcpu->mp_affinity);
379 }
380
381 g_free(nodename);
382 }
383}
384
385static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi)
386{
387 vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
388 qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m");
389 qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible",
390 "arm,gic-v2m-frame");
391 qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0);
392 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg",
393 2, vbi->memmap[VIRT_GIC_V2M].base,
394 2, vbi->memmap[VIRT_GIC_V2M].size);
395 qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle);
396}
397
398static void fdt_add_gic_node(VirtBoardInfo *vbi, int type)
399{
400 vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
401 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle);
402
403 qemu_fdt_add_subnode(vbi->fdt, "/intc");
404 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3);
405 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0);
406 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2);
407 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2);
408 qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0);
409 if (type == 3) {
410 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
411 "arm,gic-v3");
412 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
413 2, vbi->memmap[VIRT_GIC_DIST].base,
414 2, vbi->memmap[VIRT_GIC_DIST].size,
415 2, vbi->memmap[VIRT_GIC_REDIST].base,
416 2, vbi->memmap[VIRT_GIC_REDIST].size);
417 } else {
418
419 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
420 "arm,cortex-a15-gic");
421 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
422 2, vbi->memmap[VIRT_GIC_DIST].base,
423 2, vbi->memmap[VIRT_GIC_DIST].size,
424 2, vbi->memmap[VIRT_GIC_CPU].base,
425 2, vbi->memmap[VIRT_GIC_CPU].size);
426 }
427
428 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle);
429}
430
431static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic)
432{
433 int i;
434 int irq = vbi->irqmap[VIRT_GIC_V2M];
435 DeviceState *dev;
436
437 dev = qdev_create(NULL, "arm-gicv2m");
438 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base);
439 qdev_prop_set_uint32(dev, "base-spi", irq);
440 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
441 qdev_init_nofail(dev);
442
443 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
444 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
445 }
446
447 fdt_add_v2m_gic_node(vbi);
448}
449
450static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure)
451{
452
453 DeviceState *gicdev;
454 SysBusDevice *gicbusdev;
455 const char *gictype;
456 int i;
457
458 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
459
460 gicdev = qdev_create(NULL, gictype);
461 qdev_prop_set_uint32(gicdev, "revision", type);
462 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
463
464
465
466 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
467 if (!kvm_irqchip_in_kernel()) {
468 qdev_prop_set_bit(gicdev, "has-security-extensions", secure);
469 }
470 qdev_init_nofail(gicdev);
471 gicbusdev = SYS_BUS_DEVICE(gicdev);
472 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base);
473 if (type == 3) {
474 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base);
475 } else {
476 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
477 }
478
479
480
481
482
483 for (i = 0; i < smp_cpus; i++) {
484 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
485 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
486 int irq;
487
488
489
490 const int timer_irq[] = {
491 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
492 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
493 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
494 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
495 };
496
497 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
498 qdev_connect_gpio_out(cpudev, irq,
499 qdev_get_gpio_in(gicdev,
500 ppibase + timer_irq[irq]));
501 }
502
503 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
504 sysbus_connect_irq(gicbusdev, i + smp_cpus,
505 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
506 }
507
508 for (i = 0; i < NUM_IRQS; i++) {
509 pic[i] = qdev_get_gpio_in(gicdev, i);
510 }
511
512 fdt_add_gic_node(vbi, type);
513
514 if (type == 2) {
515 create_v2m(vbi, pic);
516 }
517}
518
519static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart,
520 MemoryRegion *mem)
521{
522 char *nodename;
523 hwaddr base = vbi->memmap[uart].base;
524 hwaddr size = vbi->memmap[uart].size;
525 int irq = vbi->irqmap[uart];
526 const char compat[] = "arm,pl011\0arm,primecell";
527 const char clocknames[] = "uartclk\0apb_pclk";
528 DeviceState *dev = qdev_create(NULL, "pl011");
529 SysBusDevice *s = SYS_BUS_DEVICE(dev);
530
531 qdev_init_nofail(dev);
532 memory_region_add_subregion(mem, base,
533 sysbus_mmio_get_region(s, 0));
534 sysbus_connect_irq(s, 0, pic[irq]);
535
536 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
537 qemu_fdt_add_subnode(vbi->fdt, nodename);
538
539 qemu_fdt_setprop(vbi->fdt, nodename, "compatible",
540 compat, sizeof(compat));
541 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
542 2, base, 2, size);
543 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
544 GIC_FDT_IRQ_TYPE_SPI, irq,
545 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
546 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks",
547 vbi->clock_phandle, vbi->clock_phandle);
548 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names",
549 clocknames, sizeof(clocknames));
550
551 if (uart == VIRT_UART) {
552 qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename);
553 } else {
554
555 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled");
556 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay");
557 }
558
559 g_free(nodename);
560}
561
562static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic)
563{
564 char *nodename;
565 hwaddr base = vbi->memmap[VIRT_RTC].base;
566 hwaddr size = vbi->memmap[VIRT_RTC].size;
567 int irq = vbi->irqmap[VIRT_RTC];
568 const char compat[] = "arm,pl031\0arm,primecell";
569
570 sysbus_create_simple("pl031", base, pic[irq]);
571
572 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
573 qemu_fdt_add_subnode(vbi->fdt, nodename);
574 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat));
575 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
576 2, base, 2, size);
577 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
578 GIC_FDT_IRQ_TYPE_SPI, irq,
579 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
580 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle);
581 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk");
582 g_free(nodename);
583}
584
585static DeviceState *gpio_key_dev;
586static void virt_powerdown_req(Notifier *n, void *opaque)
587{
588
589 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
590}
591
592static Notifier virt_system_powerdown_notifier = {
593 .notify = virt_powerdown_req
594};
595
596static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic)
597{
598 char *nodename;
599 DeviceState *pl061_dev;
600 hwaddr base = vbi->memmap[VIRT_GPIO].base;
601 hwaddr size = vbi->memmap[VIRT_GPIO].size;
602 int irq = vbi->irqmap[VIRT_GPIO];
603 const char compat[] = "arm,pl061\0arm,primecell";
604
605 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
606
607 uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt);
608 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
609 qemu_fdt_add_subnode(vbi->fdt, nodename);
610 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
611 2, base, 2, size);
612 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat));
613 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2);
614 qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0);
615 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
616 GIC_FDT_IRQ_TYPE_SPI, irq,
617 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
618 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle);
619 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk");
620 qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle);
621
622 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
623 qdev_get_gpio_in(pl061_dev, 3));
624 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys");
625 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys");
626 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0);
627 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1);
628
629 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff");
630 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff",
631 "label", "GPIO Key Poweroff");
632 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code",
633 KEY_POWER);
634 qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff",
635 "gpios", phandle, 3, 0);
636
637
638 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
639
640 g_free(nodename);
641}
642
643static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic)
644{
645 int i;
646 hwaddr size = vbi->memmap[VIRT_MMIO].size;
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
676 int irq = vbi->irqmap[VIRT_MMIO] + i;
677 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size;
678
679 sysbus_create_simple("virtio-mmio", base, pic[irq]);
680 }
681
682
683
684
685
686
687
688
689 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
690 char *nodename;
691 int irq = vbi->irqmap[VIRT_MMIO] + i;
692 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size;
693
694 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
695 qemu_fdt_add_subnode(vbi->fdt, nodename);
696 qemu_fdt_setprop_string(vbi->fdt, nodename,
697 "compatible", "virtio,mmio");
698 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
699 2, base, 2, size);
700 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
701 GIC_FDT_IRQ_TYPE_SPI, irq,
702 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
703 g_free(nodename);
704 }
705}
706
707static void create_one_flash(const char *name, hwaddr flashbase,
708 hwaddr flashsize, const char *file,
709 MemoryRegion *sysmem)
710{
711
712
713
714 DriveInfo *dinfo = drive_get_next(IF_PFLASH);
715 DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
716 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
717 const uint64_t sectorlength = 256 * 1024;
718
719 if (dinfo) {
720 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
721 &error_abort);
722 }
723
724 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
725 qdev_prop_set_uint64(dev, "sector-length", sectorlength);
726 qdev_prop_set_uint8(dev, "width", 4);
727 qdev_prop_set_uint8(dev, "device-width", 2);
728 qdev_prop_set_bit(dev, "big-endian", false);
729 qdev_prop_set_uint16(dev, "id0", 0x89);
730 qdev_prop_set_uint16(dev, "id1", 0x18);
731 qdev_prop_set_uint16(dev, "id2", 0x00);
732 qdev_prop_set_uint16(dev, "id3", 0x00);
733 qdev_prop_set_string(dev, "name", name);
734 qdev_init_nofail(dev);
735
736 memory_region_add_subregion(sysmem, flashbase,
737 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
738
739 if (file) {
740 char *fn;
741 int image_size;
742
743 if (drive_get(IF_PFLASH, 0, 0)) {
744 error_report("The contents of the first flash device may be "
745 "specified with -bios or with -drive if=pflash... "
746 "but you cannot use both options at once");
747 exit(1);
748 }
749 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
750 if (!fn) {
751 error_report("Could not find ROM image '%s'", file);
752 exit(1);
753 }
754 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
755 g_free(fn);
756 if (image_size < 0) {
757 error_report("Could not load ROM image '%s'", file);
758 exit(1);
759 }
760 }
761}
762
763static void create_flash(const VirtBoardInfo *vbi,
764 MemoryRegion *sysmem,
765 MemoryRegion *secure_sysmem)
766{
767
768
769
770
771
772
773
774
775 hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2;
776 hwaddr flashbase = vbi->memmap[VIRT_FLASH].base;
777 char *nodename;
778
779 create_one_flash("virt.flash0", flashbase, flashsize,
780 bios_name, secure_sysmem);
781 create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
782 NULL, sysmem);
783
784 if (sysmem == secure_sysmem) {
785
786 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
787 qemu_fdt_add_subnode(vbi->fdt, nodename);
788 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash");
789 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
790 2, flashbase, 2, flashsize,
791 2, flashbase + flashsize, 2, flashsize);
792 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4);
793 g_free(nodename);
794 } else {
795
796
797
798 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
799 qemu_fdt_add_subnode(vbi->fdt, nodename);
800 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash");
801 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
802 2, flashbase, 2, flashsize);
803 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4);
804 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled");
805 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay");
806 g_free(nodename);
807
808 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
809 qemu_fdt_add_subnode(vbi->fdt, nodename);
810 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash");
811 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
812 2, flashbase + flashsize, 2, flashsize);
813 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4);
814 g_free(nodename);
815 }
816}
817
818static void create_fw_cfg(const VirtBoardInfo *vbi, AddressSpace *as)
819{
820 hwaddr base = vbi->memmap[VIRT_FW_CFG].base;
821 hwaddr size = vbi->memmap[VIRT_FW_CFG].size;
822 char *nodename;
823
824 fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
825
826 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
827 qemu_fdt_add_subnode(vbi->fdt, nodename);
828 qemu_fdt_setprop_string(vbi->fdt, nodename,
829 "compatible", "qemu,fw-cfg-mmio");
830 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
831 2, base, 2, size);
832 g_free(nodename);
833}
834
835static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
836 int first_irq, const char *nodename)
837{
838 int devfn, pin;
839 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
840 uint32_t *irq_map = full_irq_map;
841
842 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
843 for (pin = 0; pin < 4; pin++) {
844 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
845 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
846 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
847 int i;
848
849 uint32_t map[] = {
850 devfn << 8, 0, 0,
851 pin + 1,
852 gic_phandle, 0, 0, irq_type, irq_nr, irq_level };
853
854
855 for (i = 0; i < 10; i++) {
856 irq_map[i] = cpu_to_be32(map[i]);
857 }
858 irq_map += 10;
859 }
860 }
861
862 qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map",
863 full_irq_map, sizeof(full_irq_map));
864
865 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask",
866 0x1800, 0, 0,
867 0x7 );
868}
869
870static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
871 bool use_highmem)
872{
873 hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base;
874 hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size;
875 hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base;
876 hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size;
877 hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base;
878 hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size;
879 hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base;
880 hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size;
881 hwaddr base = base_mmio;
882 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
883 int irq = vbi->irqmap[VIRT_PCIE];
884 MemoryRegion *mmio_alias;
885 MemoryRegion *mmio_reg;
886 MemoryRegion *ecam_alias;
887 MemoryRegion *ecam_reg;
888 DeviceState *dev;
889 char *nodename;
890 int i;
891 PCIHostState *pci;
892
893 dev = qdev_create(NULL, TYPE_GPEX_HOST);
894 qdev_init_nofail(dev);
895
896
897 ecam_alias = g_new0(MemoryRegion, 1);
898 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
899 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
900 ecam_reg, 0, size_ecam);
901 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
902
903
904
905
906
907
908 mmio_alias = g_new0(MemoryRegion, 1);
909 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
910 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
911 mmio_reg, base_mmio, size_mmio);
912 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
913
914 if (use_highmem) {
915
916 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
917
918 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
919 mmio_reg, base_mmio_high, size_mmio_high);
920 memory_region_add_subregion(get_system_memory(), base_mmio_high,
921 high_mmio_alias);
922 }
923
924
925 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
926
927 for (i = 0; i < GPEX_NUM_IRQS; i++) {
928 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
929 }
930
931 pci = PCI_HOST_BRIDGE(dev);
932 if (pci->bus) {
933 for (i = 0; i < nb_nics; i++) {
934 NICInfo *nd = &nd_table[i];
935
936 if (!nd->model) {
937 nd->model = g_strdup("virtio");
938 }
939
940 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
941 }
942 }
943
944 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
945 qemu_fdt_add_subnode(vbi->fdt, nodename);
946 qemu_fdt_setprop_string(vbi->fdt, nodename,
947 "compatible", "pci-host-ecam-generic");
948 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci");
949 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3);
950 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2);
951 qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0,
952 nr_pcie_buses - 1);
953
954 if (vbi->v2m_phandle) {
955 qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent",
956 vbi->v2m_phandle);
957 }
958
959 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
960 2, base_ecam, 2, size_ecam);
961
962 if (use_highmem) {
963 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
964 1, FDT_PCI_RANGE_IOPORT, 2, 0,
965 2, base_pio, 2, size_pio,
966 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
967 2, base_mmio, 2, size_mmio,
968 1, FDT_PCI_RANGE_MMIO_64BIT,
969 2, base_mmio_high,
970 2, base_mmio_high, 2, size_mmio_high);
971 } else {
972 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
973 1, FDT_PCI_RANGE_IOPORT, 2, 0,
974 2, base_pio, 2, size_pio,
975 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
976 2, base_mmio, 2, size_mmio);
977 }
978
979 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1);
980 create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename);
981
982 g_free(nodename);
983}
984
985static void create_platform_bus(VirtBoardInfo *vbi, qemu_irq *pic)
986{
987 DeviceState *dev;
988 SysBusDevice *s;
989 int i;
990 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1);
991 MemoryRegion *sysmem = get_system_memory();
992
993 platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base;
994 platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size;
995 platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS];
996 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS;
997
998 fdt_params->system_params = &platform_bus_params;
999 fdt_params->binfo = &vbi->bootinfo;
1000 fdt_params->intc = "/intc";
1001
1002
1003
1004
1005 arm_register_platform_bus_fdt_creator(fdt_params);
1006
1007 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1008 dev->id = (char *) TYPE_PLATFORM_BUS_DEVICE;
1009 qdev_prop_set_uint32(dev, "num_irqs",
1010 platform_bus_params.platform_bus_num_irqs);
1011 qdev_prop_set_uint32(dev, "mmio_size",
1012 platform_bus_params.platform_bus_size);
1013 qdev_init_nofail(dev);
1014 s = SYS_BUS_DEVICE(dev);
1015
1016 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) {
1017 int irqn = platform_bus_params.platform_bus_first_irq + i;
1018 sysbus_connect_irq(s, i, pic[irqn]);
1019 }
1020
1021 memory_region_add_subregion(sysmem,
1022 platform_bus_params.platform_bus_base,
1023 sysbus_mmio_get_region(s, 0));
1024}
1025
1026static void create_secure_ram(VirtBoardInfo *vbi, MemoryRegion *secure_sysmem)
1027{
1028 MemoryRegion *secram = g_new(MemoryRegion, 1);
1029 char *nodename;
1030 hwaddr base = vbi->memmap[VIRT_SECURE_MEM].base;
1031 hwaddr size = vbi->memmap[VIRT_SECURE_MEM].size;
1032
1033 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal);
1034 vmstate_register_ram_global(secram);
1035 memory_region_add_subregion(secure_sysmem, base, secram);
1036
1037 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1038 qemu_fdt_add_subnode(vbi->fdt, nodename);
1039 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "memory");
1040 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base, 2, size);
1041 qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled");
1042 qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay");
1043
1044 g_free(nodename);
1045}
1046
1047static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1048{
1049 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo;
1050
1051 *fdt_size = board->fdt_size;
1052 return board->fdt;
1053}
1054
1055static void virt_build_smbios(VirtGuestInfo *guest_info)
1056{
1057 FWCfgState *fw_cfg = guest_info->fw_cfg;
1058 uint8_t *smbios_tables, *smbios_anchor;
1059 size_t smbios_tables_len, smbios_anchor_len;
1060 const char *product = "QEMU Virtual Machine";
1061
1062 if (!fw_cfg) {
1063 return;
1064 }
1065
1066 if (kvm_enabled()) {
1067 product = "KVM Virtual Machine";
1068 }
1069
1070 smbios_set_defaults("QEMU", product,
1071 "1.0", false, true, SMBIOS_ENTRY_POINT_30);
1072
1073 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
1074 &smbios_anchor, &smbios_anchor_len);
1075
1076 if (smbios_anchor) {
1077 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
1078 smbios_tables, smbios_tables_len);
1079 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
1080 smbios_anchor, smbios_anchor_len);
1081 }
1082}
1083
1084static
1085void virt_guest_info_machine_done(Notifier *notifier, void *data)
1086{
1087 VirtGuestInfoState *guest_info_state = container_of(notifier,
1088 VirtGuestInfoState, machine_done);
1089 virt_acpi_setup(&guest_info_state->info);
1090 virt_build_smbios(&guest_info_state->info);
1091}
1092
1093static void machvirt_init(MachineState *machine)
1094{
1095 VirtMachineState *vms = VIRT_MACHINE(machine);
1096 qemu_irq pic[NUM_IRQS];
1097 MemoryRegion *sysmem = get_system_memory();
1098 MemoryRegion *secure_sysmem = NULL;
1099 int gic_version = vms->gic_version;
1100 int n, virt_max_cpus;
1101 MemoryRegion *ram = g_new(MemoryRegion, 1);
1102 const char *cpu_model = machine->cpu_model;
1103 VirtBoardInfo *vbi;
1104 VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1105 VirtGuestInfo *guest_info = &guest_info_state->info;
1106 char **cpustr;
1107 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1108
1109 if (!cpu_model) {
1110 cpu_model = "cortex-a15";
1111 }
1112
1113
1114
1115
1116 if (!gic_version) {
1117 gic_version = kvm_arm_vgic_probe();
1118 if (!gic_version) {
1119 error_report("Unable to determine GIC version supported by host");
1120 error_printf("KVM acceleration is probably not supported\n");
1121 exit(1);
1122 }
1123 }
1124
1125
1126 cpustr = g_strsplit(cpu_model, ",", 2);
1127
1128 vbi = find_machine_info(cpustr[0]);
1129
1130 if (!vbi) {
1131 error_report("mach-virt: CPU %s not supported", cpustr[0]);
1132 exit(1);
1133 }
1134
1135
1136
1137
1138
1139
1140
1141
1142 vbi->using_psci = !(vms->secure && firmware_loaded);
1143
1144
1145
1146
1147 if (gic_version == 3) {
1148 virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000;
1149 } else {
1150 virt_max_cpus = GIC_NCPU;
1151 }
1152
1153 if (max_cpus > virt_max_cpus) {
1154 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1155 "supported by machine 'mach-virt' (%d)",
1156 max_cpus, virt_max_cpus);
1157 exit(1);
1158 }
1159
1160 vbi->smp_cpus = smp_cpus;
1161
1162 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) {
1163 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB);
1164 exit(1);
1165 }
1166
1167 if (vms->secure) {
1168 if (kvm_enabled()) {
1169 error_report("mach-virt: KVM does not support Security extensions");
1170 exit(1);
1171 }
1172
1173
1174
1175
1176
1177
1178 secure_sysmem = g_new(MemoryRegion, 1);
1179 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1180 UINT64_MAX);
1181 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1182 }
1183
1184 create_fdt(vbi);
1185
1186 for (n = 0; n < smp_cpus; n++) {
1187 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
1188 CPUClass *cc = CPU_CLASS(oc);
1189 Object *cpuobj;
1190 Error *err = NULL;
1191 char *cpuopts = g_strdup(cpustr[1]);
1192
1193 if (!oc) {
1194 error_report("Unable to find CPU definition");
1195 exit(1);
1196 }
1197 cpuobj = object_new(object_class_get_name(oc));
1198
1199
1200 cc->parse_features(CPU(cpuobj), cpuopts, &err);
1201 g_free(cpuopts);
1202 if (err) {
1203 error_report_err(err);
1204 exit(1);
1205 }
1206
1207 if (!vms->secure) {
1208 object_property_set_bool(cpuobj, false, "has_el3", NULL);
1209 }
1210
1211 if (vbi->using_psci) {
1212 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC,
1213 "psci-conduit", NULL);
1214
1215
1216 if (n > 0) {
1217 object_property_set_bool(cpuobj, true,
1218 "start-powered-off", NULL);
1219 }
1220 }
1221
1222 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1223 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base,
1224 "reset-cbar", &error_abort);
1225 }
1226
1227 object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1228 &error_abort);
1229 if (vms->secure) {
1230 object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1231 "secure-memory", &error_abort);
1232 }
1233
1234 object_property_set_bool(cpuobj, true, "realized", NULL);
1235 }
1236 g_strfreev(cpustr);
1237 fdt_add_timer_nodes(vbi, gic_version);
1238 fdt_add_cpu_nodes(vbi);
1239 fdt_add_psci_node(vbi);
1240
1241 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1242 machine->ram_size);
1243 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram);
1244
1245 create_flash(vbi, sysmem, secure_sysmem ? secure_sysmem : sysmem);
1246
1247 create_gic(vbi, pic, gic_version, vms->secure);
1248
1249 create_uart(vbi, pic, VIRT_UART, sysmem);
1250
1251 if (vms->secure) {
1252 create_secure_ram(vbi, secure_sysmem);
1253 create_uart(vbi, pic, VIRT_SECURE_UART, secure_sysmem);
1254 }
1255
1256 create_rtc(vbi, pic);
1257
1258 create_pcie(vbi, pic, vms->highmem);
1259
1260 create_gpio(vbi, pic);
1261
1262
1263
1264
1265
1266 create_virtio_devices(vbi, pic);
1267
1268 create_fw_cfg(vbi, &address_space_memory);
1269 rom_set_fw(fw_cfg_find());
1270
1271 guest_info->smp_cpus = smp_cpus;
1272 guest_info->fw_cfg = fw_cfg_find();
1273 guest_info->memmap = vbi->memmap;
1274 guest_info->irqmap = vbi->irqmap;
1275 guest_info->use_highmem = vms->highmem;
1276 guest_info->gic_version = gic_version;
1277 guest_info_state->machine_done.notify = virt_guest_info_machine_done;
1278 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1279
1280 vbi->bootinfo.ram_size = machine->ram_size;
1281 vbi->bootinfo.kernel_filename = machine->kernel_filename;
1282 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1283 vbi->bootinfo.initrd_filename = machine->initrd_filename;
1284 vbi->bootinfo.nb_cpus = smp_cpus;
1285 vbi->bootinfo.board_id = -1;
1286 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base;
1287 vbi->bootinfo.get_dtb = machvirt_dtb;
1288 vbi->bootinfo.firmware_loaded = firmware_loaded;
1289 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo);
1290
1291
1292
1293
1294
1295
1296
1297 create_platform_bus(vbi, pic);
1298}
1299
1300static bool virt_get_secure(Object *obj, Error **errp)
1301{
1302 VirtMachineState *vms = VIRT_MACHINE(obj);
1303
1304 return vms->secure;
1305}
1306
1307static void virt_set_secure(Object *obj, bool value, Error **errp)
1308{
1309 VirtMachineState *vms = VIRT_MACHINE(obj);
1310
1311 vms->secure = value;
1312}
1313
1314static bool virt_get_highmem(Object *obj, Error **errp)
1315{
1316 VirtMachineState *vms = VIRT_MACHINE(obj);
1317
1318 return vms->highmem;
1319}
1320
1321static void virt_set_highmem(Object *obj, bool value, Error **errp)
1322{
1323 VirtMachineState *vms = VIRT_MACHINE(obj);
1324
1325 vms->highmem = value;
1326}
1327
1328static char *virt_get_gic_version(Object *obj, Error **errp)
1329{
1330 VirtMachineState *vms = VIRT_MACHINE(obj);
1331 const char *val = vms->gic_version == 3 ? "3" : "2";
1332
1333 return g_strdup(val);
1334}
1335
1336static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1337{
1338 VirtMachineState *vms = VIRT_MACHINE(obj);
1339
1340 if (!strcmp(value, "3")) {
1341 vms->gic_version = 3;
1342 } else if (!strcmp(value, "2")) {
1343 vms->gic_version = 2;
1344 } else if (!strcmp(value, "host")) {
1345 vms->gic_version = 0;
1346 } else {
1347 error_setg(errp, "Invalid gic-version value");
1348 error_append_hint(errp, "Valid values are 3, 2, host.\n");
1349 }
1350}
1351
1352static void virt_machine_class_init(ObjectClass *oc, void *data)
1353{
1354 MachineClass *mc = MACHINE_CLASS(oc);
1355
1356 mc->init = machvirt_init;
1357
1358
1359
1360
1361 mc->max_cpus = MAX_CPUMASK_BITS;
1362 mc->has_dynamic_sysbus = true;
1363 mc->block_default_type = IF_VIRTIO;
1364 mc->no_cdrom = 1;
1365 mc->pci_allow_0_address = true;
1366}
1367
1368static const TypeInfo virt_machine_info = {
1369 .name = TYPE_VIRT_MACHINE,
1370 .parent = TYPE_MACHINE,
1371 .abstract = true,
1372 .instance_size = sizeof(VirtMachineState),
1373 .class_size = sizeof(VirtMachineClass),
1374 .class_init = virt_machine_class_init,
1375};
1376
1377static void virt_2_6_instance_init(Object *obj)
1378{
1379 VirtMachineState *vms = VIRT_MACHINE(obj);
1380
1381
1382
1383
1384
1385 vms->secure = false;
1386 object_property_add_bool(obj, "secure", virt_get_secure,
1387 virt_set_secure, NULL);
1388 object_property_set_description(obj, "secure",
1389 "Set on/off to enable/disable the ARM "
1390 "Security Extensions (TrustZone)",
1391 NULL);
1392
1393
1394 vms->highmem = true;
1395 object_property_add_bool(obj, "highmem", virt_get_highmem,
1396 virt_set_highmem, NULL);
1397 object_property_set_description(obj, "highmem",
1398 "Set on/off to enable/disable using "
1399 "physical address space above 32 bits",
1400 NULL);
1401
1402 vms->gic_version = 2;
1403 object_property_add_str(obj, "gic-version", virt_get_gic_version,
1404 virt_set_gic_version, NULL);
1405 object_property_set_description(obj, "gic-version",
1406 "Set GIC version. "
1407 "Valid values are 2, 3 and host", NULL);
1408}
1409
1410static void virt_2_6_class_init(ObjectClass *oc, void *data)
1411{
1412 MachineClass *mc = MACHINE_CLASS(oc);
1413 static GlobalProperty compat_props[] = {
1414 { }
1415 };
1416
1417 mc->desc = "QEMU 2.6 ARM Virtual Machine";
1418 mc->alias = "virt";
1419 mc->compat_props = compat_props;
1420}
1421
1422static const TypeInfo machvirt_info = {
1423 .name = MACHINE_TYPE_NAME("virt-2.6"),
1424 .parent = TYPE_VIRT_MACHINE,
1425 .instance_init = virt_2_6_instance_init,
1426 .class_init = virt_2_6_class_init,
1427};
1428
1429static void machvirt_machine_init(void)
1430{
1431 type_register_static(&virt_machine_info);
1432 type_register_static(&machvirt_info);
1433}
1434
1435type_init(machvirt_machine_init);
1436