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38#include "qemu/osdep.h"
39#include "hw/hw.h"
40#include "hw/block/flash.h"
41#include "qapi/error.h"
42#include "qemu/timer.h"
43#include "sysemu/block-backend.h"
44#include "exec/address-spaces.h"
45#include "qemu/host-utils.h"
46#include "hw/sysbus.h"
47
48
49#ifdef PFLASH_DEBUG
50#define DPRINTF(fmt, ...) \
51do { \
52 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
53} while (0)
54#else
55#define DPRINTF(fmt, ...) do { } while (0)
56#endif
57
58#define PFLASH_LAZY_ROMD_THRESHOLD 42
59
60#define TYPE_CFI_PFLASH02 "cfi.pflash02"
61#define CFI_PFLASH02(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH02)
62
63struct pflash_t {
64
65 SysBusDevice parent_obj;
66
67
68 BlockBackend *blk;
69 uint32_t sector_len;
70 uint32_t nb_blocs;
71 uint32_t chip_len;
72 uint8_t mappings;
73 uint8_t width;
74 uint8_t be;
75 int wcycle;
76 int bypass;
77 int ro;
78 uint8_t cmd;
79 uint8_t status;
80
81 uint16_t ident0;
82 uint16_t ident1;
83 uint16_t ident2;
84 uint16_t ident3;
85 uint16_t unlock_addr0;
86 uint16_t unlock_addr1;
87 uint8_t cfi_len;
88 uint8_t cfi_table[0x52];
89 QEMUTimer *timer;
90
91
92
93
94 MemoryRegion mem;
95 MemoryRegion *mem_mappings;
96 MemoryRegion orig_mem;
97 int rom_mode;
98 int read_counter;
99 char *name;
100 void *storage;
101};
102
103
104
105
106static void pflash_setup_mappings(pflash_t *pfl)
107{
108 unsigned i;
109 hwaddr size = memory_region_size(&pfl->orig_mem);
110
111 memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
112 pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
113 for (i = 0; i < pfl->mappings; ++i) {
114 memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
115 "pflash-alias", &pfl->orig_mem, 0, size);
116 memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
117 }
118}
119
120static void pflash_register_memory(pflash_t *pfl, int rom_mode)
121{
122 memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
123 pfl->rom_mode = rom_mode;
124}
125
126static void pflash_timer (void *opaque)
127{
128 pflash_t *pfl = opaque;
129
130 DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
131
132 pfl->status ^= 0x80;
133 if (pfl->bypass) {
134 pfl->wcycle = 2;
135 } else {
136 pflash_register_memory(pfl, 1);
137 pfl->wcycle = 0;
138 }
139 pfl->cmd = 0;
140}
141
142static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
143 int width, int be)
144{
145 hwaddr boff;
146 uint32_t ret;
147 uint8_t *p;
148
149 DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset);
150 ret = -1;
151
152 if (!pfl->rom_mode && pfl->wcycle == 0 &&
153 ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
154 pflash_register_memory(pfl, 1);
155 }
156 offset &= pfl->chip_len - 1;
157 boff = offset & 0xFF;
158 if (pfl->width == 2)
159 boff = boff >> 1;
160 else if (pfl->width == 4)
161 boff = boff >> 2;
162 switch (pfl->cmd) {
163 default:
164
165 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
166 pfl->wcycle = 0;
167 pfl->cmd = 0;
168
169 case 0x80:
170
171 case 0x00:
172 flash_read:
173
174 p = pfl->storage;
175 switch (width) {
176 case 1:
177 ret = p[offset];
178
179 break;
180 case 2:
181 if (be) {
182 ret = p[offset] << 8;
183 ret |= p[offset + 1];
184 } else {
185 ret = p[offset];
186 ret |= p[offset + 1] << 8;
187 }
188
189 break;
190 case 4:
191 if (be) {
192 ret = p[offset] << 24;
193 ret |= p[offset + 1] << 16;
194 ret |= p[offset + 2] << 8;
195 ret |= p[offset + 3];
196 } else {
197 ret = p[offset];
198 ret |= p[offset + 1] << 8;
199 ret |= p[offset + 2] << 16;
200 ret |= p[offset + 3] << 24;
201 }
202
203 break;
204 }
205 break;
206 case 0x90:
207
208 switch (boff) {
209 case 0x00:
210 case 0x01:
211 ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
212 break;
213 case 0x02:
214 ret = 0x00;
215 break;
216 case 0x0E:
217 case 0x0F:
218 ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
219 if (ret == (uint8_t)-1) {
220 goto flash_read;
221 }
222 break;
223 default:
224 goto flash_read;
225 }
226 DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret);
227 break;
228 case 0xA0:
229 case 0x10:
230 case 0x30:
231
232 ret = pfl->status;
233 DPRINTF("%s: status %x\n", __func__, ret);
234
235 pfl->status ^= 0x40;
236 break;
237 case 0x98:
238
239 if (boff > pfl->cfi_len)
240 ret = 0;
241 else
242 ret = pfl->cfi_table[boff];
243 break;
244 }
245
246 return ret;
247}
248
249
250static void pflash_update(pflash_t *pfl, int offset,
251 int size)
252{
253 int offset_end;
254 if (pfl->blk) {
255 offset_end = offset + size;
256
257 offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
258 offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
259 blk_pwrite(pfl->blk, offset, pfl->storage + offset,
260 offset_end - offset);
261 }
262}
263
264static void pflash_write (pflash_t *pfl, hwaddr offset,
265 uint32_t value, int width, int be)
266{
267 hwaddr boff;
268 uint8_t *p;
269 uint8_t cmd;
270
271 cmd = value;
272 if (pfl->cmd != 0xA0 && cmd == 0xF0) {
273#if 0
274 DPRINTF("%s: flash reset asked (%02x %02x)\n",
275 __func__, pfl->cmd, cmd);
276#endif
277 goto reset_flash;
278 }
279 DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__,
280 offset, value, width, pfl->wcycle);
281 offset &= pfl->chip_len - 1;
282
283 DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,
284 offset, value, width);
285 boff = offset & (pfl->sector_len - 1);
286 if (pfl->width == 2)
287 boff = boff >> 1;
288 else if (pfl->width == 4)
289 boff = boff >> 2;
290 switch (pfl->wcycle) {
291 case 0:
292
293 if (pfl->rom_mode)
294 pflash_register_memory(pfl, 0);
295 pfl->read_counter = 0;
296
297 check_unlock0:
298 if (boff == 0x55 && cmd == 0x98) {
299 enter_CFI_mode:
300
301 pfl->wcycle = 7;
302 pfl->cmd = 0x98;
303 return;
304 }
305 if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
306 DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
307 __func__, boff, cmd, pfl->unlock_addr0);
308 goto reset_flash;
309 }
310 DPRINTF("%s: unlock sequence started\n", __func__);
311 break;
312 case 1:
313
314 check_unlock1:
315 if (boff != pfl->unlock_addr1 || cmd != 0x55) {
316 DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
317 boff, cmd);
318 goto reset_flash;
319 }
320 DPRINTF("%s: unlock sequence done\n", __func__);
321 break;
322 case 2:
323
324 if (!pfl->bypass && boff != pfl->unlock_addr0) {
325 DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
326 boff, cmd);
327 goto reset_flash;
328 }
329 switch (cmd) {
330 case 0x20:
331 pfl->bypass = 1;
332 goto do_bypass;
333 case 0x80:
334 case 0x90:
335 case 0xA0:
336 pfl->cmd = cmd;
337 DPRINTF("%s: starting command %02x\n", __func__, cmd);
338 break;
339 default:
340 DPRINTF("%s: unknown command %02x\n", __func__, cmd);
341 goto reset_flash;
342 }
343 break;
344 case 3:
345 switch (pfl->cmd) {
346 case 0x80:
347
348 goto check_unlock0;
349 case 0xA0:
350 DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n",
351 __func__, offset, value, width);
352 p = pfl->storage;
353 if (!pfl->ro) {
354 switch (width) {
355 case 1:
356 p[offset] &= value;
357 pflash_update(pfl, offset, 1);
358 break;
359 case 2:
360 if (be) {
361 p[offset] &= value >> 8;
362 p[offset + 1] &= value;
363 } else {
364 p[offset] &= value;
365 p[offset + 1] &= value >> 8;
366 }
367 pflash_update(pfl, offset, 2);
368 break;
369 case 4:
370 if (be) {
371 p[offset] &= value >> 24;
372 p[offset + 1] &= value >> 16;
373 p[offset + 2] &= value >> 8;
374 p[offset + 3] &= value;
375 } else {
376 p[offset] &= value;
377 p[offset + 1] &= value >> 8;
378 p[offset + 2] &= value >> 16;
379 p[offset + 3] &= value >> 24;
380 }
381 pflash_update(pfl, offset, 4);
382 break;
383 }
384 }
385 pfl->status = 0x00 | ~(value & 0x80);
386
387 if (pfl->bypass)
388 goto do_bypass;
389 goto reset_flash;
390 case 0x90:
391 if (pfl->bypass && cmd == 0x00) {
392
393 goto reset_flash;
394 }
395
396 if (boff == 0x55 && cmd == 0x98)
397 goto enter_CFI_mode;
398
399 default:
400 DPRINTF("%s: invalid write for command %02x\n",
401 __func__, pfl->cmd);
402 goto reset_flash;
403 }
404 case 4:
405 switch (pfl->cmd) {
406 case 0xA0:
407
408
409 return;
410 case 0x80:
411 goto check_unlock1;
412 default:
413
414 DPRINTF("%s: invalid command state %02x (wc 4)\n",
415 __func__, pfl->cmd);
416 goto reset_flash;
417 }
418 break;
419 case 5:
420 switch (cmd) {
421 case 0x10:
422 if (boff != pfl->unlock_addr0) {
423 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
424 __func__, offset);
425 goto reset_flash;
426 }
427
428 DPRINTF("%s: start chip erase\n", __func__);
429 if (!pfl->ro) {
430 memset(pfl->storage, 0xFF, pfl->chip_len);
431 pflash_update(pfl, 0, pfl->chip_len);
432 }
433 pfl->status = 0x00;
434
435 timer_mod(pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
436 (NANOSECONDS_PER_SECOND * 5));
437 break;
438 case 0x30:
439
440 p = pfl->storage;
441 offset &= ~(pfl->sector_len - 1);
442 DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
443 offset);
444 if (!pfl->ro) {
445 memset(p + offset, 0xFF, pfl->sector_len);
446 pflash_update(pfl, offset, pfl->sector_len);
447 }
448 pfl->status = 0x00;
449
450 timer_mod(pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
451 (NANOSECONDS_PER_SECOND / 2));
452 break;
453 default:
454 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
455 goto reset_flash;
456 }
457 pfl->cmd = cmd;
458 break;
459 case 6:
460 switch (pfl->cmd) {
461 case 0x10:
462
463 return;
464 case 0x30:
465
466 return;
467 default:
468
469 DPRINTF("%s: invalid command state %02x (wc 6)\n",
470 __func__, pfl->cmd);
471 goto reset_flash;
472 }
473 break;
474 case 7:
475 DPRINTF("%s: invalid write in CFI query mode\n", __func__);
476 goto reset_flash;
477 default:
478
479 DPRINTF("%s: invalid write state (wc 7)\n", __func__);
480 goto reset_flash;
481 }
482 pfl->wcycle++;
483
484 return;
485
486
487 reset_flash:
488 pfl->bypass = 0;
489 pfl->wcycle = 0;
490 pfl->cmd = 0;
491 return;
492
493 do_bypass:
494 pfl->wcycle = 2;
495 pfl->cmd = 0;
496}
497
498
499static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
500{
501 return pflash_read(opaque, addr, 1, 1);
502}
503
504static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
505{
506 return pflash_read(opaque, addr, 1, 0);
507}
508
509static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
510{
511 pflash_t *pfl = opaque;
512
513 return pflash_read(pfl, addr, 2, 1);
514}
515
516static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
517{
518 pflash_t *pfl = opaque;
519
520 return pflash_read(pfl, addr, 2, 0);
521}
522
523static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
524{
525 pflash_t *pfl = opaque;
526
527 return pflash_read(pfl, addr, 4, 1);
528}
529
530static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
531{
532 pflash_t *pfl = opaque;
533
534 return pflash_read(pfl, addr, 4, 0);
535}
536
537static void pflash_writeb_be(void *opaque, hwaddr addr,
538 uint32_t value)
539{
540 pflash_write(opaque, addr, value, 1, 1);
541}
542
543static void pflash_writeb_le(void *opaque, hwaddr addr,
544 uint32_t value)
545{
546 pflash_write(opaque, addr, value, 1, 0);
547}
548
549static void pflash_writew_be(void *opaque, hwaddr addr,
550 uint32_t value)
551{
552 pflash_t *pfl = opaque;
553
554 pflash_write(pfl, addr, value, 2, 1);
555}
556
557static void pflash_writew_le(void *opaque, hwaddr addr,
558 uint32_t value)
559{
560 pflash_t *pfl = opaque;
561
562 pflash_write(pfl, addr, value, 2, 0);
563}
564
565static void pflash_writel_be(void *opaque, hwaddr addr,
566 uint32_t value)
567{
568 pflash_t *pfl = opaque;
569
570 pflash_write(pfl, addr, value, 4, 1);
571}
572
573static void pflash_writel_le(void *opaque, hwaddr addr,
574 uint32_t value)
575{
576 pflash_t *pfl = opaque;
577
578 pflash_write(pfl, addr, value, 4, 0);
579}
580
581static const MemoryRegionOps pflash_cfi02_ops_be = {
582 .old_mmio = {
583 .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
584 .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
585 },
586 .endianness = DEVICE_NATIVE_ENDIAN,
587};
588
589static const MemoryRegionOps pflash_cfi02_ops_le = {
590 .old_mmio = {
591 .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
592 .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
593 },
594 .endianness = DEVICE_NATIVE_ENDIAN,
595};
596
597static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
598{
599 pflash_t *pfl = CFI_PFLASH02(dev);
600 uint32_t chip_len;
601 int ret;
602 Error *local_err = NULL;
603
604 chip_len = pfl->sector_len * pfl->nb_blocs;
605
606#if 0
607 if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
608 total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
609 return NULL;
610#endif
611
612 memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ?
613 &pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
614 pfl, pfl->name, chip_len, &local_err);
615 if (local_err) {
616 error_propagate(errp, local_err);
617 return;
618 }
619
620 vmstate_register_ram(&pfl->orig_mem, DEVICE(pfl));
621 pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
622 pfl->chip_len = chip_len;
623 if (pfl->blk) {
624
625 ret = blk_pread(pfl->blk, 0, pfl->storage, chip_len);
626 if (ret < 0) {
627 vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
628 error_setg(errp, "failed to read the initial flash content");
629 return;
630 }
631 }
632
633 pflash_setup_mappings(pfl);
634 pfl->rom_mode = 1;
635 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
636
637 if (pfl->blk) {
638 pfl->ro = blk_is_read_only(pfl->blk);
639 } else {
640 pfl->ro = 0;
641 }
642
643 pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
644 pfl->wcycle = 0;
645 pfl->cmd = 0;
646 pfl->status = 0;
647
648 pfl->cfi_len = 0x52;
649
650 pfl->cfi_table[0x10] = 'Q';
651 pfl->cfi_table[0x11] = 'R';
652 pfl->cfi_table[0x12] = 'Y';
653
654 pfl->cfi_table[0x13] = 0x02;
655 pfl->cfi_table[0x14] = 0x00;
656
657 pfl->cfi_table[0x15] = 0x31;
658 pfl->cfi_table[0x16] = 0x00;
659
660 pfl->cfi_table[0x17] = 0x00;
661 pfl->cfi_table[0x18] = 0x00;
662
663 pfl->cfi_table[0x19] = 0x00;
664 pfl->cfi_table[0x1A] = 0x00;
665
666 pfl->cfi_table[0x1B] = 0x27;
667
668 pfl->cfi_table[0x1C] = 0x36;
669
670 pfl->cfi_table[0x1D] = 0x00;
671
672 pfl->cfi_table[0x1E] = 0x00;
673
674 pfl->cfi_table[0x1F] = 0x07;
675
676 pfl->cfi_table[0x20] = 0x00;
677
678 pfl->cfi_table[0x21] = 0x09;
679
680 pfl->cfi_table[0x22] = 0x0C;
681
682 pfl->cfi_table[0x23] = 0x01;
683
684 pfl->cfi_table[0x24] = 0x00;
685
686 pfl->cfi_table[0x25] = 0x0A;
687
688 pfl->cfi_table[0x26] = 0x0D;
689
690 pfl->cfi_table[0x27] = ctz32(chip_len);
691
692 pfl->cfi_table[0x28] = 0x02;
693 pfl->cfi_table[0x29] = 0x00;
694
695
696
697 pfl->cfi_table[0x2A] = 0x00;
698 pfl->cfi_table[0x2B] = 0x00;
699
700 pfl->cfi_table[0x2C] = 0x01;
701
702 pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
703 pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
704 pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
705 pfl->cfi_table[0x30] = pfl->sector_len >> 16;
706
707
708 pfl->cfi_table[0x31] = 'P';
709 pfl->cfi_table[0x32] = 'R';
710 pfl->cfi_table[0x33] = 'I';
711
712 pfl->cfi_table[0x34] = '1';
713 pfl->cfi_table[0x35] = '0';
714
715 pfl->cfi_table[0x36] = 0x00;
716 pfl->cfi_table[0x37] = 0x00;
717 pfl->cfi_table[0x38] = 0x00;
718 pfl->cfi_table[0x39] = 0x00;
719
720 pfl->cfi_table[0x3a] = 0x00;
721
722 pfl->cfi_table[0x3b] = 0x00;
723 pfl->cfi_table[0x3c] = 0x00;
724}
725
726static Property pflash_cfi02_properties[] = {
727 DEFINE_PROP_DRIVE("drive", struct pflash_t, blk),
728 DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
729 DEFINE_PROP_UINT32("sector-length", struct pflash_t, sector_len, 0),
730 DEFINE_PROP_UINT8("width", struct pflash_t, width, 0),
731 DEFINE_PROP_UINT8("mappings", struct pflash_t, mappings, 0),
732 DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0),
733 DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
734 DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
735 DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),
736 DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),
737 DEFINE_PROP_UINT16("unlock-addr0", struct pflash_t, unlock_addr0, 0),
738 DEFINE_PROP_UINT16("unlock-addr1", struct pflash_t, unlock_addr1, 0),
739 DEFINE_PROP_STRING("name", struct pflash_t, name),
740 DEFINE_PROP_END_OF_LIST(),
741};
742
743static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
744{
745 DeviceClass *dc = DEVICE_CLASS(klass);
746
747 dc->realize = pflash_cfi02_realize;
748 dc->props = pflash_cfi02_properties;
749 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
750}
751
752static const TypeInfo pflash_cfi02_info = {
753 .name = TYPE_CFI_PFLASH02,
754 .parent = TYPE_SYS_BUS_DEVICE,
755 .instance_size = sizeof(struct pflash_t),
756 .class_init = pflash_cfi02_class_init,
757};
758
759static void pflash_cfi02_register_types(void)
760{
761 type_register_static(&pflash_cfi02_info);
762}
763
764type_init(pflash_cfi02_register_types)
765
766pflash_t *pflash_cfi02_register(hwaddr base,
767 DeviceState *qdev, const char *name,
768 hwaddr size,
769 BlockBackend *blk, uint32_t sector_len,
770 int nb_blocs, int nb_mappings, int width,
771 uint16_t id0, uint16_t id1,
772 uint16_t id2, uint16_t id3,
773 uint16_t unlock_addr0, uint16_t unlock_addr1,
774 int be)
775{
776 DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH02);
777
778 if (blk) {
779 qdev_prop_set_drive(dev, "drive", blk, &error_abort);
780 }
781 qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
782 qdev_prop_set_uint32(dev, "sector-length", sector_len);
783 qdev_prop_set_uint8(dev, "width", width);
784 qdev_prop_set_uint8(dev, "mappings", nb_mappings);
785 qdev_prop_set_uint8(dev, "big-endian", !!be);
786 qdev_prop_set_uint16(dev, "id0", id0);
787 qdev_prop_set_uint16(dev, "id1", id1);
788 qdev_prop_set_uint16(dev, "id2", id2);
789 qdev_prop_set_uint16(dev, "id3", id3);
790 qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
791 qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
792 qdev_prop_set_string(dev, "name", name);
793 qdev_init_nofail(dev);
794
795 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
796 return CFI_PFLASH02(dev);
797}
798