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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "sysemu/char.h"
28
29#include "trace.h"
30
31#define UART_REG_SIZE 20
32
33
34#define UART_DATA_READY (1 << 0)
35#define UART_TRANSMIT_SHIFT_EMPTY (1 << 1)
36#define UART_TRANSMIT_FIFO_EMPTY (1 << 2)
37#define UART_BREAK_RECEIVED (1 << 3)
38#define UART_OVERRUN (1 << 4)
39#define UART_PARITY_ERROR (1 << 5)
40#define UART_FRAMING_ERROR (1 << 6)
41#define UART_TRANSMIT_FIFO_HALF (1 << 7)
42#define UART_RECEIVE_FIFO_HALF (1 << 8)
43#define UART_TRANSMIT_FIFO_FULL (1 << 9)
44#define UART_RECEIVE_FIFO_FULL (1 << 10)
45
46
47#define UART_RECEIVE_ENABLE (1 << 0)
48#define UART_TRANSMIT_ENABLE (1 << 1)
49#define UART_RECEIVE_INTERRUPT (1 << 2)
50#define UART_TRANSMIT_INTERRUPT (1 << 3)
51#define UART_PARITY_SELECT (1 << 4)
52#define UART_PARITY_ENABLE (1 << 5)
53#define UART_FLOW_CONTROL (1 << 6)
54#define UART_LOOPBACK (1 << 7)
55#define UART_EXTERNAL_CLOCK (1 << 8)
56#define UART_RECEIVE_FIFO_INTERRUPT (1 << 9)
57#define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
58#define UART_FIFO_DEBUG_MODE (1 << 11)
59#define UART_OUTPUT_ENABLE (1 << 12)
60#define UART_FIFO_AVAILABLE (1 << 31)
61
62
63#define DATA_OFFSET 0x00
64#define STATUS_OFFSET 0x04
65#define CONTROL_OFFSET 0x08
66#define SCALER_OFFSET 0x0C
67#define FIFO_DEBUG_OFFSET 0x10
68
69#define FIFO_LENGTH 1024
70
71#define TYPE_GRLIB_APB_UART "grlib,apbuart"
72#define GRLIB_APB_UART(obj) \
73 OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART)
74
75typedef struct UART {
76 SysBusDevice parent_obj;
77
78 MemoryRegion iomem;
79 qemu_irq irq;
80
81 CharDriverState *chr;
82
83
84 uint32_t status;
85 uint32_t control;
86
87
88 char buffer[FIFO_LENGTH];
89 int len;
90 int current;
91} UART;
92
93static int uart_data_to_read(UART *uart)
94{
95 return uart->current < uart->len;
96}
97
98static char uart_pop(UART *uart)
99{
100 char ret;
101
102 if (uart->len == 0) {
103 uart->status &= ~UART_DATA_READY;
104 return 0;
105 }
106
107 ret = uart->buffer[uart->current++];
108
109 if (uart->current >= uart->len) {
110
111 uart->len = 0;
112 uart->current = 0;
113 }
114
115 if (!uart_data_to_read(uart)) {
116 uart->status &= ~UART_DATA_READY;
117 }
118
119 return ret;
120}
121
122static void uart_add_to_fifo(UART *uart,
123 const uint8_t *buffer,
124 int length)
125{
126 if (uart->len + length > FIFO_LENGTH) {
127 abort();
128 }
129 memcpy(uart->buffer + uart->len, buffer, length);
130 uart->len += length;
131}
132
133static int grlib_apbuart_can_receive(void *opaque)
134{
135 UART *uart = opaque;
136
137 return FIFO_LENGTH - uart->len;
138}
139
140static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size)
141{
142 UART *uart = opaque;
143
144 if (uart->control & UART_RECEIVE_ENABLE) {
145 uart_add_to_fifo(uart, buf, size);
146
147 uart->status |= UART_DATA_READY;
148
149 if (uart->control & UART_RECEIVE_INTERRUPT) {
150 qemu_irq_pulse(uart->irq);
151 }
152 }
153}
154
155static void grlib_apbuart_event(void *opaque, int event)
156{
157 trace_grlib_apbuart_event(event);
158}
159
160
161static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
162 unsigned size)
163{
164 UART *uart = opaque;
165
166 addr &= 0xff;
167
168
169 switch (addr) {
170 case DATA_OFFSET:
171 case DATA_OFFSET + 3:
172 return uart_pop(uart);
173
174 case STATUS_OFFSET:
175
176 return uart->status;
177
178 case CONTROL_OFFSET:
179 return uart->control;
180
181 case SCALER_OFFSET:
182
183 return 0;
184
185 default:
186 trace_grlib_apbuart_readl_unknown(addr);
187 return 0;
188 }
189}
190
191static void grlib_apbuart_write(void *opaque, hwaddr addr,
192 uint64_t value, unsigned size)
193{
194 UART *uart = opaque;
195 unsigned char c = 0;
196
197 addr &= 0xff;
198
199
200 switch (addr) {
201 case DATA_OFFSET:
202 case DATA_OFFSET + 3:
203
204 if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) {
205 c = value & 0xFF;
206 qemu_chr_fe_write(uart->chr, &c, 1);
207
208 if (uart->control & UART_TRANSMIT_INTERRUPT) {
209 qemu_irq_pulse(uart->irq);
210 }
211 }
212 return;
213
214 case STATUS_OFFSET:
215
216 return;
217
218 case CONTROL_OFFSET:
219 uart->control = value;
220 return;
221
222 case SCALER_OFFSET:
223
224 return;
225
226 default:
227 break;
228 }
229
230 trace_grlib_apbuart_writel_unknown(addr, value);
231}
232
233static const MemoryRegionOps grlib_apbuart_ops = {
234 .write = grlib_apbuart_write,
235 .read = grlib_apbuart_read,
236 .endianness = DEVICE_NATIVE_ENDIAN,
237};
238
239static int grlib_apbuart_init(SysBusDevice *dev)
240{
241 UART *uart = GRLIB_APB_UART(dev);
242
243 qemu_chr_add_handlers(uart->chr,
244 grlib_apbuart_can_receive,
245 grlib_apbuart_receive,
246 grlib_apbuart_event,
247 uart);
248
249 sysbus_init_irq(dev, &uart->irq);
250
251 memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
252 "uart", UART_REG_SIZE);
253
254 sysbus_init_mmio(dev, &uart->iomem);
255
256 return 0;
257}
258
259static void grlib_apbuart_reset(DeviceState *d)
260{
261 UART *uart = GRLIB_APB_UART(d);
262
263
264 uart->status = UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY;
265
266 uart->control = 0;
267
268 uart->len = 0;
269 uart->current = 0;
270}
271
272static Property grlib_apbuart_properties[] = {
273 DEFINE_PROP_CHR("chrdev", UART, chr),
274 DEFINE_PROP_END_OF_LIST(),
275};
276
277static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
278{
279 DeviceClass *dc = DEVICE_CLASS(klass);
280 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
281
282 k->init = grlib_apbuart_init;
283 dc->reset = grlib_apbuart_reset;
284 dc->props = grlib_apbuart_properties;
285}
286
287static const TypeInfo grlib_apbuart_info = {
288 .name = TYPE_GRLIB_APB_UART,
289 .parent = TYPE_SYS_BUS_DEVICE,
290 .instance_size = sizeof(UART),
291 .class_init = grlib_apbuart_class_init,
292};
293
294static void grlib_apbuart_register_types(void)
295{
296 type_register_static(&grlib_apbuart_info);
297}
298
299type_init(grlib_apbuart_register_types)
300