LXR qemu/hw/cpu/a15mpcore.c

   1/*
   2 * Cortex-A15MPCore internal peripheral emulation.
   3 *
   4 * Copyright (c) 2012 Linaro Limited.
   5 * Written by Peter Maydell.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "hw/cpu/a15mpcore.h"
  24#include "sysemu/kvm.h"
  25#include "kvm_arm.h"
  26
  27static void a15mp_priv_set_irq(void *opaque, int irq, int level)
  28{
  29    A15MPPrivState *s = (A15MPPrivState *)opaque;
  30
  31    qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  32}
  33
  34static void a15mp_priv_initfn(Object *obj)
  35{
  36    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  37    A15MPPrivState *s = A15MPCORE_PRIV(obj);
  38    DeviceState *gicdev;
  39
  40    memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
  41    sysbus_init_mmio(sbd, &s->container);
  42
  43    object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
  44    gicdev = DEVICE(&s->gic);
  45    qdev_set_parent_bus(gicdev, sysbus_get_default());
  46    qdev_prop_set_uint32(gicdev, "revision", 2);
  47}
  48
  49static void a15mp_priv_realize(DeviceState *dev, Error **errp)
  50{
  51    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  52    A15MPPrivState *s = A15MPCORE_PRIV(dev);
  53    DeviceState *gicdev;
  54    SysBusDevice *busdev;
  55    int i;
  56    Error *err = NULL;
  57    bool has_el3;
  58    Object *cpuobj;
  59
  60    gicdev = DEVICE(&s->gic);
  61    qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  62    qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  63
  64    if (!kvm_irqchip_in_kernel()) {
  65        /* Make the GIC's TZ support match the CPUs. We assume that
  66         * either all the CPUs have TZ, or none do.
  67         */
  68        cpuobj = OBJECT(qemu_get_cpu(0));
  69        has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
  70            object_property_get_bool(cpuobj, "has_el3", &error_abort);
  71        qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
  72    }
  73
  74    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  75    if (err != NULL) {
  76        error_propagate(errp, err);
  77        return;
  78    }
  79    busdev = SYS_BUS_DEVICE(&s->gic);
  80
  81    /* Pass through outbound IRQ lines from the GIC */
  82    sysbus_pass_irq(sbd, busdev);
  83
  84    /* Pass through inbound GPIO lines to the GIC */
  85    qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
  86
  87    /* Wire the outputs from each CPU's generic timer to the
  88     * appropriate GIC PPI inputs
  89     */
  90    for (i = 0; i < s->num_cpu; i++) {
  91        DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
  92        int ppibase = s->num_irq - 32 + i * 32;
  93        int irq;
  94        /* Mapping from the output timer irq lines from the CPU to the
  95         * GIC PPI inputs used on the A15:
  96         */
  97        const int timer_irq[] = {
  98            [GTIMER_PHYS] = 30,
  99            [GTIMER_VIRT] = 27,
 100            [GTIMER_HYP]  = 26,
 101            [GTIMER_SEC]  = 29,
 102        };
 103        for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 104            qdev_connect_gpio_out(cpudev, irq,
 105                                  qdev_get_gpio_in(gicdev,
 106                                                   ppibase + timer_irq[irq]));
 107        }
 108    }
 109
 110    /* Memory map (addresses are offsets from PERIPHBASE):
 111     *  0x0000-0x0fff -- reserved
 112     *  0x1000-0x1fff -- GIC Distributor
 113     *  0x2000-0x3fff -- GIC CPU interface
 114     *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
 115     *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
 116     *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
 117     */
 118    memory_region_add_subregion(&s->container, 0x1000,
 119                                sysbus_mmio_get_region(busdev, 0));
 120    memory_region_add_subregion(&s->container, 0x2000,
 121                                sysbus_mmio_get_region(busdev, 1));
 122}
 123
 124static Property a15mp_priv_properties[] = {
 125    DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
 126    /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
 127     * IRQ lines (with another 32 internal). We default to 128+32, which
 128     * is the number provided by the Cortex-A15MP test chip in the
 129     * Versatile Express A15 development board.
 130     * Other boards may differ and should set this property appropriately.
 131     */
 132    DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
 133    DEFINE_PROP_END_OF_LIST(),
 134};
 135
 136static void a15mp_priv_class_init(ObjectClass *klass, void *data)
 137{
 138    DeviceClass *dc = DEVICE_CLASS(klass);
 139
 140    dc->realize = a15mp_priv_realize;
 141    dc->props = a15mp_priv_properties;
 142    /* We currently have no savable state */
 143}
 144
 145static const TypeInfo a15mp_priv_info = {
 146    .name  = TYPE_A15MPCORE_PRIV,
 147    .parent = TYPE_SYS_BUS_DEVICE,
 148    .instance_size  = sizeof(A15MPPrivState),
 149    .instance_init = a15mp_priv_initfn,
 150    .class_init = a15mp_priv_class_init,
 151};
 152
 153static void a15mp_register_types(void)
 154{
 155    type_register_static(&a15mp_priv_info);
 156}
 157
 158type_init(a15mp_register_types)
 159