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25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu/log.h"
28#include "hw/display/xlnx_dp.h"
29
30#ifndef DEBUG_DP
31#define DEBUG_DP 0
32#endif
33
34#define DPRINTF(fmt, ...) do { \
35 if (DEBUG_DP) { \
36 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \
37 } \
38} while (0);
39
40
41
42
43#define DP_LINK_BW_SET (0x0000 >> 2)
44#define DP_LANE_COUNT_SET (0x0004 >> 2)
45#define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
46#define DP_TRAINING_PATTERN_SET (0x000C >> 2)
47#define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
48#define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
49#define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
50#define DP_SOFTWARE_RESET (0x001C >> 2)
51#define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
52#define DP_MAIN_STREAM_ENABLE (0x0084 >> 2)
53#define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2)
54#define DP_VERSION_REGISTER (0x00F8 >> 2)
55#define DP_CORE_ID (0x00FC >> 2)
56
57#define DP_AUX_COMMAND_REGISTER (0x0100 >> 2)
58#define AUX_ADDR_ONLY_MASK (0x1000)
59#define AUX_COMMAND_MASK (0x0F00)
60#define AUX_COMMAND_SHIFT (8)
61#define AUX_COMMAND_NBYTES (0x000F)
62
63#define DP_AUX_WRITE_FIFO (0x0104 >> 2)
64#define DP_AUX_ADDRESS (0x0108 >> 2)
65#define DP_AUX_CLOCK_DIVIDER (0x010C >> 2)
66#define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2)
67#define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2)
68#define DP_AUX_REPLY_DATA (0x0134 >> 2)
69#define DP_AUX_REPLY_CODE (0x0138 >> 2)
70#define DP_AUX_REPLY_COUNT (0x013C >> 2)
71#define DP_REPLY_DATA_COUNT (0x0148 >> 2)
72#define DP_REPLY_STATUS (0x014C >> 2)
73#define DP_HPD_DURATION (0x0150 >> 2)
74#define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2)
75#define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2)
76#define DP_MAIN_STREAM_POLARITY (0x0188 >> 2)
77#define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2)
78#define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2)
79#define DP_MAIN_STREAM_HRES (0x0194 >> 2)
80#define DP_MAIN_STREAM_VRES (0x0198 >> 2)
81#define DP_MAIN_STREAM_HSTART (0x019C >> 2)
82#define DP_MAIN_STREAM_VSTART (0x01A0 >> 2)
83#define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2)
84#define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2)
85#define DP_MAIN_STREAM_M_VID (0x01AC >> 2)
86#define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2)
87#define DP_MAIN_STREAM_N_VID (0x01B4 >> 2)
88#define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2)
89#define DP_MIN_BYTES_PER_TU (0x01C4 >> 2)
90#define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2)
91#define DP_INIT_WAIT (0x01CC >> 2)
92#define DP_PHY_RESET (0x0200 >> 2)
93#define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2)
94#define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2)
95#define DP_TRANSMIT_PRBS7 (0x0230 >> 2)
96#define DP_PHY_CLOCK_SELECT (0x0234 >> 2)
97#define DP_TX_PHY_POWER_DOWN (0x0238 >> 2)
98#define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2)
99#define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2)
100#define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2)
101#define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2)
102#define DP_PHY_STATUS (0x0280 >> 2)
103
104#define DP_TX_AUDIO_CONTROL (0x0300 >> 2)
105#define DP_TX_AUD_CTRL (1)
106
107#define DP_TX_AUDIO_CHANNELS (0x0304 >> 2)
108#define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2)
109#define DP_TX_M_AUD (0x0328 >> 2)
110#define DP_TX_N_AUD (0x032C >> 2)
111#define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2)
112#define DP_INT_STATUS (0x03A0 >> 2)
113#define DP_INT_MASK (0x03A4 >> 2)
114#define DP_INT_EN (0x03A8 >> 2)
115#define DP_INT_DS (0x03AC >> 2)
116
117
118
119
120#define V_BLEND_OFFSET (0xA000)
121#define V_BLEND_BG_CLR_0 (0x0000 >> 2)
122#define V_BLEND_BG_CLR_1 (0x0004 >> 2)
123#define V_BLEND_BG_CLR_2 (0x0008 >> 2)
124#define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2)
125#define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2)
126#define V_BLEND_LAYER0_CONTROL (0x0018 >> 2)
127#define V_BLEND_LAYER1_CONTROL (0x001C >> 2)
128
129#define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2)
130#define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2)
131
132#define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2)
133#define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2)
134#define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2)
135#define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2)
136#define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2)
137#define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2)
138
139#define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2)
140
141#define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2)
142#define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2)
143#define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2)
144#define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2)
145#define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2)
146#define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2)
147#define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2)
148
149
150
151
152#define AV_BUF_MANAGER_OFFSET (0xB000)
153#define AV_BUF_FORMAT (0x0000 >> 2)
154#define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2)
155#define AV_CHBUF0 (0x0010 >> 2)
156#define AV_CHBUF1 (0x0014 >> 2)
157#define AV_CHBUF2 (0x0018 >> 2)
158#define AV_CHBUF3 (0x001C >> 2)
159#define AV_CHBUF4 (0x0020 >> 2)
160#define AV_CHBUF5 (0x0024 >> 2)
161#define AV_BUF_STC_CONTROL (0x002C >> 2)
162#define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2)
163#define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2)
164#define AV_BUF_STC_ADJ (0x0038 >> 2)
165#define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2)
166#define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2)
167#define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2)
168#define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2)
169#define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2)
170#define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2)
171#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2)
172#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2)
173#define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2)
174#define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2)
175#define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2)
176#define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2)
177#define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2)
178#define AV_BUF_DITHER_CONFIG (0x007C >> 2)
179#define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2)
180#define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2)
181#define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2)
182#define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2)
183#define AV_BUF_SRST_REG (0x0124 >> 2)
184#define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2)
185#define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2)
186
187#define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2)
188
189#define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2)
190
191#define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2)
192
193#define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2)
194
195#define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2)
196
197#define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2)
198
199#define AUDIO_MIXER_REGISTER_OFFSET (0xC000)
200#define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2)
201#define AUDIO_MIXER_META_DATA (0x0004 >> 2)
202#define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2)
203#define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2)
204#define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2)
205
206#define DP_AUDIO_DMA_CHANNEL(n) (4 + n)
207#define DP_GRAPHIC_DMA_CHANNEL (3)
208#define DP_VIDEO_DMA_CHANNEL (0)
209
210enum DPGraphicFmt {
211 DP_GRAPHIC_RGBA8888 = 0 << 8,
212 DP_GRAPHIC_ABGR8888 = 1 << 8,
213 DP_GRAPHIC_RGB888 = 2 << 8,
214 DP_GRAPHIC_BGR888 = 3 << 8,
215 DP_GRAPHIC_RGBA5551 = 4 << 8,
216 DP_GRAPHIC_RGBA4444 = 5 << 8,
217 DP_GRAPHIC_RGB565 = 6 << 8,
218 DP_GRAPHIC_8BPP = 7 << 8,
219 DP_GRAPHIC_4BPP = 8 << 8,
220 DP_GRAPHIC_2BPP = 9 << 8,
221 DP_GRAPHIC_1BPP = 10 << 8,
222 DP_GRAPHIC_MASK = 0xF << 8
223};
224
225enum DPVideoFmt {
226 DP_NL_VID_CB_Y0_CR_Y1 = 0,
227 DP_NL_VID_CR_Y0_CB_Y1 = 1,
228 DP_NL_VID_Y0_CR_Y1_CB = 2,
229 DP_NL_VID_Y0_CB_Y1_CR = 3,
230 DP_NL_VID_YV16 = 4,
231 DP_NL_VID_YV24 = 5,
232 DP_NL_VID_YV16CL = 6,
233 DP_NL_VID_MONO = 7,
234 DP_NL_VID_YV16CL2 = 8,
235 DP_NL_VID_YUV444 = 9,
236 DP_NL_VID_RGB888 = 10,
237 DP_NL_VID_RGBA8880 = 11,
238 DP_NL_VID_RGB888_10BPC = 12,
239 DP_NL_VID_YUV444_10BPC = 13,
240 DP_NL_VID_YV16CL2_10BPC = 14,
241 DP_NL_VID_YV16CL_10BPC = 15,
242 DP_NL_VID_YV16_10BPC = 16,
243 DP_NL_VID_YV24_10BPC = 17,
244 DP_NL_VID_Y_ONLY_10BPC = 18,
245 DP_NL_VID_YV16_420 = 19,
246 DP_NL_VID_YV16CL_420 = 20,
247 DP_NL_VID_YV16CL2_420 = 21,
248 DP_NL_VID_YV16_420_10BPC = 22,
249 DP_NL_VID_YV16CL_420_10BPC = 23,
250 DP_NL_VID_YV16CL2_420_10BPC = 24,
251 DP_NL_VID_FMT_MASK = 0x1F
252};
253
254typedef enum DPGraphicFmt DPGraphicFmt;
255typedef enum DPVideoFmt DPVideoFmt;
256
257static const VMStateDescription vmstate_dp = {
258 .name = TYPE_XLNX_DP,
259 .version_id = 1,
260 .fields = (VMStateField[]){
261 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState,
262 DP_CORE_REG_ARRAY_SIZE),
263 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState,
264 DP_AVBUF_REG_ARRAY_SIZE),
265 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState,
266 DP_VBLEND_REG_ARRAY_SIZE),
267 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState,
268 DP_AUDIO_REG_ARRAY_SIZE),
269 VMSTATE_END_OF_LIST()
270 }
271};
272
273static void xlnx_dp_update_irq(XlnxDPState *s);
274
275static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
276{
277 XlnxDPState *s = XLNX_DP(opaque);
278
279 offset = offset >> 2;
280 return s->audio_registers[offset];
281}
282
283static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
284 unsigned size)
285{
286 XlnxDPState *s = XLNX_DP(opaque);
287
288 offset = offset >> 2;
289
290 switch (offset) {
291 case AUDIO_MIXER_META_DATA:
292 s->audio_registers[offset] = value & 0x00000001;
293 break;
294 default:
295 s->audio_registers[offset] = value;
296 break;
297 }
298}
299
300static const MemoryRegionOps audio_ops = {
301 .read = xlnx_dp_audio_read,
302 .write = xlnx_dp_audio_write,
303 .endianness = DEVICE_NATIVE_ENDIAN,
304};
305
306static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s,
307 uint8_t channel)
308{
309 switch (channel) {
310 case 0:
311 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16);
312 case 1:
313 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16,
314 16);
315 default:
316 return 0;
317 }
318}
319
320static inline void xlnx_dp_audio_activate(XlnxDPState *s)
321{
322 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL]
323 & DP_TX_AUD_CTRL) != 0);
324 AUD_set_active_out(s->amixer_output_stream, activated);
325 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0),
326 &s->audio_buffer_0);
327 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1),
328 &s->audio_buffer_1);
329}
330
331static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s)
332{
333
334
335
336
337
338
339
340 int i;
341
342 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) {
343 for (i = 0; i < s->audio_data_available[0] / 2; i++) {
344 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
345 * xlnx_dp_audio_get_volume(s, 0) / 8192;
346 }
347 s->byte_left = s->audio_data_available[0];
348 } else {
349 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
350 }
351
352 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) {
353 if ((s->audio_data_available[0] == 0)
354 || (s->audio_data_available[1] == s->audio_data_available[0])) {
355 for (i = 0; i < s->audio_data_available[1] / 2; i++) {
356 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
357 * xlnx_dp_audio_get_volume(s, 1) / 8192;
358 }
359 s->byte_left = s->audio_data_available[1];
360 }
361 }
362
363 for (i = 0; i < s->byte_left / 2; i++) {
364 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767));
365 }
366
367 s->data_ptr = 0;
368}
369
370static void xlnx_dp_audio_callback(void *opaque, int avail)
371{
372
373
374
375
376 XlnxDPState *s = XLNX_DP(opaque);
377 size_t written = 0;
378
379
380 if (s->byte_left == 0) {
381 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4,
382 true);
383 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5,
384 true);
385 xlnx_dp_audio_mix_buffer(s);
386 }
387
388
389 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
390 if (s->byte_left != 0) {
391 written = AUD_write(s->amixer_output_stream,
392 &s->out_buffer[s->data_ptr], s->byte_left);
393 } else {
394
395
396
397
398 written = 0;
399 memset(s->out_buffer, 0, 1024);
400 AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
401 }
402 } else {
403 written = AUD_write(s->amixer_output_stream,
404 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
405 }
406 s->byte_left -= written;
407 s->data_ptr += written;
408}
409
410
411
412
413static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s)
414{
415 fifo8_reset(&s->rx_fifo);
416}
417
418static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
419{
420 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
421 fifo8_push_all(&s->rx_fifo, buf, len);
422}
423
424static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
425{
426 uint8_t ret;
427
428 if (fifo8_is_empty(&s->rx_fifo)) {
429 DPRINTF("rx_fifo underflow..\n");
430 abort();
431 }
432 ret = fifo8_pop(&s->rx_fifo);
433 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
434 return ret;
435}
436
437static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s)
438{
439 fifo8_reset(&s->tx_fifo);
440}
441
442static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
443{
444 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
445 fifo8_push_all(&s->tx_fifo, buf, len);
446}
447
448static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
449{
450 uint8_t ret;
451
452 if (fifo8_is_empty(&s->tx_fifo)) {
453 DPRINTF("tx_fifo underflow..\n");
454 abort();
455 }
456 ret = fifo8_pop(&s->tx_fifo);
457 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
458 return ret;
459}
460
461static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s)
462{
463 return s->core_registers[DP_AUX_ADDRESS];
464}
465
466static uint8_t xlnx_dp_aux_get_data(XlnxDPState *s)
467{
468 return xlnx_dp_aux_pop_rx_fifo(s);
469}
470
471static void xlnx_dp_aux_set_data(XlnxDPState *s, uint8_t value)
472{
473 xlnx_dp_aux_push_tx_fifo(s, &value, 1);
474}
475
476
477
478
479static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
480{
481 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
482 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
483 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
484 uint8_t buf[16];
485 int i;
486
487
488
489
490
491 if (address_only) {
492 nbytes = 0;
493 }
494
495 switch (cmd) {
496 case READ_AUX:
497 case READ_I2C:
498 case READ_I2C_MOT:
499 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
500 xlnx_dp_aux_get_address(s),
501 nbytes, buf);
502 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
503
504 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
505 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes);
506 }
507 break;
508 case WRITE_AUX:
509 case WRITE_I2C:
510 case WRITE_I2C_MOT:
511 for (i = 0; i < nbytes; i++) {
512 buf[i] = xlnx_dp_aux_pop_tx_fifo(s);
513 }
514 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
515 xlnx_dp_aux_get_address(s),
516 nbytes, buf);
517 xlnx_dp_aux_clear_tx_fifo(s);
518 break;
519 case WRITE_I2C_STATUS:
520 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
521 break;
522 default:
523 abort();
524 }
525
526 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
527}
528
529static void xlnx_dp_set_dpdma(Object *obj, const char *name, Object *val,
530 Error **errp)
531{
532 XlnxDPState *s = XLNX_DP(obj);
533 if (s->console) {
534 DisplaySurface *surface = qemu_console_surface(s->console);
535 XlnxDPDMAState *dma = XLNX_DPDMA(val);
536 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL,
537 surface_data(surface));
538 }
539}
540
541static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s)
542{
543 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
544}
545
546static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s)
547{
548
549
550
551
552 return ((xlnx_dp_global_alpha_value(s) != 0xFF) &&
553 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
554}
555
556static void xlnx_dp_recreate_surface(XlnxDPState *s)
557{
558
559
560
561
562 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
563 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
564 DisplaySurface *current_console_surface = qemu_console_surface(s->console);
565
566 if ((width != 0) && (height != 0)) {
567
568
569
570
571
572 if (s->bout_plane.surface != current_console_surface) {
573 qemu_free_displaysurface(s->bout_plane.surface);
574 }
575 if (s->v_plane.surface != current_console_surface) {
576 qemu_free_displaysurface(s->v_plane.surface);
577 }
578 if (s->g_plane.surface != current_console_surface) {
579 qemu_free_displaysurface(s->g_plane.surface);
580
581 }
582
583 s->g_plane.surface
584 = qemu_create_displaysurface_from(width, height,
585 s->g_plane.format, 0, NULL);
586 s->v_plane.surface
587 = qemu_create_displaysurface_from(width, height,
588 s->v_plane.format, 0, NULL);
589 if (xlnx_dp_global_alpha_enabled(s)) {
590 s->bout_plane.surface =
591 qemu_create_displaysurface_from(width,
592 height,
593 s->g_plane.format,
594 0, NULL);
595 dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
596 } else {
597 s->bout_plane.surface = NULL;
598 dpy_gfx_replace_surface(s->console, s->g_plane.surface);
599 }
600
601 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
602 surface_data(s->g_plane.surface));
603 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL,
604 surface_data(s->v_plane.surface));
605 }
606}
607
608
609
610
611static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
612{
613 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
614 case DP_GRAPHIC_RGBA8888:
615 s->g_plane.format = PIXMAN_r8g8b8a8;
616 break;
617 case DP_GRAPHIC_ABGR8888:
618 s->g_plane.format = PIXMAN_a8b8g8r8;
619 break;
620 case DP_GRAPHIC_RGB565:
621 s->g_plane.format = PIXMAN_r5g6b5;
622 break;
623 case DP_GRAPHIC_RGB888:
624 s->g_plane.format = PIXMAN_r8g8b8;
625 break;
626 case DP_GRAPHIC_BGR888:
627 s->g_plane.format = PIXMAN_b8g8r8;
628 break;
629 default:
630 DPRINTF("error: unsupported graphic format %u.\n",
631 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
632 abort();
633 }
634
635 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
636 case 0:
637 s->v_plane.format = PIXMAN_x8b8g8r8;
638 break;
639 case DP_NL_VID_RGBA8880:
640 s->v_plane.format = PIXMAN_x8b8g8r8;
641 break;
642 default:
643 DPRINTF("error: unsupported video format %u.\n",
644 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
645 abort();
646 }
647
648 xlnx_dp_recreate_surface(s);
649}
650
651static void xlnx_dp_update_irq(XlnxDPState *s)
652{
653 uint32_t flags;
654
655 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
656 DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
657 qemu_set_irq(s->irq, flags != 0);
658}
659
660static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size)
661{
662 XlnxDPState *s = XLNX_DP(opaque);
663 uint64_t ret = 0;
664
665 offset = offset >> 2;
666
667 switch (offset) {
668 case DP_TX_USER_FIFO_OVERFLOW:
669
670 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
671 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
672 break;
673 case DP_AUX_REPLY_DATA:
674 ret = xlnx_dp_aux_get_data(s);
675 break;
676 case DP_INTERRUPT_SIGNAL_STATE:
677
678
679
680
681
682 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
683 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
684 break;
685 case DP_AUX_WRITE_FIFO:
686 case DP_TX_AUDIO_INFO_DATA(0):
687 case DP_TX_AUDIO_INFO_DATA(1):
688 case DP_TX_AUDIO_INFO_DATA(2):
689 case DP_TX_AUDIO_INFO_DATA(3):
690 case DP_TX_AUDIO_INFO_DATA(4):
691 case DP_TX_AUDIO_INFO_DATA(5):
692 case DP_TX_AUDIO_INFO_DATA(6):
693 case DP_TX_AUDIO_INFO_DATA(7):
694 case DP_TX_AUDIO_EXT_DATA(0):
695 case DP_TX_AUDIO_EXT_DATA(1):
696 case DP_TX_AUDIO_EXT_DATA(2):
697 case DP_TX_AUDIO_EXT_DATA(3):
698 case DP_TX_AUDIO_EXT_DATA(4):
699 case DP_TX_AUDIO_EXT_DATA(5):
700 case DP_TX_AUDIO_EXT_DATA(6):
701 case DP_TX_AUDIO_EXT_DATA(7):
702 case DP_TX_AUDIO_EXT_DATA(8):
703
704 ret = 0;
705 break;
706 default:
707 assert(offset <= (0x3AC >> 2));
708 ret = s->core_registers[offset];
709 break;
710 }
711
712 DPRINTF("core read @%" PRIx64 " = 0x%8.8lX\n", offset << 2, ret);
713 return ret;
714}
715
716static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value,
717 unsigned size)
718{
719 XlnxDPState *s = XLNX_DP(opaque);
720
721 DPRINTF("core write @%" PRIx64 " = 0x%8.8lX\n", offset, value);
722
723 offset = offset >> 2;
724
725 switch (offset) {
726
727
728
729 case DP_LINK_BW_SET:
730 s->core_registers[offset] = value & 0x000000FF;
731 break;
732 case DP_LANE_COUNT_SET:
733 case DP_MAIN_STREAM_MISC0:
734 s->core_registers[offset] = value & 0x0000000F;
735 break;
736 case DP_TRAINING_PATTERN_SET:
737 case DP_LINK_QUAL_PATTERN_SET:
738 case DP_MAIN_STREAM_POLARITY:
739 case DP_PHY_VOLTAGE_DIFF_LANE_0:
740 case DP_PHY_VOLTAGE_DIFF_LANE_1:
741 s->core_registers[offset] = value & 0x00000003;
742 break;
743 case DP_ENHANCED_FRAME_EN:
744 case DP_SCRAMBLING_DISABLE:
745 case DP_DOWNSPREAD_CTRL:
746 case DP_MAIN_STREAM_ENABLE:
747 case DP_TRANSMIT_PRBS7:
748 s->core_registers[offset] = value & 0x00000001;
749 break;
750 case DP_PHY_CLOCK_SELECT:
751 s->core_registers[offset] = value & 0x00000007;
752 break;
753 case DP_SOFTWARE_RESET:
754
755
756
757
758
759
760 break;
761 case DP_TRANSMITTER_ENABLE:
762 s->core_registers[offset] = value & 0x01;
763 break;
764 case DP_FORCE_SCRAMBLER_RESET:
765
766
767
768
769
770
771 break;
772 case DP_AUX_COMMAND_REGISTER:
773 s->core_registers[offset] = value & 0x00001F0F;
774 xlnx_dp_aux_set_command(s, s->core_registers[offset]);
775 break;
776 case DP_MAIN_STREAM_HTOTAL:
777 case DP_MAIN_STREAM_VTOTAL:
778 case DP_MAIN_STREAM_HSTART:
779 case DP_MAIN_STREAM_VSTART:
780 s->core_registers[offset] = value & 0x0000FFFF;
781 break;
782 case DP_MAIN_STREAM_HRES:
783 case DP_MAIN_STREAM_VRES:
784 s->core_registers[offset] = value & 0x0000FFFF;
785 xlnx_dp_recreate_surface(s);
786 break;
787 case DP_MAIN_STREAM_HSWIDTH:
788 case DP_MAIN_STREAM_VSWIDTH:
789 s->core_registers[offset] = value & 0x00007FFF;
790 break;
791 case DP_MAIN_STREAM_MISC1:
792 s->core_registers[offset] = value & 0x00000086;
793 break;
794 case DP_MAIN_STREAM_M_VID:
795 case DP_MAIN_STREAM_N_VID:
796 s->core_registers[offset] = value & 0x00FFFFFF;
797 break;
798 case DP_MSA_TRANSFER_UNIT_SIZE:
799 case DP_MIN_BYTES_PER_TU:
800 case DP_INIT_WAIT:
801 s->core_registers[offset] = value & 0x00000007;
802 break;
803 case DP_USER_DATA_COUNT_PER_LANE:
804 s->core_registers[offset] = value & 0x0003FFFF;
805 break;
806 case DP_FRAC_BYTES_PER_TU:
807 s->core_registers[offset] = value & 0x000003FF;
808 break;
809 case DP_PHY_RESET:
810 s->core_registers[offset] = value & 0x00010003;
811
812
813
814 break;
815 case DP_TX_PHY_POWER_DOWN:
816 s->core_registers[offset] = value & 0x0000000F;
817
818
819
820 break;
821 case DP_AUX_WRITE_FIFO:
822 xlnx_dp_aux_set_data(s, value & 0x0000000F);
823 break;
824 case DP_AUX_CLOCK_DIVIDER:
825 break;
826 case DP_AUX_REPLY_COUNT:
827
828
829
830 s->core_registers[offset] = 0x00000000;
831 break;
832 case DP_AUX_ADDRESS:
833 s->core_registers[offset] = value & 0x000FFFFF;
834 break;
835 case DP_VERSION_REGISTER:
836 case DP_CORE_ID:
837 case DP_TX_USER_FIFO_OVERFLOW:
838 case DP_AUX_REPLY_DATA:
839 case DP_AUX_REPLY_CODE:
840 case DP_REPLY_DATA_COUNT:
841 case DP_REPLY_STATUS:
842 case DP_HPD_DURATION:
843
844
845
846 break;
847 case DP_TX_AUDIO_CONTROL:
848 s->core_registers[offset] = value & 0x00000001;
849 xlnx_dp_audio_activate(s);
850 break;
851 case DP_TX_AUDIO_CHANNELS:
852 s->core_registers[offset] = value & 0x00000007;
853 xlnx_dp_audio_activate(s);
854 break;
855 case DP_INT_STATUS:
856 s->core_registers[DP_INT_STATUS] &= ~value;
857 xlnx_dp_update_irq(s);
858 break;
859 case DP_INT_EN:
860 s->core_registers[DP_INT_MASK] &= ~value;
861 xlnx_dp_update_irq(s);
862 break;
863 case DP_INT_DS:
864 s->core_registers[DP_INT_MASK] |= ~value;
865 xlnx_dp_update_irq(s);
866 break;
867 default:
868 assert(offset <= (0x504C >> 2));
869 s->core_registers[offset] = value;
870 break;
871 }
872}
873
874static const MemoryRegionOps dp_ops = {
875 .read = xlnx_dp_read,
876 .write = xlnx_dp_write,
877 .endianness = DEVICE_NATIVE_ENDIAN,
878 .valid = {
879 .min_access_size = 4,
880 .max_access_size = 4,
881 },
882 .impl = {
883 .min_access_size = 4,
884 .max_access_size = 4,
885 },
886};
887
888
889
890
891static void xlnx_dp_vblend_write(void *opaque, hwaddr offset,
892 uint64_t value, unsigned size)
893{
894 XlnxDPState *s = XLNX_DP(opaque);
895 bool alpha_was_enabled;
896
897 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
898 (uint32_t)value);
899 offset = offset >> 2;
900
901 switch (offset) {
902 case V_BLEND_BG_CLR_0:
903 case V_BLEND_BG_CLR_1:
904 case V_BLEND_BG_CLR_2:
905 s->vblend_registers[offset] = value & 0x00000FFF;
906 break;
907 case V_BLEND_SET_GLOBAL_ALPHA_REG:
908
909
910
911
912 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s);
913 s->vblend_registers[offset] = value & 0x000001FF;
914 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
915 xlnx_dp_recreate_surface(s);
916 }
917 break;
918 case V_BLEND_OUTPUT_VID_FORMAT:
919 s->vblend_registers[offset] = value & 0x00000017;
920 break;
921 case V_BLEND_LAYER0_CONTROL:
922 case V_BLEND_LAYER1_CONTROL:
923 s->vblend_registers[offset] = value & 0x00000103;
924 break;
925 case V_BLEND_RGB2YCBCR_COEFF(0):
926 case V_BLEND_RGB2YCBCR_COEFF(1):
927 case V_BLEND_RGB2YCBCR_COEFF(2):
928 case V_BLEND_RGB2YCBCR_COEFF(3):
929 case V_BLEND_RGB2YCBCR_COEFF(4):
930 case V_BLEND_RGB2YCBCR_COEFF(5):
931 case V_BLEND_RGB2YCBCR_COEFF(6):
932 case V_BLEND_RGB2YCBCR_COEFF(7):
933 case V_BLEND_RGB2YCBCR_COEFF(8):
934 case V_BLEND_IN1CSC_COEFF(0):
935 case V_BLEND_IN1CSC_COEFF(1):
936 case V_BLEND_IN1CSC_COEFF(2):
937 case V_BLEND_IN1CSC_COEFF(3):
938 case V_BLEND_IN1CSC_COEFF(4):
939 case V_BLEND_IN1CSC_COEFF(5):
940 case V_BLEND_IN1CSC_COEFF(6):
941 case V_BLEND_IN1CSC_COEFF(7):
942 case V_BLEND_IN1CSC_COEFF(8):
943 case V_BLEND_IN2CSC_COEFF(0):
944 case V_BLEND_IN2CSC_COEFF(1):
945 case V_BLEND_IN2CSC_COEFF(2):
946 case V_BLEND_IN2CSC_COEFF(3):
947 case V_BLEND_IN2CSC_COEFF(4):
948 case V_BLEND_IN2CSC_COEFF(5):
949 case V_BLEND_IN2CSC_COEFF(6):
950 case V_BLEND_IN2CSC_COEFF(7):
951 case V_BLEND_IN2CSC_COEFF(8):
952 s->vblend_registers[offset] = value & 0x0000FFFF;
953 break;
954 case V_BLEND_LUMA_IN1CSC_OFFSET:
955 case V_BLEND_CR_IN1CSC_OFFSET:
956 case V_BLEND_CB_IN1CSC_OFFSET:
957 case V_BLEND_LUMA_IN2CSC_OFFSET:
958 case V_BLEND_CR_IN2CSC_OFFSET:
959 case V_BLEND_CB_IN2CSC_OFFSET:
960 case V_BLEND_LUMA_OUTCSC_OFFSET:
961 case V_BLEND_CR_OUTCSC_OFFSET:
962 case V_BLEND_CB_OUTCSC_OFFSET:
963 s->vblend_registers[offset] = value & 0x3FFF7FFF;
964 break;
965 case V_BLEND_CHROMA_KEY_ENABLE:
966 s->vblend_registers[offset] = value & 0x00000003;
967 break;
968 case V_BLEND_CHROMA_KEY_COMP1:
969 case V_BLEND_CHROMA_KEY_COMP2:
970 case V_BLEND_CHROMA_KEY_COMP3:
971 s->vblend_registers[offset] = value & 0x0FFF0FFF;
972 break;
973 default:
974 s->vblend_registers[offset] = value;
975 break;
976 }
977}
978
979static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset,
980 unsigned size)
981{
982 XlnxDPState *s = XLNX_DP(opaque);
983
984 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
985 s->vblend_registers[offset >> 2]);
986 return s->vblend_registers[offset >> 2];
987}
988
989static const MemoryRegionOps vblend_ops = {
990 .read = xlnx_dp_vblend_read,
991 .write = xlnx_dp_vblend_write,
992 .endianness = DEVICE_NATIVE_ENDIAN,
993 .valid = {
994 .min_access_size = 4,
995 .max_access_size = 4,
996 },
997 .impl = {
998 .min_access_size = 4,
999 .max_access_size = 4,
1000 },
1001};
1002
1003
1004
1005
1006static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
1007 unsigned size)
1008{
1009 XlnxDPState *s = XLNX_DP(opaque);
1010
1011 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
1012 (uint32_t)value);
1013 offset = offset >> 2;
1014
1015 switch (offset) {
1016 case AV_BUF_FORMAT:
1017 s->avbufm_registers[offset] = value & 0x00000FFF;
1018 xlnx_dp_change_graphic_fmt(s);
1019 break;
1020 case AV_CHBUF0:
1021 case AV_CHBUF1:
1022 case AV_CHBUF2:
1023 case AV_CHBUF3:
1024 case AV_CHBUF4:
1025 case AV_CHBUF5:
1026 s->avbufm_registers[offset] = value & 0x0000007F;
1027 break;
1028 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
1029 s->avbufm_registers[offset] = value & 0x0000007F;
1030 break;
1031 case AV_BUF_DITHER_CONFIG:
1032 s->avbufm_registers[offset] = value & 0x000007FF;
1033 break;
1034 case AV_BUF_DITHER_CONFIG_MAX:
1035 case AV_BUF_DITHER_CONFIG_MIN:
1036 s->avbufm_registers[offset] = value & 0x00000FFF;
1037 break;
1038 case AV_BUF_PATTERN_GEN_SELECT:
1039 s->avbufm_registers[offset] = value & 0xFFFFFF03;
1040 break;
1041 case AV_BUF_AUD_VID_CLK_SOURCE:
1042 s->avbufm_registers[offset] = value & 0x00000007;
1043 break;
1044 case AV_BUF_SRST_REG:
1045 s->avbufm_registers[offset] = value & 0x00000002;
1046 break;
1047 case AV_BUF_AUDIO_CH_CONFIG:
1048 s->avbufm_registers[offset] = value & 0x00000003;
1049 break;
1050 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0):
1051 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1):
1052 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2):
1053 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0):
1054 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1):
1055 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2):
1056 s->avbufm_registers[offset] = value & 0x0000FFFF;
1057 break;
1058 case AV_BUF_LIVE_VIDEO_COMP_SF(0):
1059 case AV_BUF_LIVE_VIDEO_COMP_SF(1):
1060 case AV_BUF_LIVE_VIDEO_COMP_SF(2):
1061 case AV_BUF_LIVE_VID_CONFIG:
1062 case AV_BUF_LIVE_GFX_COMP_SF(0):
1063 case AV_BUF_LIVE_GFX_COMP_SF(1):
1064 case AV_BUF_LIVE_GFX_COMP_SF(2):
1065 case AV_BUF_LIVE_GFX_CONFIG:
1066 case AV_BUF_NON_LIVE_LATENCY:
1067 case AV_BUF_STC_CONTROL:
1068 case AV_BUF_STC_INIT_VALUE0:
1069 case AV_BUF_STC_INIT_VALUE1:
1070 case AV_BUF_STC_ADJ:
1071 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
1072 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
1073 case AV_BUF_STC_EXT_VSYNC_TS_REG0:
1074 case AV_BUF_STC_EXT_VSYNC_TS_REG1:
1075 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
1076 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
1077 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
1078 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
1079 case AV_BUF_STC_SNAPSHOT0:
1080 case AV_BUF_STC_SNAPSHOT1:
1081 case AV_BUF_HCOUNT_VCOUNT_INT0:
1082 case AV_BUF_HCOUNT_VCOUNT_INT1:
1083 qemu_log_mask(LOG_UNIMP, "avbufm: unimplmented");
1084 break;
1085 default:
1086 s->avbufm_registers[offset] = value;
1087 break;
1088 }
1089}
1090
1091static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset,
1092 unsigned size)
1093{
1094 XlnxDPState *s = XLNX_DP(opaque);
1095
1096 offset = offset >> 2;
1097 return s->avbufm_registers[offset];
1098}
1099
1100static const MemoryRegionOps avbufm_ops = {
1101 .read = xlnx_dp_avbufm_read,
1102 .write = xlnx_dp_avbufm_write,
1103 .endianness = DEVICE_NATIVE_ENDIAN,
1104 .valid = {
1105 .min_access_size = 4,
1106 .max_access_size = 4,
1107 },
1108 .impl = {
1109 .min_access_size = 4,
1110 .max_access_size = 4,
1111 },
1112};
1113
1114
1115
1116
1117
1118
1119static inline void xlnx_dp_blend_surface(XlnxDPState *s)
1120{
1121 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
1122 pixman_double_to_fixed(1),
1123 pixman_double_to_fixed(1.0) };
1124 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
1125 pixman_double_to_fixed(1),
1126 pixman_double_to_fixed(1.0) };
1127
1128 if ((surface_width(s->g_plane.surface)
1129 != surface_width(s->v_plane.surface)) ||
1130 (surface_height(s->g_plane.surface)
1131 != surface_height(s->v_plane.surface))) {
1132 return;
1133 }
1134
1135 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s))
1136 / 256.0);
1137 alpha2[2] = pixman_double_to_fixed((255.0
1138 - (double)xlnx_dp_global_alpha_value(s))
1139 / 256.0);
1140
1141 pixman_image_set_filter(s->g_plane.surface->image,
1142 PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
1143 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
1144 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1145 surface_width(s->g_plane.surface),
1146 surface_height(s->g_plane.surface));
1147 pixman_image_set_filter(s->v_plane.surface->image,
1148 PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
1149 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
1150 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1151 surface_width(s->g_plane.surface),
1152 surface_height(s->g_plane.surface));
1153}
1154
1155static void xlnx_dp_update_display(void *opaque)
1156{
1157 XlnxDPState *s = XLNX_DP(opaque);
1158
1159 if (DEBUG_DP) {
1160 int64_t last_time = 0;
1161 int64_t frame = 0;
1162 int64_t time = get_clock();
1163 int64_t fps;
1164
1165 if (last_time == 0) {
1166 last_time = get_clock();
1167 }
1168 frame++;
1169 if (last_time + 1000000000 < time) {
1170 fps = (1000000000.0 * frame) / (time - last_time);
1171 last_time = time;
1172 frame = 0;
1173 DPRINTF("xlnx_dp: %ldfps\n", fps);
1174 }
1175 }
1176
1177
1178 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
1179 return;
1180 }
1181
1182 s->core_registers[DP_INT_STATUS] |= (1 << 13);
1183 xlnx_dp_update_irq(s);
1184
1185 xlnx_dpdma_trigger_vsync_irq(s->dpdma);
1186
1187
1188
1189
1190 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) {
1191
1192
1193
1194
1195 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1196 xlnx_dp_update_irq(s);
1197 return;
1198 }
1199
1200 if (xlnx_dp_global_alpha_enabled(s)) {
1201 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) {
1202 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1203 xlnx_dp_update_irq(s);
1204 return;
1205 }
1206 xlnx_dp_blend_surface(s);
1207 }
1208
1209
1210
1211
1212 dpy_gfx_update(s->console, 0, 0, surface_width(s->g_plane.surface),
1213 surface_height(s->g_plane.surface));
1214}
1215
1216static const GraphicHwOps xlnx_dp_gfx_ops = {
1217 .gfx_update = xlnx_dp_update_display,
1218};
1219
1220static void xlnx_dp_init(Object *obj)
1221{
1222 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1223 XlnxDPState *s = XLNX_DP(obj);
1224
1225 memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050);
1226
1227 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP
1228 ".core", 0x3AF);
1229 memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
1230
1231 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP
1232 ".v_blend", 0x1DF);
1233 memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
1234
1235 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP
1236 ".av_buffer_manager", 0x238);
1237 memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
1238 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP
1239 ".audio", sizeof(s->audio_registers));
1240 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
1241 sysbus_init_mmio(sbd, &s->container);
1242
1243 sysbus_init_irq(sbd, &s->irq);
1244
1245 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA,
1246 (Object **) &s->dpdma,
1247 xlnx_dp_set_dpdma,
1248 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1249 &error_abort);
1250
1251
1252
1253
1254 s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
1255
1256
1257
1258
1259 s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd", 0x00000));
1260 s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
1261 i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
1262
1263 fifo8_create(&s->rx_fifo, 16);
1264 fifo8_create(&s->tx_fifo, 16);
1265}
1266
1267static void xlnx_dp_realize(DeviceState *dev, Error **errp)
1268{
1269 XlnxDPState *s = XLNX_DP(dev);
1270 DisplaySurface *surface;
1271 struct audsettings as;
1272
1273 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
1274 surface = qemu_console_surface(s->console);
1275 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
1276 surface_data(surface));
1277
1278 as.freq = 44100;
1279 as.nchannels = 2;
1280 as.fmt = AUD_FMT_S16;
1281 as.endianness = 0;
1282
1283 AUD_register_card("xlnx_dp.audio", &s->aud_card);
1284
1285 s->amixer_output_stream = AUD_open_out(&s->aud_card,
1286 s->amixer_output_stream,
1287 "xlnx_dp.audio.out",
1288 s,
1289 xlnx_dp_audio_callback,
1290 &as);
1291 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
1292 xlnx_dp_audio_activate(s);
1293}
1294
1295static void xlnx_dp_reset(DeviceState *dev)
1296{
1297 XlnxDPState *s = XLNX_DP(dev);
1298
1299 memset(s->core_registers, 0, sizeof(s->core_registers));
1300 s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
1301 s->core_registers[DP_CORE_ID] = 0x01020000;
1302 s->core_registers[DP_REPLY_STATUS] = 0x00000010;
1303 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
1304 s->core_registers[DP_INIT_WAIT] = 0x00000020;
1305 s->core_registers[DP_PHY_RESET] = 0x00010003;
1306 s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
1307 s->core_registers[DP_PHY_STATUS] = 0x00000043;
1308 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
1309
1310 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000;
1311 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000;
1312 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000;
1313 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000;
1314 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000;
1315 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000;
1316 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000;
1317 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000;
1318 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000;
1319
1320 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
1321 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
1322 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
1323 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101;
1324 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101;
1325 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101;
1326 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101;
1327 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101;
1328 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101;
1329 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101;
1330 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101;
1331 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101;
1332 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101;
1333 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101;
1334 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101;
1335
1336 memset(s->audio_registers, 0, sizeof(s->audio_registers));
1337 s->byte_left = 0;
1338
1339 xlnx_dp_aux_clear_rx_fifo(s);
1340 xlnx_dp_change_graphic_fmt(s);
1341 xlnx_dp_update_irq(s);
1342}
1343
1344static void xlnx_dp_class_init(ObjectClass *oc, void *data)
1345{
1346 DeviceClass *dc = DEVICE_CLASS(oc);
1347
1348 dc->realize = xlnx_dp_realize;
1349 dc->vmsd = &vmstate_dp;
1350 dc->reset = xlnx_dp_reset;
1351}
1352
1353static const TypeInfo xlnx_dp_info = {
1354 .name = TYPE_XLNX_DP,
1355 .parent = TYPE_SYS_BUS_DEVICE,
1356 .instance_size = sizeof(XlnxDPState),
1357 .instance_init = xlnx_dp_init,
1358 .class_init = xlnx_dp_class_init,
1359};
1360
1361static void xlnx_dp_register_types(void)
1362{
1363 type_register_static(&xlnx_dp_info);
1364}
1365
1366type_init(xlnx_dp_register_types)
1367