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6#include "qemu/osdep.h"
7#include "qapi/error.h"
8#include "hw/dma/bcm2835_dma.h"
9
10
11#define BCM2708_DMA_ACTIVE (1 << 0)
12#define BCM2708_DMA_END (1 << 1)
13#define BCM2708_DMA_INT (1 << 2)
14#define BCM2708_DMA_ISPAUSED (1 << 4)
15#define BCM2708_DMA_ISHELD (1 << 5)
16#define BCM2708_DMA_ERR (1 << 8)
17#define BCM2708_DMA_ABORT (1 << 30)
18#define BCM2708_DMA_RESET (1 << 31)
19
20
21#define BCM2708_DMA_INT_EN (1 << 0)
22#define BCM2708_DMA_TDMODE (1 << 1)
23#define BCM2708_DMA_WAIT_RESP (1 << 3)
24#define BCM2708_DMA_D_INC (1 << 4)
25#define BCM2708_DMA_D_WIDTH (1 << 5)
26#define BCM2708_DMA_D_DREQ (1 << 6)
27#define BCM2708_DMA_D_IGNORE (1 << 7)
28#define BCM2708_DMA_S_INC (1 << 8)
29#define BCM2708_DMA_S_WIDTH (1 << 9)
30#define BCM2708_DMA_S_DREQ (1 << 10)
31#define BCM2708_DMA_S_IGNORE (1 << 11)
32
33
34#define BCM2708_DMA_CS 0x00
35#define BCM2708_DMA_ADDR 0x04
36
37#define BCM2708_DMA_INFO 0x08
38#define BCM2708_DMA_SOURCE_AD 0x0c
39#define BCM2708_DMA_DEST_AD 0x10
40#define BCM2708_DMA_TXFR_LEN 0x14
41#define BCM2708_DMA_STRIDE 0x18
42#define BCM2708_DMA_NEXTCB 0x1C
43#define BCM2708_DMA_DEBUG 0x20
44
45#define BCM2708_DMA_INT_STATUS 0xfe0
46#define BCM2708_DMA_ENABLE 0xff0
47
48#define BCM2708_DMA_CS_RW_MASK 0x30ff0001
49
50static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
51{
52 BCM2835DMAChan *ch = &s->chan[c];
53 uint32_t data, xlen, ylen;
54 int16_t dst_stride, src_stride;
55
56 if (!(s->enable & (1 << c))) {
57 return;
58 }
59
60 while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
61
62 ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad);
63 ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4);
64 ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8);
65 ch->txfr_len = ldl_le_phys(&s->dma_as, ch->conblk_ad + 12);
66 ch->stride = ldl_le_phys(&s->dma_as, ch->conblk_ad + 16);
67 ch->nextconbk = ldl_le_phys(&s->dma_as, ch->conblk_ad + 20);
68
69 if (ch->ti & BCM2708_DMA_TDMODE) {
70
71 ylen = (ch->txfr_len >> 16) & 0x3fff;
72 xlen = ch->txfr_len & 0xffff;
73 dst_stride = ch->stride >> 16;
74 src_stride = ch->stride & 0xffff;
75 } else {
76 ylen = 1;
77 xlen = ch->txfr_len;
78 dst_stride = 0;
79 src_stride = 0;
80 }
81
82 while (ylen != 0) {
83
84 while (xlen != 0) {
85 if (ch->ti & BCM2708_DMA_S_IGNORE) {
86
87 data = 0;
88 } else {
89 data = ldl_le_phys(&s->dma_as, ch->source_ad);
90 }
91 if (ch->ti & BCM2708_DMA_S_INC) {
92 ch->source_ad += 4;
93 }
94
95 if (ch->ti & BCM2708_DMA_D_IGNORE) {
96
97 } else {
98 stl_le_phys(&s->dma_as, ch->dest_ad, data);
99 }
100 if (ch->ti & BCM2708_DMA_D_INC) {
101 ch->dest_ad += 4;
102 }
103
104
105 xlen -= 4;
106 if (ch->ti & BCM2708_DMA_TDMODE) {
107 ch->txfr_len = (ylen << 16) | xlen;
108 } else {
109 ch->txfr_len = xlen;
110 }
111 }
112
113 if (--ylen != 0) {
114 ch->source_ad += src_stride;
115 ch->dest_ad += dst_stride;
116 }
117 }
118 ch->cs |= BCM2708_DMA_END;
119 if (ch->ti & BCM2708_DMA_INT_EN) {
120 ch->cs |= BCM2708_DMA_INT;
121 s->int_status |= (1 << c);
122 qemu_set_irq(ch->irq, 1);
123 }
124
125
126 ch->conblk_ad = ch->nextconbk;
127 }
128
129 ch->cs &= ~BCM2708_DMA_ACTIVE;
130 ch->cs |= BCM2708_DMA_ISPAUSED;
131}
132
133static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch)
134{
135 ch->cs = 0;
136 ch->conblk_ad = 0;
137}
138
139static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset,
140 unsigned size, unsigned c)
141{
142 BCM2835DMAChan *ch;
143 uint32_t res = 0;
144
145 assert(size == 4);
146 assert(c < BCM2835_DMA_NCHANS);
147
148 ch = &s->chan[c];
149
150 switch (offset) {
151 case BCM2708_DMA_CS:
152 res = ch->cs;
153 break;
154 case BCM2708_DMA_ADDR:
155 res = ch->conblk_ad;
156 break;
157 case BCM2708_DMA_INFO:
158 res = ch->ti;
159 break;
160 case BCM2708_DMA_SOURCE_AD:
161 res = ch->source_ad;
162 break;
163 case BCM2708_DMA_DEST_AD:
164 res = ch->dest_ad;
165 break;
166 case BCM2708_DMA_TXFR_LEN:
167 res = ch->txfr_len;
168 break;
169 case BCM2708_DMA_STRIDE:
170 res = ch->stride;
171 break;
172 case BCM2708_DMA_NEXTCB:
173 res = ch->nextconbk;
174 break;
175 case BCM2708_DMA_DEBUG:
176 res = ch->debug;
177 break;
178 default:
179 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
180 __func__, offset);
181 break;
182 }
183 return res;
184}
185
186static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
187 uint64_t value, unsigned size, unsigned c)
188{
189 BCM2835DMAChan *ch;
190 uint32_t oldcs;
191
192 assert(size == 4);
193 assert(c < BCM2835_DMA_NCHANS);
194
195 ch = &s->chan[c];
196
197 switch (offset) {
198 case BCM2708_DMA_CS:
199 oldcs = ch->cs;
200 if (value & BCM2708_DMA_RESET) {
201 bcm2835_dma_chan_reset(ch);
202 }
203 if (value & BCM2708_DMA_ABORT) {
204
205 }
206 if (value & BCM2708_DMA_END) {
207 ch->cs &= ~BCM2708_DMA_END;
208 }
209 if (value & BCM2708_DMA_INT) {
210 ch->cs &= ~BCM2708_DMA_INT;
211 s->int_status &= ~(1 << c);
212 qemu_set_irq(ch->irq, 0);
213 }
214 ch->cs &= ~BCM2708_DMA_CS_RW_MASK;
215 ch->cs |= (value & BCM2708_DMA_CS_RW_MASK);
216 if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
217 bcm2835_dma_update(s, c);
218 }
219 break;
220 case BCM2708_DMA_ADDR:
221 ch->conblk_ad = value;
222 break;
223 case BCM2708_DMA_DEBUG:
224 ch->debug = value;
225 break;
226 default:
227 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
228 __func__, offset);
229 break;
230 }
231}
232
233static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
234{
235 BCM2835DMAState *s = opaque;
236
237 if (offset < 0xf00) {
238 return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
239 } else {
240 switch (offset) {
241 case BCM2708_DMA_INT_STATUS:
242 return s->int_status;
243 case BCM2708_DMA_ENABLE:
244 return s->enable;
245 default:
246 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
247 __func__, offset);
248 return 0;
249 }
250 }
251}
252
253static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
254{
255 return bcm2835_dma_read(opaque, (offset & 0xff), size, 15);
256}
257
258static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value,
259 unsigned size)
260{
261 BCM2835DMAState *s = opaque;
262
263 if (offset < 0xf00) {
264 bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf);
265 } else {
266 switch (offset) {
267 case BCM2708_DMA_INT_STATUS:
268 break;
269 case BCM2708_DMA_ENABLE:
270 s->enable = (value & 0xffff);
271 break;
272 default:
273 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
274 __func__, offset);
275 }
276 }
277
278}
279
280static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
281 unsigned size)
282{
283 bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15);
284}
285
286static const MemoryRegionOps bcm2835_dma0_ops = {
287 .read = bcm2835_dma0_read,
288 .write = bcm2835_dma0_write,
289 .endianness = DEVICE_NATIVE_ENDIAN,
290 .valid.min_access_size = 4,
291 .valid.max_access_size = 4,
292};
293
294static const MemoryRegionOps bcm2835_dma15_ops = {
295 .read = bcm2835_dma15_read,
296 .write = bcm2835_dma15_write,
297 .endianness = DEVICE_NATIVE_ENDIAN,
298 .valid.min_access_size = 4,
299 .valid.max_access_size = 4,
300};
301
302static const VMStateDescription vmstate_bcm2835_dma_chan = {
303 .name = TYPE_BCM2835_DMA "-chan",
304 .version_id = 1,
305 .minimum_version_id = 1,
306 .fields = (VMStateField[]) {
307 VMSTATE_UINT32(cs, BCM2835DMAChan),
308 VMSTATE_UINT32(conblk_ad, BCM2835DMAChan),
309 VMSTATE_UINT32(ti, BCM2835DMAChan),
310 VMSTATE_UINT32(source_ad, BCM2835DMAChan),
311 VMSTATE_UINT32(dest_ad, BCM2835DMAChan),
312 VMSTATE_UINT32(txfr_len, BCM2835DMAChan),
313 VMSTATE_UINT32(stride, BCM2835DMAChan),
314 VMSTATE_UINT32(nextconbk, BCM2835DMAChan),
315 VMSTATE_UINT32(debug, BCM2835DMAChan),
316 VMSTATE_END_OF_LIST()
317 }
318};
319
320static const VMStateDescription vmstate_bcm2835_dma = {
321 .name = TYPE_BCM2835_DMA,
322 .version_id = 1,
323 .minimum_version_id = 1,
324 .fields = (VMStateField[]) {
325 VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1,
326 vmstate_bcm2835_dma_chan, BCM2835DMAChan),
327 VMSTATE_UINT32(int_status, BCM2835DMAState),
328 VMSTATE_UINT32(enable, BCM2835DMAState),
329 VMSTATE_END_OF_LIST()
330 }
331};
332
333static void bcm2835_dma_init(Object *obj)
334{
335 BCM2835DMAState *s = BCM2835_DMA(obj);
336 int n;
337
338
339
340
341
342
343 memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s,
344 TYPE_BCM2835_DMA, 0x1000);
345 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0);
346
347 memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
348 TYPE_BCM2835_DMA "-chan15", 0x100);
349 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15);
350
351 for (n = 0; n < 16; n++) {
352 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq);
353 }
354}
355
356static void bcm2835_dma_reset(DeviceState *dev)
357{
358 BCM2835DMAState *s = BCM2835_DMA(dev);
359 int n;
360
361 s->enable = 0xffff;
362 s->int_status = 0;
363 for (n = 0; n < BCM2835_DMA_NCHANS; n++) {
364 bcm2835_dma_chan_reset(&s->chan[n]);
365 }
366}
367
368static void bcm2835_dma_realize(DeviceState *dev, Error **errp)
369{
370 BCM2835DMAState *s = BCM2835_DMA(dev);
371 Error *err = NULL;
372 Object *obj;
373
374 obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
375 if (obj == NULL) {
376 error_setg(errp, "%s: required dma-mr link not found: %s",
377 __func__, error_get_pretty(err));
378 return;
379 }
380
381 s->dma_mr = MEMORY_REGION(obj);
382 address_space_init(&s->dma_as, s->dma_mr, NULL);
383
384 bcm2835_dma_reset(dev);
385}
386
387static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
388{
389 DeviceClass *dc = DEVICE_CLASS(klass);
390
391 dc->realize = bcm2835_dma_realize;
392 dc->reset = bcm2835_dma_reset;
393 dc->vmsd = &vmstate_bcm2835_dma;
394}
395
396static TypeInfo bcm2835_dma_info = {
397 .name = TYPE_BCM2835_DMA,
398 .parent = TYPE_SYS_BUS_DEVICE,
399 .instance_size = sizeof(BCM2835DMAState),
400 .class_init = bcm2835_dma_class_init,
401 .instance_init = bcm2835_dma_init,
402};
403
404static void bcm2835_dma_register_types(void)
405{
406 type_register_static(&bcm2835_dma_info);
407}
408
409type_init(bcm2835_dma_register_types)
410
