LXR qemu/hw/dma/sun4m

   1/*
   2 * QEMU Sun4m iommu emulation
   3 *
   4 * Copyright (c) 2003-2005 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/sparc/sun4m.h"
  27#include "hw/sysbus.h"
  28#include "exec/address-spaces.h"
  29#include "trace.h"
  30
  31/*
  32 * I/O MMU used by Sun4m systems
  33 *
  34 * Chipset docs:
  35 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
  36 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
  37 */
  38
  39#define IOMMU_NREGS         (4*4096/4)
  40#define IOMMU_CTRL          (0x0000 >> 2)
  41#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  42#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  43#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  44#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  45#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  46#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  47#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  48#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  49#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  50#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  51#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  52#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  53#define IOMMU_CTRL_MASK     0x0000001d
  54
  55#define IOMMU_BASE          (0x0004 >> 2)
  56#define IOMMU_BASE_MASK     0x07fffc00
  57
  58#define IOMMU_TLBFLUSH      (0x0014 >> 2)
  59#define IOMMU_TLBFLUSH_MASK 0xffffffff
  60
  61#define IOMMU_PGFLUSH       (0x0018 >> 2)
  62#define IOMMU_PGFLUSH_MASK  0xffffffff
  63
  64#define IOMMU_AFSR          (0x1000 >> 2)
  65#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  66#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
  67                                          transaction */
  68#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
  69                                          12.8 us. */
  70#define IOMMU_AFSR_BE       0x10000000 /* Write access received error
  71                                          acknowledge */
  72#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  73#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  74#define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
  75                                          hardware */
  76#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  77#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  78#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  79#define IOMMU_AFSR_MASK     0xff0fffff
  80
  81#define IOMMU_AFAR          (0x1004 >> 2)
  82
  83#define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
  84#define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
  85#define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
  86#define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
  87#define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
  88#define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
  89#define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
  90#define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
  91#define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
  92#define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
  93#define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
  94#define IOMMU_AER_MASK      0x801f000f
  95
  96#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  97#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  98#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  99#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
 100#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
 101                                          bypass enabled */
 102#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
 103#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
 104#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
 105                                          produced by this device as pure
 106                                          physical. */
 107#define IOMMU_SBCFG_MASK    0x00010003
 108
 109#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
 110#define IOMMU_ARBEN_MASK    0x001f0000
 111#define IOMMU_MID           0x00000008
 112
 113#define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
 114#define IOMMU_MASK_ID_MASK  0x00ffffff
 115
 116#define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
 117#define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */
 118
 119/* The format of an iopte in the page tables */
 120#define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
 121#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
 122                                          Viking/MXCC) */
 123#define IOPTE_WRITE         0x00000004 /* Writable */
 124#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
 125#define IOPTE_WAZ           0x00000001 /* Write as zeros */
 126
 127#define IOMMU_PAGE_SHIFT    12
 128#define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
 129#define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)
 130
 131#define TYPE_SUN4M_IOMMU "iommu"
 132#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU)
 133
 134typedef struct IOMMUState {
 135    SysBusDevice parent_obj;
 136
 137    MemoryRegion iomem;
 138    uint32_t regs[IOMMU_NREGS];
 139    hwaddr iostart;
 140    qemu_irq irq;
 141    uint32_t version;
 142} IOMMUState;
 143
 144static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
 145                               unsigned size)
 146{
 147    IOMMUState *s = opaque;
 148    hwaddr saddr;
 149    uint32_t ret;
 150
 151    saddr = addr >> 2;
 152    switch (saddr) {
 153    default:
 154        ret = s->regs[saddr];
 155        break;
 156    case IOMMU_AFAR:
 157    case IOMMU_AFSR:
 158        ret = s->regs[saddr];
 159        qemu_irq_lower(s->irq);
 160        break;
 161    }
 162    trace_sun4m_iommu_mem_readl(saddr, ret);
 163    return ret;
 164}
 165
 166static void iommu_mem_write(void *opaque, hwaddr addr,
 167                            uint64_t val, unsigned size)
 168{
 169    IOMMUState *s = opaque;
 170    hwaddr saddr;
 171
 172    saddr = addr >> 2;
 173    trace_sun4m_iommu_mem_writel(saddr, val);
 174    switch (saddr) {
 175    case IOMMU_CTRL:
 176        switch (val & IOMMU_CTRL_RNGE) {
 177        case IOMMU_RNGE_16MB:
 178            s->iostart = 0xffffffffff000000ULL;
 179            break;
 180        case IOMMU_RNGE_32MB:
 181            s->iostart = 0xfffffffffe000000ULL;
 182            break;
 183        case IOMMU_RNGE_64MB:
 184            s->iostart = 0xfffffffffc000000ULL;
 185            break;
 186        case IOMMU_RNGE_128MB:
 187            s->iostart = 0xfffffffff8000000ULL;
 188            break;
 189        case IOMMU_RNGE_256MB:
 190            s->iostart = 0xfffffffff0000000ULL;
 191            break;
 192        case IOMMU_RNGE_512MB:
 193            s->iostart = 0xffffffffe0000000ULL;
 194            break;
 195        case IOMMU_RNGE_1GB:
 196            s->iostart = 0xffffffffc0000000ULL;
 197            break;
 198        default:
 199        case IOMMU_RNGE_2GB:
 200            s->iostart = 0xffffffff80000000ULL;
 201            break;
 202        }
 203        trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
 204        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 205        break;
 206    case IOMMU_BASE:
 207        s->regs[saddr] = val & IOMMU_BASE_MASK;
 208        break;
 209    case IOMMU_TLBFLUSH:
 210        trace_sun4m_iommu_mem_writel_tlbflush(val);
 211        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 212        break;
 213    case IOMMU_PGFLUSH:
 214        trace_sun4m_iommu_mem_writel_pgflush(val);
 215        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 216        break;
 217    case IOMMU_AFAR:
 218        s->regs[saddr] = val;
 219        qemu_irq_lower(s->irq);
 220        break;
 221    case IOMMU_AER:
 222        s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
 223        break;
 224    case IOMMU_AFSR:
 225        s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
 226        qemu_irq_lower(s->irq);
 227        break;
 228    case IOMMU_SBCFG0:
 229    case IOMMU_SBCFG1:
 230    case IOMMU_SBCFG2:
 231    case IOMMU_SBCFG3:
 232        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 233        break;
 234    case IOMMU_ARBEN:
 235        // XXX implement SBus probing: fault when reading unmapped
 236        // addresses, fault cause and address stored to MMU/IOMMU
 237        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 238        break;
 239    case IOMMU_MASK_ID:
 240        s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
 241        break;
 242    default:
 243        s->regs[saddr] = val;
 244        break;
 245    }
 246}
 247
 248static const MemoryRegionOps iommu_mem_ops = {
 249    .read = iommu_mem_read,
 250    .write = iommu_mem_write,
 251    .endianness = DEVICE_NATIVE_ENDIAN,
 252    .valid = {
 253        .min_access_size = 4,
 254        .max_access_size = 4,
 255    },
 256};
 257
 258static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
 259{
 260    uint32_t ret;
 261    hwaddr iopte;
 262    hwaddr pa = addr;
 263
 264    iopte = s->regs[IOMMU_BASE] << 4;
 265    addr &= ~s->iostart;
 266    iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
 267    ret = address_space_ldl_be(&address_space_memory, iopte,
 268                               MEMTXATTRS_UNSPECIFIED, NULL);
 269    trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
 270    return ret;
 271}
 272
 273static hwaddr iommu_translate_pa(hwaddr addr,
 274                                             uint32_t pte)
 275{
 276    hwaddr pa;
 277
 278    pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
 279    trace_sun4m_iommu_translate_pa(addr, pa, pte);
 280    return pa;
 281}
 282
 283static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
 284                           int is_write)
 285{
 286    trace_sun4m_iommu_bad_addr(addr);
 287    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
 288        IOMMU_AFSR_FAV;
 289    if (!is_write)
 290        s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 291    s->regs[IOMMU_AFAR] = addr;
 292    qemu_irq_raise(s->irq);
 293}
 294
 295void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
 296                           uint8_t *buf, int len, int is_write)
 297{
 298    int l;
 299    uint32_t flags;
 300    hwaddr page, phys_addr;
 301
 302    while (len > 0) {
 303        page = addr & IOMMU_PAGE_MASK;
 304        l = (page + IOMMU_PAGE_SIZE) - addr;
 305        if (l > len)
 306            l = len;
 307        flags = iommu_page_get_flags(opaque, page);
 308        if (!(flags & IOPTE_VALID)) {
 309            iommu_bad_addr(opaque, page, is_write);
 310            return;
 311        }
 312        phys_addr = iommu_translate_pa(addr, flags);
 313        if (is_write) {
 314            if (!(flags & IOPTE_WRITE)) {
 315                iommu_bad_addr(opaque, page, is_write);
 316                return;
 317            }
 318            cpu_physical_memory_write(phys_addr, buf, l);
 319        } else {
 320            cpu_physical_memory_read(phys_addr, buf, l);
 321        }
 322        len -= l;
 323        buf += l;
 324        addr += l;
 325    }
 326}
 327
 328static const VMStateDescription vmstate_iommu = {
 329    .name ="iommu",
 330    .version_id = 2,
 331    .minimum_version_id = 2,
 332    .fields = (VMStateField[]) {
 333        VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
 334        VMSTATE_UINT64(iostart, IOMMUState),
 335        VMSTATE_END_OF_LIST()
 336    }
 337};
 338
 339static void iommu_reset(DeviceState *d)
 340{
 341    IOMMUState *s = SUN4M_IOMMU(d);
 342
 343    memset(s->regs, 0, IOMMU_NREGS * 4);
 344    s->iostart = 0;
 345    s->regs[IOMMU_CTRL] = s->version;
 346    s->regs[IOMMU_ARBEN] = IOMMU_MID;
 347    s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
 348    s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
 349    s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
 350}
 351
 352static int iommu_init1(SysBusDevice *dev)
 353{
 354    IOMMUState *s = SUN4M_IOMMU(dev);
 355
 356    sysbus_init_irq(dev, &s->irq);
 357
 358    memory_region_init_io(&s->iomem, OBJECT(s), &iommu_mem_ops, s, "iommu",
 359                          IOMMU_NREGS * sizeof(uint32_t));
 360    sysbus_init_mmio(dev, &s->iomem);
 361
 362    return 0;
 363}
 364
 365static Property iommu_properties[] = {
 366    DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
 367    DEFINE_PROP_END_OF_LIST(),
 368};
 369
 370static void iommu_class_init(ObjectClass *klass, void *data)
 371{
 372    DeviceClass *dc = DEVICE_CLASS(klass);
 373    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 374
 375    k->init = iommu_init1;
 376    dc->reset = iommu_reset;
 377    dc->vmsd = &vmstate_iommu;
 378    dc->props = iommu_properties;
 379}
 380
 381static const TypeInfo iommu_info = {
 382    .name          = TYPE_SUN4M_IOMMU,
 383    .parent        = TYPE_SYS_BUS_DEVICE,
 384    .instance_size = sizeof(IOMMUState),
 385    .class_init    = iommu_class_init,
 386};
 387
 388static void iommu_register_types(void)
 389{
 390    type_register_static(&iommu_info);
 391}
 392
 393type_init(iommu_register_types)
 394