LXR qemu/hw/gpio/pl061.c

   1/*
   2 * Arm PrimeCell PL061 General Purpose IO with additional
   3 * Luminary Micro Stellaris bits.
   4 *
   5 * Copyright (c) 2007 CodeSourcery.
   6 * Written by Paul Brook
   7 *
   8 * This code is licensed under the GPL.
   9 */
  10
  11#include "qemu/osdep.h"
  12#include "hw/sysbus.h"
  13#include "qemu/log.h"
  14
  15//#define DEBUG_PL061 1
  16
  17#ifdef DEBUG_PL061
  18#define DPRINTF(fmt, ...) \
  19do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
  20#define BADF(fmt, ...) \
  21do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  22#else
  23#define DPRINTF(fmt, ...) do {} while(0)
  24#define BADF(fmt, ...) \
  25do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
  26#endif
  27
  28static const uint8_t pl061_id[12] =
  29  { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  30static const uint8_t pl061_id_luminary[12] =
  31  { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
  32
  33#define TYPE_PL061 "pl061"
  34#define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)
  35
  36typedef struct PL061State {
  37    SysBusDevice parent_obj;
  38
  39    MemoryRegion iomem;
  40    uint32_t locked;
  41    uint32_t data;
  42    uint32_t old_out_data;
  43    uint32_t old_in_data;
  44    uint32_t dir;
  45    uint32_t isense;
  46    uint32_t ibe;
  47    uint32_t iev;
  48    uint32_t im;
  49    uint32_t istate;
  50    uint32_t afsel;
  51    uint32_t dr2r;
  52    uint32_t dr4r;
  53    uint32_t dr8r;
  54    uint32_t odr;
  55    uint32_t pur;
  56    uint32_t pdr;
  57    uint32_t slr;
  58    uint32_t den;
  59    uint32_t cr;
  60    uint32_t amsel;
  61    qemu_irq irq;
  62    qemu_irq out[8];
  63    const unsigned char *id;
  64    uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
  65} PL061State;
  66
  67static const VMStateDescription vmstate_pl061 = {
  68    .name = "pl061",
  69    .version_id = 4,
  70    .minimum_version_id = 4,
  71    .fields = (VMStateField[]) {
  72        VMSTATE_UINT32(locked, PL061State),
  73        VMSTATE_UINT32(data, PL061State),
  74        VMSTATE_UINT32(old_out_data, PL061State),
  75        VMSTATE_UINT32(old_in_data, PL061State),
  76        VMSTATE_UINT32(dir, PL061State),
  77        VMSTATE_UINT32(isense, PL061State),
  78        VMSTATE_UINT32(ibe, PL061State),
  79        VMSTATE_UINT32(iev, PL061State),
  80        VMSTATE_UINT32(im, PL061State),
  81        VMSTATE_UINT32(istate, PL061State),
  82        VMSTATE_UINT32(afsel, PL061State),
  83        VMSTATE_UINT32(dr2r, PL061State),
  84        VMSTATE_UINT32(dr4r, PL061State),
  85        VMSTATE_UINT32(dr8r, PL061State),
  86        VMSTATE_UINT32(odr, PL061State),
  87        VMSTATE_UINT32(pur, PL061State),
  88        VMSTATE_UINT32(pdr, PL061State),
  89        VMSTATE_UINT32(slr, PL061State),
  90        VMSTATE_UINT32(den, PL061State),
  91        VMSTATE_UINT32(cr, PL061State),
  92        VMSTATE_UINT32_V(amsel, PL061State, 2),
  93        VMSTATE_END_OF_LIST()
  94    }
  95};
  96
  97static void pl061_update(PL061State *s)
  98{
  99    uint8_t changed;
 100    uint8_t mask;
 101    uint8_t out;
 102    int i;
 103
 104    DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
 105
 106    /* Outputs float high.  */
 107    /* FIXME: This is board dependent.  */
 108    out = (s->data & s->dir) | ~s->dir;
 109    changed = s->old_out_data ^ out;
 110    if (changed) {
 111        s->old_out_data = out;
 112        for (i = 0; i < 8; i++) {
 113            mask = 1 << i;
 114            if (changed & mask) {
 115                DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
 116                qemu_set_irq(s->out[i], (out & mask) != 0);
 117            }
 118        }
 119    }
 120
 121    /* Inputs */
 122    changed = (s->old_in_data ^ s->data) & ~s->dir;
 123    if (changed) {
 124        s->old_in_data = s->data;
 125        for (i = 0; i < 8; i++) {
 126            mask = 1 << i;
 127            if (changed & mask) {
 128                DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
 129
 130                if (!(s->isense & mask)) {
 131                    /* Edge interrupt */
 132                    if (s->ibe & mask) {
 133                        /* Any edge triggers the interrupt */
 134                        s->istate |= mask;
 135                    } else {
 136                        /* Edge is selected by IEV */
 137                        s->istate |= ~(s->data ^ s->iev) & mask;
 138                    }
 139                }
 140            }
 141        }
 142    }
 143
 144    /* Level interrupt */
 145    s->istate |= ~(s->data ^ s->iev) & s->isense;
 146
 147    DPRINTF("istate = %02X\n", s->istate);
 148
 149    qemu_set_irq(s->irq, (s->istate & s->im) != 0);
 150}
 151
 152static uint64_t pl061_read(void *opaque, hwaddr offset,
 153                           unsigned size)
 154{
 155    PL061State *s = (PL061State *)opaque;
 156
 157    if (offset < 0x400) {
 158        return s->data & (offset >> 2);
 159    }
 160    if (offset >= s->rsvd_start && offset <= 0xfcc) {
 161        goto err_out;
 162    }
 163    if (offset >= 0xfd0 && offset < 0x1000) {
 164        return s->id[(offset - 0xfd0) >> 2];
 165    }
 166    switch (offset) {
 167    case 0x400: /* Direction */
 168        return s->dir;
 169    case 0x404: /* Interrupt sense */
 170        return s->isense;
 171    case 0x408: /* Interrupt both edges */
 172        return s->ibe;
 173    case 0x40c: /* Interrupt event */
 174        return s->iev;
 175    case 0x410: /* Interrupt mask */
 176        return s->im;
 177    case 0x414: /* Raw interrupt status */
 178        return s->istate;
 179    case 0x418: /* Masked interrupt status */
 180        return s->istate & s->im;
 181    case 0x420: /* Alternate function select */
 182        return s->afsel;
 183    case 0x500: /* 2mA drive */
 184        return s->dr2r;
 185    case 0x504: /* 4mA drive */
 186        return s->dr4r;
 187    case 0x508: /* 8mA drive */
 188        return s->dr8r;
 189    case 0x50c: /* Open drain */
 190        return s->odr;
 191    case 0x510: /* Pull-up */
 192        return s->pur;
 193    case 0x514: /* Pull-down */
 194        return s->pdr;
 195    case 0x518: /* Slew rate control */
 196        return s->slr;
 197    case 0x51c: /* Digital enable */
 198        return s->den;
 199    case 0x520: /* Lock */
 200        return s->locked;
 201    case 0x524: /* Commit */
 202        return s->cr;
 203    case 0x528: /* Analog mode select */
 204        return s->amsel;
 205    default:
 206        break;
 207    }
 208err_out:
 209    qemu_log_mask(LOG_GUEST_ERROR,
 210                  "pl061_read: Bad offset %x\n", (int)offset);
 211    return 0;
 212}
 213
 214static void pl061_write(void *opaque, hwaddr offset,
 215                        uint64_t value, unsigned size)
 216{
 217    PL061State *s = (PL061State *)opaque;
 218    uint8_t mask;
 219
 220    if (offset < 0x400) {
 221        mask = (offset >> 2) & s->dir;
 222        s->data = (s->data & ~mask) | (value & mask);
 223        pl061_update(s);
 224        return;
 225    }
 226    if (offset >= s->rsvd_start) {
 227        goto err_out;
 228    }
 229    switch (offset) {
 230    case 0x400: /* Direction */
 231        s->dir = value & 0xff;
 232        break;
 233    case 0x404: /* Interrupt sense */
 234        s->isense = value & 0xff;
 235        break;
 236    case 0x408: /* Interrupt both edges */
 237        s->ibe = value & 0xff;
 238        break;
 239    case 0x40c: /* Interrupt event */
 240        s->iev = value & 0xff;
 241        break;
 242    case 0x410: /* Interrupt mask */
 243        s->im = value & 0xff;
 244        break;
 245    case 0x41c: /* Interrupt clear */
 246        s->istate &= ~value;
 247        break;
 248    case 0x420: /* Alternate function select */
 249        mask = s->cr;
 250        s->afsel = (s->afsel & ~mask) | (value & mask);
 251        break;
 252    case 0x500: /* 2mA drive */
 253        s->dr2r = value & 0xff;
 254        break;
 255    case 0x504: /* 4mA drive */
 256        s->dr4r = value & 0xff;
 257        break;
 258    case 0x508: /* 8mA drive */
 259        s->dr8r = value & 0xff;
 260        break;
 261    case 0x50c: /* Open drain */
 262        s->odr = value & 0xff;
 263        break;
 264    case 0x510: /* Pull-up */
 265        s->pur = value & 0xff;
 266        break;
 267    case 0x514: /* Pull-down */
 268        s->pdr = value & 0xff;
 269        break;
 270    case 0x518: /* Slew rate control */
 271        s->slr = value & 0xff;
 272        break;
 273    case 0x51c: /* Digital enable */
 274        s->den = value & 0xff;
 275        break;
 276    case 0x520: /* Lock */
 277        s->locked = (value != 0xacce551);
 278        break;
 279    case 0x524: /* Commit */
 280        if (!s->locked)
 281            s->cr = value & 0xff;
 282        break;
 283    case 0x528:
 284        s->amsel = value & 0xff;
 285        break;
 286    default:
 287        goto err_out;
 288    }
 289    pl061_update(s);
 290    return;
 291err_out:
 292    qemu_log_mask(LOG_GUEST_ERROR,
 293                  "pl061_write: Bad offset %x\n", (int)offset);
 294}
 295
 296static void pl061_reset(DeviceState *dev)
 297{
 298    PL061State *s = PL061(dev);
 299
 300    /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
 301    s->data = 0;
 302    s->old_out_data = 0;
 303    s->old_in_data = 0;
 304    s->dir = 0;
 305    s->isense = 0;
 306    s->ibe = 0;
 307    s->iev = 0;
 308    s->im = 0;
 309    s->istate = 0;
 310    s->afsel = 0;
 311    s->dr2r = 0xff;
 312    s->dr4r = 0;
 313    s->dr8r = 0;
 314    s->odr = 0;
 315    s->pur = 0;
 316    s->pdr = 0;
 317    s->slr = 0;
 318    s->den = 0;
 319    s->locked = 1;
 320    s->cr = 0xff;
 321    s->amsel = 0;
 322}
 323
 324static void pl061_set_irq(void * opaque, int irq, int level)
 325{
 326    PL061State *s = (PL061State *)opaque;
 327    uint8_t mask;
 328
 329    mask = 1 << irq;
 330    if ((s->dir & mask) == 0) {
 331        s->data &= ~mask;
 332        if (level)
 333            s->data |= mask;
 334        pl061_update(s);
 335    }
 336}
 337
 338static const MemoryRegionOps pl061_ops = {
 339    .read = pl061_read,
 340    .write = pl061_write,
 341    .endianness = DEVICE_NATIVE_ENDIAN,
 342};
 343
 344static int pl061_initfn(SysBusDevice *sbd)
 345{
 346    DeviceState *dev = DEVICE(sbd);
 347    PL061State *s = PL061(dev);
 348
 349    memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000);
 350    sysbus_init_mmio(sbd, &s->iomem);
 351    sysbus_init_irq(sbd, &s->irq);
 352    qdev_init_gpio_in(dev, pl061_set_irq, 8);
 353    qdev_init_gpio_out(dev, s->out, 8);
 354
 355    return 0;
 356}
 357
 358static void pl061_luminary_init(Object *obj)
 359{
 360    PL061State *s = PL061(obj);
 361
 362    s->id = pl061_id_luminary;
 363    s->rsvd_start = 0x52c;
 364}
 365
 366static void pl061_init(Object *obj)
 367{
 368    PL061State *s = PL061(obj);
 369
 370    s->id = pl061_id;
 371    s->rsvd_start = 0x424;
 372}
 373
 374static void pl061_class_init(ObjectClass *klass, void *data)
 375{
 376    DeviceClass *dc = DEVICE_CLASS(klass);
 377    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 378
 379    k->init = pl061_initfn;
 380    dc->vmsd = &vmstate_pl061;
 381    dc->reset = &pl061_reset;
 382}
 383
 384static const TypeInfo pl061_info = {
 385    .name          = TYPE_PL061,
 386    .parent        = TYPE_SYS_BUS_DEVICE,
 387    .instance_size = sizeof(PL061State),
 388    .instance_init = pl061_init,
 389    .class_init    = pl061_class_init,
 390};
 391
 392static const TypeInfo pl061_luminary_info = {
 393    .name          = "pl061_luminary",
 394    .parent        = TYPE_PL061,
 395    .instance_init = pl061_luminary_init,
 396};
 397
 398static void pl061_register_types(void)
 399{
 400    type_register_static(&pl061_info);
 401    type_register_static(&pl061_luminary_info);
 402}
 403
 404type_init(pl061_register_types)
 405