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18#include "qemu/osdep.h"
19#include "hw/hw.h"
20#include "hw/arm/sharpsl.h"
21#include "hw/sysbus.h"
22
23#undef REG_FMT
24#define REG_FMT "0x%02lx"
25
26
27
28#define TYPE_SCOOP "scoop"
29#define SCOOP(obj) OBJECT_CHECK(ScoopInfo, (obj), TYPE_SCOOP)
30
31typedef struct ScoopInfo ScoopInfo;
32struct ScoopInfo {
33 SysBusDevice parent_obj;
34
35 qemu_irq handler[16];
36 MemoryRegion iomem;
37 uint16_t status;
38 uint16_t power;
39 uint32_t gpio_level;
40 uint32_t gpio_dir;
41 uint32_t prev_level;
42
43 uint16_t mcr;
44 uint16_t cdr;
45 uint16_t ccr;
46 uint16_t irr;
47 uint16_t imr;
48 uint16_t isr;
49};
50
51#define SCOOP_MCR 0x00
52#define SCOOP_CDR 0x04
53#define SCOOP_CSR 0x08
54#define SCOOP_CPR 0x0c
55#define SCOOP_CCR 0x10
56#define SCOOP_IRR_IRM 0x14
57#define SCOOP_IMR 0x18
58#define SCOOP_ISR 0x1c
59#define SCOOP_GPCR 0x20
60#define SCOOP_GPWR 0x24
61#define SCOOP_GPRR 0x28
62
63static inline void scoop_gpio_handler_update(ScoopInfo *s) {
64 uint32_t level, diff;
65 int bit;
66 level = s->gpio_level & s->gpio_dir;
67
68 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
69 bit = ctz32(diff);
70 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
71 }
72
73 s->prev_level = level;
74}
75
76static uint64_t scoop_read(void *opaque, hwaddr addr,
77 unsigned size)
78{
79 ScoopInfo *s = (ScoopInfo *) opaque;
80
81 switch (addr & 0x3f) {
82 case SCOOP_MCR:
83 return s->mcr;
84 case SCOOP_CDR:
85 return s->cdr;
86 case SCOOP_CSR:
87 return s->status;
88 case SCOOP_CPR:
89 return s->power;
90 case SCOOP_CCR:
91 return s->ccr;
92 case SCOOP_IRR_IRM:
93 return s->irr;
94 case SCOOP_IMR:
95 return s->imr;
96 case SCOOP_ISR:
97 return s->isr;
98 case SCOOP_GPCR:
99 return s->gpio_dir;
100 case SCOOP_GPWR:
101 case SCOOP_GPRR:
102 return s->gpio_level;
103 default:
104 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
105 }
106
107 return 0;
108}
109
110static void scoop_write(void *opaque, hwaddr addr,
111 uint64_t value, unsigned size)
112{
113 ScoopInfo *s = (ScoopInfo *) opaque;
114 value &= 0xffff;
115
116 switch (addr & 0x3f) {
117 case SCOOP_MCR:
118 s->mcr = value;
119 break;
120 case SCOOP_CDR:
121 s->cdr = value;
122 break;
123 case SCOOP_CPR:
124 s->power = value;
125 if (value & 0x80)
126 s->power |= 0x8040;
127 break;
128 case SCOOP_CCR:
129 s->ccr = value;
130 break;
131 case SCOOP_IRR_IRM:
132 s->irr = value;
133 break;
134 case SCOOP_IMR:
135 s->imr = value;
136 break;
137 case SCOOP_ISR:
138 s->isr = value;
139 break;
140 case SCOOP_GPCR:
141 s->gpio_dir = value;
142 scoop_gpio_handler_update(s);
143 break;
144 case SCOOP_GPWR:
145 case SCOOP_GPRR:
146 s->gpio_level = value & s->gpio_dir;
147 scoop_gpio_handler_update(s);
148 break;
149 default:
150 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
151 }
152}
153
154static const MemoryRegionOps scoop_ops = {
155 .read = scoop_read,
156 .write = scoop_write,
157 .endianness = DEVICE_NATIVE_ENDIAN,
158};
159
160static void scoop_gpio_set(void *opaque, int line, int level)
161{
162 ScoopInfo *s = (ScoopInfo *) opaque;
163
164 if (level)
165 s->gpio_level |= (1 << line);
166 else
167 s->gpio_level &= ~(1 << line);
168}
169
170static int scoop_init(SysBusDevice *sbd)
171{
172 DeviceState *dev = DEVICE(sbd);
173 ScoopInfo *s = SCOOP(dev);
174
175 s->status = 0x02;
176 qdev_init_gpio_out(dev, s->handler, 16);
177 qdev_init_gpio_in(dev, scoop_gpio_set, 16);
178 memory_region_init_io(&s->iomem, OBJECT(s), &scoop_ops, s, "scoop", 0x1000);
179
180 sysbus_init_mmio(sbd, &s->iomem);
181
182 return 0;
183}
184
185static int scoop_post_load(void *opaque, int version_id)
186{
187 ScoopInfo *s = (ScoopInfo *) opaque;
188 int i;
189 uint32_t level;
190
191 level = s->gpio_level & s->gpio_dir;
192
193 for (i = 0; i < 16; i++) {
194 qemu_set_irq(s->handler[i], (level >> i) & 1);
195 }
196
197 s->prev_level = level;
198
199 return 0;
200}
201
202static bool is_version_0 (void *opaque, int version_id)
203{
204 return version_id == 0;
205}
206
207static bool vmstate_scoop_validate(void *opaque, int version_id)
208{
209 ScoopInfo *s = opaque;
210
211 return !(s->prev_level & 0xffff0000) &&
212 !(s->gpio_level & 0xffff0000) &&
213 !(s->gpio_dir & 0xffff0000);
214}
215
216static const VMStateDescription vmstate_scoop_regs = {
217 .name = "scoop",
218 .version_id = 1,
219 .minimum_version_id = 0,
220 .post_load = scoop_post_load,
221 .fields = (VMStateField[]) {
222 VMSTATE_UINT16(status, ScoopInfo),
223 VMSTATE_UINT16(power, ScoopInfo),
224 VMSTATE_UINT32(gpio_level, ScoopInfo),
225 VMSTATE_UINT32(gpio_dir, ScoopInfo),
226 VMSTATE_UINT32(prev_level, ScoopInfo),
227 VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
228 VMSTATE_UINT16(mcr, ScoopInfo),
229 VMSTATE_UINT16(cdr, ScoopInfo),
230 VMSTATE_UINT16(ccr, ScoopInfo),
231 VMSTATE_UINT16(irr, ScoopInfo),
232 VMSTATE_UINT16(imr, ScoopInfo),
233 VMSTATE_UINT16(isr, ScoopInfo),
234 VMSTATE_UNUSED_TEST(is_version_0, 2),
235 VMSTATE_END_OF_LIST(),
236 },
237};
238
239static void scoop_sysbus_class_init(ObjectClass *klass, void *data)
240{
241 DeviceClass *dc = DEVICE_CLASS(klass);
242 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
243
244 k->init = scoop_init;
245 dc->desc = "Scoop2 Sharp custom ASIC";
246 dc->vmsd = &vmstate_scoop_regs;
247}
248
249static const TypeInfo scoop_sysbus_info = {
250 .name = TYPE_SCOOP,
251 .parent = TYPE_SYS_BUS_DEVICE,
252 .instance_size = sizeof(ScoopInfo),
253 .class_init = scoop_sysbus_class_init,
254};
255
256static void scoop_register_types(void)
257{
258 type_register_static(&scoop_sysbus_info);
259}
260
261type_init(scoop_register_types)
262
263
264
265#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
266
267static struct QEMU_PACKED sl_param_info {
268 uint32_t comadj_keyword;
269 int32_t comadj;
270
271 uint32_t uuid_keyword;
272 char uuid[16];
273
274 uint32_t touch_keyword;
275 int32_t touch_xp;
276 int32_t touch_yp;
277 int32_t touch_xd;
278 int32_t touch_yd;
279
280 uint32_t adadj_keyword;
281 int32_t adadj;
282
283 uint32_t phad_keyword;
284 int32_t phadadj;
285} zaurus_bootparam = {
286 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
287 .comadj = 125,
288 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
289 .uuid = { -1 },
290 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
291 .touch_xp = -1,
292 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
293 .adadj = -1,
294 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
295 .phadadj = 0x01,
296};
297
298void sl_bootparam_write(hwaddr ptr)
299{
300 cpu_physical_memory_write(ptr, &zaurus_bootparam,
301 sizeof(struct sl_param_info));
302}
303
