LXR qemu/hw/i386/pc

   1/*
   2 * Q35 chipset based pc system emulator
   3 *
   4 * Copyright (c) 2003-2004 Fabrice Bellard
   5 * Copyright (c) 2009, 2010
   6 *               Isaku Yamahata <yamahata at valinux co jp>
   7 *               VA Linux Systems Japan K.K.
   8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9 *
  10 * This is based on pc.c, but heavily modified.
  11 *
  12 * Permission is hereby granted, free of charge, to any person obtaining a copy
  13 * of this software and associated documentation files (the "Software"), to deal
  14 * in the Software without restriction, including without limitation the rights
  15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16 * copies of the Software, and to permit persons to whom the Software is
  17 * furnished to do so, subject to the following conditions:
  18 *
  19 * The above copyright notice and this permission notice shall be included in
  20 * all copies or substantial portions of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28 * THE SOFTWARE.
  29 */
  30#include "qemu/osdep.h"
  31#include "hw/hw.h"
  32#include "hw/loader.h"
  33#include "sysemu/arch_init.h"
  34#include "hw/i2c/smbus.h"
  35#include "hw/boards.h"
  36#include "hw/timer/mc146818rtc.h"
  37#include "hw/xen/xen.h"
  38#include "sysemu/kvm.h"
  39#include "hw/kvm/clock.h"
  40#include "hw/pci-host/q35.h"
  41#include "exec/address-spaces.h"
  42#include "hw/i386/pc.h"
  43#include "hw/i386/ich9.h"
  44#include "hw/smbios/smbios.h"
  45#include "hw/ide/pci.h"
  46#include "hw/ide/ahci.h"
  47#include "hw/usb.h"
  48#include "qemu/error-report.h"
  49#include "migration/migration.h"
  50
  51/* ICH9 AHCI has 6 ports */
  52#define MAX_SATA_PORTS     6
  53
  54/* PC hardware initialisation */
  55static void pc_q35_init(MachineState *machine)
  56{
  57    PCMachineState *pcms = PC_MACHINE(machine);
  58    PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
  59    Q35PCIHost *q35_host;
  60    PCIHostState *phb;
  61    PCIBus *host_bus;
  62    PCIDevice *lpc;
  63    BusState *idebus[MAX_SATA_PORTS];
  64    ISADevice *rtc_state;
  65    MemoryRegion *system_io = get_system_io();
  66    MemoryRegion *pci_memory;
  67    MemoryRegion *rom_memory;
  68    MemoryRegion *ram_memory;
  69    GSIState *gsi_state;
  70    ISABus *isa_bus;
  71    qemu_irq *gsi;
  72    qemu_irq *i8259;
  73    int i;
  74    ICH9LPCState *ich9_lpc;
  75    PCIDevice *ahci;
  76    ram_addr_t lowmem;
  77    DriveInfo *hd[MAX_SATA_PORTS];
  78    MachineClass *mc = MACHINE_GET_CLASS(machine);
  79
  80    /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  81     * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  82     * also known as MMCFG).
  83     * If it doesn't, we need to split it in chunks below and above 4G.
  84     * In any case, try to make sure that guest addresses aligned at
  85     * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  86     */
  87    if (machine->ram_size >= 0xb0000000) {
  88        lowmem = 0x80000000;
  89    } else {
  90        lowmem = 0xb0000000;
  91    }
  92
  93    /* Handle the machine opt max-ram-below-4g.  It is basically doing
  94     * min(qemu limit, user limit).
  95     */
  96    if (lowmem > pcms->max_ram_below_4g) {
  97        lowmem = pcms->max_ram_below_4g;
  98        if (machine->ram_size - lowmem > lowmem &&
  99            lowmem & ((1ULL << 30) - 1)) {
 100            error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
 101                         ") not a multiple of 1G; possible bad performance.",
 102                         pcms->max_ram_below_4g);
 103        }
 104    }
 105
 106    if (machine->ram_size >= lowmem) {
 107        pcms->above_4g_mem_size = machine->ram_size - lowmem;
 108        pcms->below_4g_mem_size = lowmem;
 109    } else {
 110        pcms->above_4g_mem_size = 0;
 111        pcms->below_4g_mem_size = machine->ram_size;
 112    }
 113
 114    if (xen_enabled()) {
 115        xen_hvm_init(pcms, &ram_memory);
 116    }
 117
 118    pc_cpus_init(pcms);
 119
 120    kvmclock_create();
 121
 122    /* pci enabled */
 123    if (pcmc->pci_enabled) {
 124        pci_memory = g_new(MemoryRegion, 1);
 125        memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 126        rom_memory = pci_memory;
 127    } else {
 128        pci_memory = NULL;
 129        rom_memory = get_system_memory();
 130    }
 131
 132    pc_guest_info_init(pcms);
 133
 134    if (pcmc->smbios_defaults) {
 135        /* These values are guest ABI, do not change */
 136        smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 137                            mc->name, pcmc->smbios_legacy_mode,
 138                            pcmc->smbios_uuid_encoded,
 139                            SMBIOS_ENTRY_POINT_21);
 140    }
 141
 142    /* allocate ram and load rom/bios */
 143    if (!xen_enabled()) {
 144        pc_memory_init(pcms, get_system_memory(),
 145                       rom_memory, &ram_memory);
 146    }
 147
 148    /* irq lines */
 149    gsi_state = g_malloc0(sizeof(*gsi_state));
 150    if (kvm_ioapic_in_kernel()) {
 151        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
 152        gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 153                                 GSI_NUM_PINS);
 154    } else {
 155        gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 156    }
 157
 158    /* create pci host bus */
 159    q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 160
 161    object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 162    q35_host->mch.ram_memory = ram_memory;
 163    q35_host->mch.pci_address_space = pci_memory;
 164    q35_host->mch.system_memory = get_system_memory();
 165    q35_host->mch.address_space_io = system_io;
 166    q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size;
 167    q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size;
 168    /* pci */
 169    qdev_init_nofail(DEVICE(q35_host));
 170    phb = PCI_HOST_BRIDGE(q35_host);
 171    host_bus = phb->bus;
 172    pcms->bus = phb->bus;
 173    /* create ISA bus */
 174    lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 175                                          ICH9_LPC_FUNC), true,
 176                                          TYPE_ICH9_LPC_DEVICE);
 177
 178    object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 179                             TYPE_HOTPLUG_HANDLER,
 180                             (Object **)&pcms->acpi_dev,
 181                             object_property_allow_set_link,
 182                             OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 183    object_property_set_link(OBJECT(machine), OBJECT(lpc),
 184                             PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 185
 186    ich9_lpc = ICH9_LPC_DEVICE(lpc);
 187    ich9_lpc->pic = gsi;
 188    ich9_lpc->ioapic = gsi_state->ioapic_irq;
 189    pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 190                 ICH9_LPC_NB_PIRQS);
 191    pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 192    isa_bus = ich9_lpc->isa_bus;
 193
 194    /*end early*/
 195    isa_bus_irqs(isa_bus, gsi);
 196
 197    if (kvm_pic_in_kernel()) {
 198        i8259 = kvm_i8259_init(isa_bus);
 199    } else if (xen_enabled()) {
 200        i8259 = xen_interrupt_controller_init();
 201    } else {
 202        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 203    }
 204
 205    for (i = 0; i < ISA_NUM_IRQS; i++) {
 206        gsi_state->i8259_irq[i] = i8259[i];
 207    }
 208    if (pcmc->pci_enabled) {
 209        ioapic_init_gsi(gsi_state, "q35");
 210    }
 211
 212    pc_register_ferr_irq(gsi[13]);
 213
 214    assert(pcms->vmport != ON_OFF_AUTO__MAX);
 215    if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 216        pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 217    }
 218
 219    /* init basic PC hardware */
 220    pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy,
 221                         (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104);
 222
 223    /* connect pm stuff to lpc */
 224    ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
 225
 226    /* ahci and SATA device, for q35 1 ahci controller is built-in */
 227    ahci = pci_create_simple_multifunction(host_bus,
 228                                           PCI_DEVFN(ICH9_SATA1_DEV,
 229                                                     ICH9_SATA1_FUNC),
 230                                           true, "ich9-ahci");
 231    idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 232    idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 233    g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
 234    ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
 235    ahci_ide_create_devs(ahci, hd);
 236
 237    if (usb_enabled()) {
 238        /* Should we create 6 UHCI according to ich9 spec? */
 239        ehci_create_ich9_with_companions(host_bus, 0x1d);
 240    }
 241
 242    /* TODO: Populate SPD eeprom data.  */
 243    smbus_eeprom_init(ich9_smb_init(host_bus,
 244                                    PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 245                                    0xb100),
 246                      8, NULL, 0);
 247
 248    pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 249
 250    /* the rest devices to which pci devfn is automatically assigned */
 251    pc_vga_init(isa_bus, host_bus);
 252    pc_nic_init(isa_bus, host_bus);
 253    if (pcmc->pci_enabled) {
 254        pc_pci_device_init(host_bus);
 255    }
 256
 257    if (pcms->acpi_nvdimm_state.is_enabled) {
 258        nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io,
 259                               pcms->fw_cfg, OBJECT(pcms));
 260    }
 261}
 262
 263#define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 264    static void pc_init_##suffix(MachineState *machine) \
 265    { \
 266        void (*compat)(MachineState *m) = (compatfn); \
 267        if (compat) { \
 268            compat(machine); \
 269        } \
 270        pc_q35_init(machine); \
 271    } \
 272    DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 273
 274
 275static void pc_q35_machine_options(MachineClass *m)
 276{
 277    m->family = "pc_q35";
 278    m->desc = "Standard PC (Q35 + ICH9, 2009)";
 279    m->hot_add_cpu = pc_hot_add_cpu;
 280    m->units_per_default_bus = 1;
 281    m->default_machine_opts = "firmware=bios-256k.bin";
 282    m->default_display = "std";
 283    m->no_floppy = 1;
 284}
 285
 286static void pc_q35_2_6_machine_options(MachineClass *m)
 287{
 288    pc_q35_machine_options(m);
 289    m->alias = "q35";
 290}
 291
 292DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 293                   pc_q35_2_6_machine_options);
 294
 295static void pc_q35_2_5_machine_options(MachineClass *m)
 296{
 297    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 298    pc_q35_2_6_machine_options(m);
 299    m->alias = NULL;
 300    pcmc->save_tsc_khz = false;
 301    m->legacy_fw_cfg_order = 1;
 302    SET_MACHINE_COMPAT(m, PC_COMPAT_2_5);
 303}
 304
 305DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 306                   pc_q35_2_5_machine_options);
 307
 308static void pc_q35_2_4_machine_options(MachineClass *m)
 309{
 310    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 311    pc_q35_2_5_machine_options(m);
 312    m->hw_version = "2.4.0";
 313    pcmc->broken_reserved_end = true;
 314    SET_MACHINE_COMPAT(m, PC_COMPAT_2_4);
 315}
 316
 317DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 318                   pc_q35_2_4_machine_options);
 319