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63#include "qemu/osdep.h"
64#include <hw/hw.h>
65#include <hw/pci/msi.h>
66#include <hw/i386/pc.h>
67#include <hw/pci/pci.h>
68#include <hw/isa/isa.h>
69#include "sysemu/block-backend.h"
70#include "sysemu/dma.h"
71
72#include <hw/ide/pci.h>
73#include <hw/ide/ahci.h>
74
75#define ICH9_MSI_CAP_OFFSET 0x80
76#define ICH9_SATA_CAP_OFFSET 0xA8
77
78#define ICH9_IDP_BAR 4
79#define ICH9_MEM_BAR 5
80
81#define ICH9_IDP_INDEX 0x10
82#define ICH9_IDP_INDEX_LOG2 0x04
83
84static const VMStateDescription vmstate_ich9_ahci = {
85 .name = "ich9_ahci",
86 .version_id = 1,
87 .fields = (VMStateField[]) {
88 VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
89 VMSTATE_AHCI(ahci, AHCIPCIState),
90 VMSTATE_END_OF_LIST()
91 },
92};
93
94static void pci_ich9_reset(DeviceState *dev)
95{
96 AHCIPCIState *d = ICH_AHCI(dev);
97
98 ahci_reset(&d->ahci);
99}
100
101static void pci_ich9_ahci_init(Object *obj)
102{
103 struct AHCIPCIState *d = ICH_AHCI(obj);
104
105 ahci_init(&d->ahci, DEVICE(obj));
106}
107
108static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
109{
110 struct AHCIPCIState *d;
111 int sata_cap_offset;
112 uint8_t *sata_cap;
113 d = ICH_AHCI(dev);
114
115 ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
116
117 pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
118
119 dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
120 dev->config[PCI_LATENCY_TIMER] = 0x00;
121 pci_config_set_interrupt_pin(dev->config, 1);
122
123
124 dev->config[0x90] = 1 << 6;
125
126 d->ahci.irq = pci_allocate_irq(dev);
127
128 pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
129 &d->ahci.idp);
130 pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
131 &d->ahci.mem);
132
133 sata_cap_offset = pci_add_capability2(dev, PCI_CAP_ID_SATA,
134 ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE,
135 errp);
136 if (sata_cap_offset < 0) {
137 return;
138 }
139
140 sata_cap = dev->config + sata_cap_offset;
141 pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
142 pci_set_long(sata_cap + SATA_CAP_BAR,
143 (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
144 d->ahci.idp_offset = ICH9_IDP_INDEX;
145
146
147
148
149 msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false);
150}
151
152static void pci_ich9_uninit(PCIDevice *dev)
153{
154 struct AHCIPCIState *d;
155 d = ICH_AHCI(dev);
156
157 msi_uninit(dev);
158 ahci_uninit(&d->ahci);
159 qemu_free_irq(d->ahci.irq);
160}
161
162static void ich_ahci_class_init(ObjectClass *klass, void *data)
163{
164 DeviceClass *dc = DEVICE_CLASS(klass);
165 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
166
167 k->realize = pci_ich9_ahci_realize;
168 k->exit = pci_ich9_uninit;
169 k->vendor_id = PCI_VENDOR_ID_INTEL;
170 k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
171 k->revision = 0x02;
172 k->class_id = PCI_CLASS_STORAGE_SATA;
173 dc->vmsd = &vmstate_ich9_ahci;
174 dc->reset = pci_ich9_reset;
175 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
176}
177
178static const TypeInfo ich_ahci_info = {
179 .name = TYPE_ICH9_AHCI,
180 .parent = TYPE_PCI_DEVICE,
181 .instance_size = sizeof(AHCIPCIState),
182 .instance_init = pci_ich9_ahci_init,
183 .class_init = ich_ahci_class_init,
184};
185
186static void ich_ahci_register_types(void)
187{
188 type_register_static(&ich_ahci_info);
189}
190
191type_init(ich_ahci_register_types)
192
