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23#include "qemu/osdep.h"
24#include "qapi/error.h"
25#include "hw/intc/arm_gicv3_common.h"
26
27static void gicv3_pre_save(void *opaque)
28{
29 GICv3State *s = (GICv3State *)opaque;
30 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
31
32 if (c->pre_save) {
33 c->pre_save(s);
34 }
35}
36
37static int gicv3_post_load(void *opaque, int version_id)
38{
39 GICv3State *s = (GICv3State *)opaque;
40 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
41
42 if (c->post_load) {
43 c->post_load(s);
44 }
45 return 0;
46}
47
48static const VMStateDescription vmstate_gicv3 = {
49 .name = "arm_gicv3",
50 .unmigratable = 1,
51 .pre_save = gicv3_pre_save,
52 .post_load = gicv3_post_load,
53};
54
55void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
56 const MemoryRegionOps *ops)
57{
58 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
59 int i;
60
61
62
63
64
65
66
67
68 i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
69 qdev_init_gpio_in(DEVICE(s), handler, i);
70
71 s->parent_irq = g_malloc(s->num_cpu * sizeof(qemu_irq));
72 s->parent_fiq = g_malloc(s->num_cpu * sizeof(qemu_irq));
73
74 for (i = 0; i < s->num_cpu; i++) {
75 sysbus_init_irq(sbd, &s->parent_irq[i]);
76 }
77 for (i = 0; i < s->num_cpu; i++) {
78 sysbus_init_irq(sbd, &s->parent_fiq[i]);
79 }
80
81 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
82 "gicv3_dist", 0x10000);
83 memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
84 "gicv3_redist", 0x20000 * s->num_cpu);
85
86 sysbus_init_mmio(sbd, &s->iomem_dist);
87 sysbus_init_mmio(sbd, &s->iomem_redist);
88}
89
90static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
91{
92 GICv3State *s = ARM_GICV3_COMMON(dev);
93
94
95
96
97
98
99 if (s->revision != 3) {
100 error_setg(errp, "unsupported GIC revision %d", s->revision);
101 return;
102 }
103}
104
105static void arm_gicv3_common_reset(DeviceState *dev)
106{
107
108}
109
110static Property arm_gicv3_common_properties[] = {
111 DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
112 DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
113 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
114 DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
115 DEFINE_PROP_END_OF_LIST(),
116};
117
118static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
119{
120 DeviceClass *dc = DEVICE_CLASS(klass);
121
122 dc->reset = arm_gicv3_common_reset;
123 dc->realize = arm_gicv3_common_realize;
124 dc->props = arm_gicv3_common_properties;
125 dc->vmsd = &vmstate_gicv3;
126}
127
128static const TypeInfo arm_gicv3_common_type = {
129 .name = TYPE_ARM_GICV3_COMMON,
130 .parent = TYPE_SYS_BUS_DEVICE,
131 .instance_size = sizeof(GICv3State),
132 .class_size = sizeof(ARMGICv3CommonClass),
133 .class_init = arm_gicv3_common_class_init,
134 .abstract = true,
135};
136
137static void register_types(void)
138{
139 type_register_static(&arm_gicv3_common_type);
140}
141
142type_init(register_types)
143