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23#include "qemu/osdep.h"
24#include "monitor/monitor.h"
25#include "hw/hw.h"
26#include "hw/i386/pc.h"
27#include "hw/i386/ioapic.h"
28#include "hw/i386/ioapic_internal.h"
29#include "include/hw/pci/msi.h"
30#include "sysemu/kvm.h"
31
32
33
34#ifdef DEBUG_IOAPIC
35#define DPRINTF(fmt, ...) \
36 do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
37#else
38#define DPRINTF(fmt, ...)
39#endif
40
41#define APIC_DELIVERY_MODE_SHIFT 8
42#define APIC_POLARITY_SHIFT 14
43#define APIC_TRIG_MODE_SHIFT 15
44
45static IOAPICCommonState *ioapics[MAX_IOAPICS];
46
47
48extern int ioapic_no;
49
50static void ioapic_service(IOAPICCommonState *s)
51{
52 uint8_t i;
53 uint8_t trig_mode;
54 uint8_t vector;
55 uint8_t delivery_mode;
56 uint32_t mask;
57 uint64_t entry;
58 uint8_t dest;
59 uint8_t dest_mode;
60
61 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
62 mask = 1 << i;
63 if (s->irr & mask) {
64 int coalesce = 0;
65
66 entry = s->ioredtbl[i];
67 if (!(entry & IOAPIC_LVT_MASKED)) {
68 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
69 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
70 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
71 delivery_mode =
72 (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
73 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
74 s->irr &= ~mask;
75 } else {
76 coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
77 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
78 }
79 if (delivery_mode == IOAPIC_DM_EXTINT) {
80 vector = pic_read_irq(isa_pic);
81 } else {
82 vector = entry & IOAPIC_VECTOR_MASK;
83 }
84#ifdef CONFIG_KVM
85 if (kvm_irqchip_is_split()) {
86 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
87 kvm_set_irq(kvm_state, i, 1);
88 kvm_set_irq(kvm_state, i, 0);
89 } else {
90 if (!coalesce) {
91 kvm_set_irq(kvm_state, i, 1);
92 }
93 }
94 continue;
95 }
96#else
97 (void)coalesce;
98#endif
99 apic_deliver_irq(dest, dest_mode, delivery_mode, vector,
100 trig_mode);
101 }
102 }
103 }
104}
105
106static void ioapic_set_irq(void *opaque, int vector, int level)
107{
108 IOAPICCommonState *s = opaque;
109
110
111
112
113
114 DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
115 if (vector == 0) {
116 vector = 2;
117 }
118 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
119 uint32_t mask = 1 << vector;
120 uint64_t entry = s->ioredtbl[vector];
121
122 if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
123 IOAPIC_TRIGGER_LEVEL) {
124
125 if (level) {
126 s->irr |= mask;
127 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
128 ioapic_service(s);
129 }
130 } else {
131 s->irr &= ~mask;
132 }
133 } else {
134
135
136 if (level && !(entry & IOAPIC_LVT_MASKED)) {
137 s->irr |= mask;
138 ioapic_service(s);
139 }
140 }
141 }
142}
143
144static void ioapic_update_kvm_routes(IOAPICCommonState *s)
145{
146#ifdef CONFIG_KVM
147 int i;
148
149 if (kvm_irqchip_is_split()) {
150 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
151 uint64_t entry = s->ioredtbl[i];
152 uint8_t trig_mode;
153 uint8_t delivery_mode;
154 uint8_t dest;
155 uint8_t dest_mode;
156 uint64_t pin_polarity;
157 MSIMessage msg;
158
159 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
160 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
161 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
162 pin_polarity = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
163 delivery_mode =
164 (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
165
166 msg.address = APIC_DEFAULT_ADDRESS;
167 msg.address |= dest_mode << 2;
168 msg.address |= dest << 12;
169
170 msg.data = entry & IOAPIC_VECTOR_MASK;
171 msg.data |= delivery_mode << APIC_DELIVERY_MODE_SHIFT;
172 msg.data |= pin_polarity << APIC_POLARITY_SHIFT;
173 msg.data |= trig_mode << APIC_TRIG_MODE_SHIFT;
174
175 kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
176 }
177 kvm_irqchip_commit_routes(kvm_state);
178 }
179#endif
180}
181
182void ioapic_eoi_broadcast(int vector)
183{
184 IOAPICCommonState *s;
185 uint64_t entry;
186 int i, n;
187
188 for (i = 0; i < MAX_IOAPICS; i++) {
189 s = ioapics[i];
190 if (!s) {
191 continue;
192 }
193 for (n = 0; n < IOAPIC_NUM_PINS; n++) {
194 entry = s->ioredtbl[n];
195 if ((entry & IOAPIC_LVT_REMOTE_IRR)
196 && (entry & IOAPIC_VECTOR_MASK) == vector) {
197 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
198 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
199 ioapic_service(s);
200 }
201 }
202 }
203 }
204}
205
206void ioapic_dump_state(Monitor *mon, const QDict *qdict)
207{
208 int i;
209
210 for (i = 0; i < MAX_IOAPICS; i++) {
211 if (ioapics[i] != 0) {
212 ioapic_print_redtbl(mon, ioapics[i]);
213 }
214 }
215}
216
217static uint64_t
218ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
219{
220 IOAPICCommonState *s = opaque;
221 int index;
222 uint32_t val = 0;
223
224 switch (addr & 0xff) {
225 case IOAPIC_IOREGSEL:
226 val = s->ioregsel;
227 break;
228 case IOAPIC_IOWIN:
229 if (size != 4) {
230 break;
231 }
232 switch (s->ioregsel) {
233 case IOAPIC_REG_ID:
234 case IOAPIC_REG_ARB:
235 val = s->id << IOAPIC_ID_SHIFT;
236 break;
237 case IOAPIC_REG_VER:
238 val = IOAPIC_VERSION |
239 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
240 break;
241 default:
242 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
243 if (index >= 0 && index < IOAPIC_NUM_PINS) {
244 if (s->ioregsel & 1) {
245 val = s->ioredtbl[index] >> 32;
246 } else {
247 val = s->ioredtbl[index] & 0xffffffff;
248 }
249 }
250 }
251 DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
252 break;
253 }
254 return val;
255}
256
257static void
258ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
259 unsigned int size)
260{
261 IOAPICCommonState *s = opaque;
262 int index;
263
264 switch (addr & 0xff) {
265 case IOAPIC_IOREGSEL:
266 s->ioregsel = val;
267 break;
268 case IOAPIC_IOWIN:
269 if (size != 4) {
270 break;
271 }
272 DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
273 switch (s->ioregsel) {
274 case IOAPIC_REG_ID:
275 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
276 break;
277 case IOAPIC_REG_VER:
278 case IOAPIC_REG_ARB:
279 break;
280 default:
281 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
282 if (index >= 0 && index < IOAPIC_NUM_PINS) {
283 if (s->ioregsel & 1) {
284 s->ioredtbl[index] &= 0xffffffff;
285 s->ioredtbl[index] |= (uint64_t)val << 32;
286 } else {
287 s->ioredtbl[index] &= ~0xffffffffULL;
288 s->ioredtbl[index] |= val;
289 }
290 ioapic_service(s);
291 }
292 }
293 break;
294 }
295
296 ioapic_update_kvm_routes(s);
297}
298
299static const MemoryRegionOps ioapic_io_ops = {
300 .read = ioapic_mem_read,
301 .write = ioapic_mem_write,
302 .endianness = DEVICE_NATIVE_ENDIAN,
303};
304
305static void ioapic_realize(DeviceState *dev, Error **errp)
306{
307 IOAPICCommonState *s = IOAPIC_COMMON(dev);
308
309 memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
310 "ioapic", 0x1000);
311
312 qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
313
314 ioapics[ioapic_no] = s;
315}
316
317static void ioapic_class_init(ObjectClass *klass, void *data)
318{
319 IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
320 DeviceClass *dc = DEVICE_CLASS(klass);
321
322 k->realize = ioapic_realize;
323 dc->reset = ioapic_reset_common;
324}
325
326static const TypeInfo ioapic_info = {
327 .name = "ioapic",
328 .parent = TYPE_IOAPIC_COMMON,
329 .instance_size = sizeof(IOAPICCommonState),
330 .class_init = ioapic_class_init,
331};
332
333static void ioapic_register_types(void)
334{
335 type_register_static(&ioapic_info);
336}
337
338type_init(ioapic_register_types)
339
