LXR qemu/hw/lm32/lm32

   1/*
   2 *  LatticeMico32 hwsetup helper functions.
   3 *
   4 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20/*
  21 * These are helper functions for creating the hardware description blob used
  22 * in the Theobroma's uClinux port.
  23 */
  24
  25#ifndef QEMU_HW_LM32_HWSETUP_H
  26#define QEMU_HW_LM32_HWSETUP_H
  27
  28#include "qemu-common.h"
  29#include "qemu/cutils.h"
  30#include "hw/loader.h"
  31
  32typedef struct {
  33    void *data;
  34    void *ptr;
  35} HWSetup;
  36
  37enum hwsetup_tag {
  38    HWSETUP_TAG_EOL         = 0,
  39    HWSETUP_TAG_CPU         = 1,
  40    HWSETUP_TAG_ASRAM       = 2,
  41    HWSETUP_TAG_FLASH       = 3,
  42    HWSETUP_TAG_SDRAM       = 4,
  43    HWSETUP_TAG_OCM         = 5,
  44    HWSETUP_TAG_DDR_SDRAM   = 6,
  45    HWSETUP_TAG_DDR2_SDRAM  = 7,
  46    HWSETUP_TAG_TIMER       = 8,
  47    HWSETUP_TAG_UART        = 9,
  48    HWSETUP_TAG_GPIO        = 10,
  49    HWSETUP_TAG_TRISPEEDMAC = 11,
  50    HWSETUP_TAG_I2CM        = 12,
  51    HWSETUP_TAG_LEDS        = 13,
  52    HWSETUP_TAG_7SEG        = 14,
  53    HWSETUP_TAG_SPI_S       = 15,
  54    HWSETUP_TAG_SPI_M       = 16,
  55};
  56
  57static inline HWSetup *hwsetup_init(void)
  58{
  59    HWSetup *hw;
  60
  61    hw = g_malloc(sizeof(HWSetup));
  62    hw->data = g_malloc0(TARGET_PAGE_SIZE);
  63    hw->ptr = hw->data;
  64
  65    return hw;
  66}
  67
  68static inline void hwsetup_free(HWSetup *hw)
  69{
  70    g_free(hw->data);
  71    g_free(hw);
  72}
  73
  74static inline void hwsetup_create_rom(HWSetup *hw,
  75        hwaddr base)
  76{
  77    rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE,
  78                 TARGET_PAGE_SIZE, base, NULL, NULL, NULL);
  79}
  80
  81static inline void hwsetup_add_u8(HWSetup *hw, uint8_t u)
  82{
  83    stb_p(hw->ptr, u);
  84    hw->ptr += 1;
  85}
  86
  87static inline void hwsetup_add_u32(HWSetup *hw, uint32_t u)
  88{
  89    stl_p(hw->ptr, u);
  90    hw->ptr += 4;
  91}
  92
  93static inline void hwsetup_add_tag(HWSetup *hw, enum hwsetup_tag t)
  94{
  95    stl_p(hw->ptr, t);
  96    hw->ptr += 4;
  97}
  98
  99static inline void hwsetup_add_str(HWSetup *hw, const char *str)
 100{
 101    pstrcpy(hw->ptr, 32, str);
 102    hw->ptr += 32;
 103}
 104
 105static inline void hwsetup_add_trailer(HWSetup *hw)
 106{
 107    hwsetup_add_u32(hw, 8); /* size */
 108    hwsetup_add_tag(hw, HWSETUP_TAG_EOL);
 109}
 110
 111static inline void hwsetup_add_cpu(HWSetup *hw,
 112        const char *name, uint32_t frequency)
 113{
 114    hwsetup_add_u32(hw, 44); /* size */
 115    hwsetup_add_tag(hw, HWSETUP_TAG_CPU);
 116    hwsetup_add_str(hw, name);
 117    hwsetup_add_u32(hw, frequency);
 118}
 119
 120static inline void hwsetup_add_flash(HWSetup *hw,
 121        const char *name, uint32_t base, uint32_t size)
 122{
 123    hwsetup_add_u32(hw, 52); /* size */
 124    hwsetup_add_tag(hw, HWSETUP_TAG_FLASH);
 125    hwsetup_add_str(hw, name);
 126    hwsetup_add_u32(hw, base);
 127    hwsetup_add_u32(hw, size);
 128    hwsetup_add_u8(hw, 8); /* read latency */
 129    hwsetup_add_u8(hw, 8); /* write latency */
 130    hwsetup_add_u8(hw, 25); /* address width */
 131    hwsetup_add_u8(hw, 32); /* data width */
 132}
 133
 134static inline void hwsetup_add_ddr_sdram(HWSetup *hw,
 135        const char *name, uint32_t base, uint32_t size)
 136{
 137    hwsetup_add_u32(hw, 48); /* size */
 138    hwsetup_add_tag(hw, HWSETUP_TAG_DDR_SDRAM);
 139    hwsetup_add_str(hw, name);
 140    hwsetup_add_u32(hw, base);
 141    hwsetup_add_u32(hw, size);
 142}
 143
 144static inline void hwsetup_add_timer(HWSetup *hw,
 145        const char *name, uint32_t base, uint32_t irq)
 146{
 147    hwsetup_add_u32(hw, 56); /* size */
 148    hwsetup_add_tag(hw, HWSETUP_TAG_TIMER);
 149    hwsetup_add_str(hw, name);
 150    hwsetup_add_u32(hw, base);
 151    hwsetup_add_u8(hw, 1); /* wr_tickcount */
 152    hwsetup_add_u8(hw, 1); /* rd_tickcount */
 153    hwsetup_add_u8(hw, 1); /* start_stop_control */
 154    hwsetup_add_u8(hw, 32); /* counter_width */
 155    hwsetup_add_u32(hw, 20); /* reload_ticks */
 156    hwsetup_add_u8(hw, irq);
 157    hwsetup_add_u8(hw, 0); /* padding */
 158    hwsetup_add_u8(hw, 0); /* padding */
 159    hwsetup_add_u8(hw, 0); /* padding */
 160}
 161
 162static inline void hwsetup_add_uart(HWSetup *hw,
 163        const char *name, uint32_t base, uint32_t irq)
 164{
 165    hwsetup_add_u32(hw, 56); /* size */
 166    hwsetup_add_tag(hw, HWSETUP_TAG_UART);
 167    hwsetup_add_str(hw, name);
 168    hwsetup_add_u32(hw, base);
 169    hwsetup_add_u32(hw, 115200); /* baudrate */
 170    hwsetup_add_u8(hw, 8); /* databits */
 171    hwsetup_add_u8(hw, 1); /* stopbits */
 172    hwsetup_add_u8(hw, 1); /* use_interrupt */
 173    hwsetup_add_u8(hw, 1); /* block_on_transmit */
 174    hwsetup_add_u8(hw, 1); /* block_on_receive */
 175    hwsetup_add_u8(hw, 4); /* rx_buffer_size */
 176    hwsetup_add_u8(hw, 4); /* tx_buffer_size */
 177    hwsetup_add_u8(hw, irq);
 178}
 179
 180#endif /* QEMU_HW_LM32_HWSETUP_H */
 181