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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33#include "qapi/error.h"
34#include "hw/fdt_generic_util.h"
35
36#ifndef ARM_CCI400_ERR_DEBUG
37#define ARM_CCI400_ERR_DEBUG 0
38#endif
39
40#define TYPE_ARM_CCI400 "arm,cci-400"
41
42#define ARM_CCI400(obj) \
43 OBJECT_CHECK(CCI, (obj), TYPE_ARM_CCI400)
44
45REG32(CONTROL_OVERRIDE_REGISTER, 0x0)
46 FIELD(CONTROL_OVERRIDE_REGISTER, DISABLE_RETRY_REDUCTION_BUFFERS, 1, 5)
47 FIELD(CONTROL_OVERRIDE_REGISTER, DISABLE_PRIORITY_PROMOTION, 1, 4)
48 FIELD(CONTROL_OVERRIDE_REGISTER, TERMINATE_BARRIERS, 1, 3)
49 FIELD(CONTROL_OVERRIDE_REGISTER, DISABLE_SPECULATIVE_FETCHES, 1, 2)
50 FIELD(CONTROL_OVERRIDE_REGISTER, DVM_MESSAGE_DISABLE, 1, 1)
51 FIELD(CONTROL_OVERRIDE_REGISTER, SNOOP_DISABLE, 1, 0)
52REG32(SPECULATION_CONTROL_REGISTER, 0x4)
53 FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S4, 1, 20)
54 FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S3, 1, 19)
55 FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S2, 1, 18)
56 FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S1, 1, 17)
57 FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S0, 1, 16)
58 FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_M2, 1, 2)
59 FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_M1, 1, 1)
60 FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_M0, 1, 0)
61REG32(SECURE_ACCESS_REGISTER, 0x8)
62 FIELD(SECURE_ACCESS_REGISTER, SECURE_ACCESS_CONTROL, 1, 0)
63REG32(STATUS_REGISTER, 0xc)
64 FIELD(STATUS_REGISTER, CCI_STATUS, 1, 0)
65REG32(IMPRECISE_ERROR_REGISTER, 0x10)
66 FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S4, 1, 20)
67 FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S3, 1, 19)
68 FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S2, 1, 18)
69 FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S1, 1, 17)
70 FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S0, 1, 16)
71 FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_M2, 1, 2)
72 FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_M1, 1, 1)
73 FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_M0, 1, 0)
74REG32(PERFORMANCE_MONITOR_CONTROL_REGISTER, 0x100)
75 FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, PMU_COUNT_NUM, 5, 11)
76 FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, DP, 1, 5)
77 FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, EX, 1, 4)
78 FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, CCD, 1, 3)
79 FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, CCR, 1, 2)
80 FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, RST, 1, 1)
81 FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, CEN, 1, 0)
82REG32(PERIPHERAL_ID4, 0xfd0)
83 FIELD(PERIPHERAL_ID4, PERIPH_ID_4, 8, 0)
84REG32(PERIPHERAL_ID5, 0xfd4)
85 FIELD(PERIPHERAL_ID5, PERIPH_ID_5, 8, 0)
86REG32(PERIPHERAL_ID6, 0xfd8)
87 FIELD(PERIPHERAL_ID6, PERIPH_ID_6, 8, 0)
88REG32(PERIPHERAL_ID7, 0xfdc)
89 FIELD(PERIPHERAL_ID7, PERIPH_ID_7, 8, 0)
90REG32(PERIPHERAL_ID0, 0xfe0)
91 FIELD(PERIPHERAL_ID0, PERIPHERAL_ID0, 8, 0)
92REG32(PERIPHERAL_ID1, 0xfe4)
93 FIELD(PERIPHERAL_ID1, PERIPHERAL_ID1, 8, 0)
94REG32(PERIPHERAL_ID2, 0xfe8)
95 FIELD(PERIPHERAL_ID2, PERIPH_ID_2, 8, 0)
96REG32(PERIPHERAL_ID3, 0xfec)
97 FIELD(PERIPHERAL_ID3, REV_AND, 4, 4)
98 FIELD(PERIPHERAL_ID3, CUST_MOD_NUM, 4, 0)
99REG32(COMPONENT_ID0, 0xff0)
100 FIELD(COMPONENT_ID0, COMPONENT_ID0, 8, 0)
101REG32(COMPONENT_ID1, 0xff4)
102 FIELD(COMPONENT_ID1, COMPONENT_ID1, 8, 0)
103REG32(COMPONENT_ID2, 0xff8)
104 FIELD(COMPONENT_ID2, COMPONENT_ID2, 8, 0)
105REG32(COMPONENT_ID3, 0xffc)
106 FIELD(COMPONENT_ID3, COMPONENT_ID3, 8, 0)
107REG32(SNOOP_CONTROL_REGISTER_S0, 0x1000)
108 FIELD(SNOOP_CONTROL_REGISTER_S0, SUPPORT_DVMS, 1, 31)
109 FIELD(SNOOP_CONTROL_REGISTER_S0, SUPPORT_SNOOPS, 1, 30)
110 FIELD(SNOOP_CONTROL_REGISTER_S0, ENABLE_DVMS, 1, 1)
111REG32(SHAREABLE_OVERRIDE_REGISTER_S0, 0x1004)
112 FIELD(SHAREABLE_OVERRIDE_REGISTER_S0, AXDOMAIN_OVERRIDE, 2, 0)
113REG32(READ_QOS_OVERRIDE_REGISTER_S0, 0x1100)
114 FIELD(READ_QOS_OVERRIDE_REGISTER_S0, ARQOS_OVERRIDE_READBACK, 4, 8)
115 FIELD(READ_QOS_OVERRIDE_REGISTER_S0, ARQOS_VALUE, 4, 0)
116REG32(WRITE_QOS_OVERRIDE_REGISTER_S0, 0x1104)
117 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S0, AWQOS_OVERRIDE_READBACK, 4, 8)
118 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S0, AWQOS_VALUE, 4, 0)
119REG32(QOS_CONTROL_REGISTER_S0, 0x110c)
120 FIELD(QOS_CONTROL_REGISTER_S0, QOS_REGULATION_DISABLED, 1, 31)
121 FIELD(QOS_CONTROL_REGISTER_S0, BANDWIDTH_REGULATION_MODE, 1, 21)
122 FIELD(QOS_CONTROL_REGISTER_S0, ARQOS_REGULATION_MODE, 1, 20)
123 FIELD(QOS_CONTROL_REGISTER_S0, AWQOS_REGULATION_MODE, 1, 16)
124 FIELD(QOS_CONTROL_REGISTER_S0, AR_OT_REGULATION, 1, 3)
125 FIELD(QOS_CONTROL_REGISTER_S0, AW_OT_REGULATION, 1, 2)
126 FIELD(QOS_CONTROL_REGISTER_S0, ARQOS_REGULATION, 1, 1)
127 FIELD(QOS_CONTROL_REGISTER_S0, AWQOS_REGULATION, 1, 0)
128REG32(MAX_OT_REGISTER_S0, 0x1110)
129 FIELD(MAX_OT_REGISTER_S0, INT_OT_AR, 6, 24)
130 FIELD(MAX_OT_REGISTER_S0, FRAC_OT_AR, 8, 16)
131 FIELD(MAX_OT_REGISTER_S0, INT_OT_AW, 6, 8)
132 FIELD(MAX_OT_REGISTER_S0, FRAC_OT_AW, 8, 0)
133REG32(TARGET_LATENCY_REGISTER_S0, 0x1130)
134 FIELD(TARGET_LATENCY_REGISTER_S0, AR_LAT, 12, 16)
135 FIELD(TARGET_LATENCY_REGISTER_S0, AW_LAT, 12, 0)
136REG32(LATENCY_REGULATION_REGISTER_S0, 0x1134)
137 FIELD(LATENCY_REGULATION_REGISTER_S0, AR_SCALE_FACT, 3, 8)
138 FIELD(LATENCY_REGULATION_REGISTER_S0, AW_SCALE_FACT, 3, 0)
139REG32(QOS_RANGE_REGISTER_S0, 0x1138)
140 FIELD(QOS_RANGE_REGISTER_S0, MAX_ARQOS, 4, 24)
141 FIELD(QOS_RANGE_REGISTER_S0, MIN_ARQOS, 4, 16)
142 FIELD(QOS_RANGE_REGISTER_S0, MAX_AWQOS, 4, 8)
143 FIELD(QOS_RANGE_REGISTER_S0, MIN_AWQOS, 4, 0)
144REG32(SNOOP_CONTROL_REGISTER_S1, 0x2000)
145 FIELD(SNOOP_CONTROL_REGISTER_S1, SUPPORT_DVMS, 1, 31)
146 FIELD(SNOOP_CONTROL_REGISTER_S1, SUPPORT_SNOOPS, 1, 30)
147 FIELD(SNOOP_CONTROL_REGISTER_S1, ENABLE_DVMS, 1, 1)
148REG32(SHAREABLE_OVERRIDE_REGISTER_S1, 0x2004)
149 FIELD(SHAREABLE_OVERRIDE_REGISTER_S1, AXDOMAIN_OVERRIDE, 2, 0)
150REG32(READ_QOS_OVERRIDE_REGISTER_S1, 0x2100)
151 FIELD(READ_QOS_OVERRIDE_REGISTER_S1, ARQOS_OVERRIDE_READBACK, 4, 8)
152 FIELD(READ_QOS_OVERRIDE_REGISTER_S1, ARQOS_VALUE, 4, 0)
153REG32(WRITE_QOS_OVERRIDE_REGISTER_S1, 0x2104)
154 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S1, AWQOS_OVERRIDE_READBACK, 4, 8)
155 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S1, AWQOS_VALUE, 4, 0)
156REG32(QOS_CONTROL_REGISTER_S1, 0x210c)
157 FIELD(QOS_CONTROL_REGISTER_S1, QOS_REGULATION_DISABLED, 1, 31)
158 FIELD(QOS_CONTROL_REGISTER_S1, BANDWIDTH_REGULATION_MODE, 1, 21)
159 FIELD(QOS_CONTROL_REGISTER_S1, ARQOS_REGULATION_MODE, 1, 20)
160 FIELD(QOS_CONTROL_REGISTER_S1, AWQOS_REGULATION_MODE, 1, 16)
161 FIELD(QOS_CONTROL_REGISTER_S1, AR_OT_REGULATION, 1, 3)
162 FIELD(QOS_CONTROL_REGISTER_S1, AW_OT_REGULATION, 1, 2)
163 FIELD(QOS_CONTROL_REGISTER_S1, ARQOS_REGULATION, 1, 1)
164 FIELD(QOS_CONTROL_REGISTER_S1, AWQOS_REGULATION, 1, 0)
165REG32(MAX_OT_REGISTER_S1, 0x2110)
166 FIELD(MAX_OT_REGISTER_S1, INT_OT_AR, 6, 24)
167 FIELD(MAX_OT_REGISTER_S1, FRAC_OT_AR, 8, 16)
168 FIELD(MAX_OT_REGISTER_S1, INT_OT_AW, 6, 8)
169 FIELD(MAX_OT_REGISTER_S1, FRAC_OT_AW, 8, 0)
170REG32(TARGET_LATENCY_REGISTER_S1, 0x2130)
171 FIELD(TARGET_LATENCY_REGISTER_S1, AR_LAT, 12, 16)
172 FIELD(TARGET_LATENCY_REGISTER_S1, AW_LAT, 12, 0)
173REG32(LATENCY_REGULATION_REGISTER_S1, 0x2134)
174 FIELD(LATENCY_REGULATION_REGISTER_S1, AR_SCALE_FACT, 3, 8)
175 FIELD(LATENCY_REGULATION_REGISTER_S1, AW_SCALE_FACT, 3, 0)
176REG32(QOS_RANGE_REGISTER_S1, 0x2138)
177 FIELD(QOS_RANGE_REGISTER_S1, MAX_ARQOS, 4, 24)
178 FIELD(QOS_RANGE_REGISTER_S1, MIN_ARQOS, 4, 16)
179 FIELD(QOS_RANGE_REGISTER_S1, MAX_AWQOS, 4, 8)
180 FIELD(QOS_RANGE_REGISTER_S1, MIN_AWQOS, 4, 0)
181REG32(SNOOP_CONTROL_REGISTER_S2, 0x3000)
182 FIELD(SNOOP_CONTROL_REGISTER_S2, SUPPORT_DVMS, 1, 31)
183 FIELD(SNOOP_CONTROL_REGISTER_S2, SUPPORT_SNOOPS, 1, 30)
184 FIELD(SNOOP_CONTROL_REGISTER_S2, ENABLE_DVMS, 1, 1)
185REG32(SHAREABLE_OVERRIDE_REGISTER_S2, 0x3004)
186 FIELD(SHAREABLE_OVERRIDE_REGISTER_S2, AXDOMAIN_OVERRIDE, 2, 0)
187REG32(READ_QOS_OVERRIDE_REGISTER_S2, 0x3100)
188 FIELD(READ_QOS_OVERRIDE_REGISTER_S2, ARQOS_OVERRIDE_READBACK, 4, 8)
189 FIELD(READ_QOS_OVERRIDE_REGISTER_S2, ARQOS_VALUE, 4, 0)
190REG32(WRITE_QOS_OVERRIDE_REGISTER_S2, 0x3104)
191 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S2, AWQOS_OVERRIDE_READBACK, 4, 8)
192 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S2, AWQOS_VALUE, 4, 0)
193REG32(QOS_CONTROL_REGISTER_S2, 0x310c)
194 FIELD(QOS_CONTROL_REGISTER_S2, QOS_REGULATION_DISABLED, 1, 31)
195 FIELD(QOS_CONTROL_REGISTER_S2, BANDWIDTH_REGULATION_MODE, 1, 21)
196 FIELD(QOS_CONTROL_REGISTER_S2, ARQOS_REGULATION_MODE, 1, 20)
197 FIELD(QOS_CONTROL_REGISTER_S2, AWQOS_REGULATION_MODE, 1, 16)
198 FIELD(QOS_CONTROL_REGISTER_S2, AR_OT_REGULATION, 1, 3)
199 FIELD(QOS_CONTROL_REGISTER_S2, AW_OT_REGULATION, 1, 2)
200 FIELD(QOS_CONTROL_REGISTER_S2, ARQOS_REGULATION, 1, 1)
201 FIELD(QOS_CONTROL_REGISTER_S2, AWQOS_REGULATION, 1, 0)
202REG32(MAX_OT_REGISTER_S2, 0x3110)
203 FIELD(MAX_OT_REGISTER_S2, INT_OT_AR, 6, 24)
204 FIELD(MAX_OT_REGISTER_S2, FRAC_OT_AR, 8, 16)
205 FIELD(MAX_OT_REGISTER_S2, INT_OT_AW, 6, 8)
206 FIELD(MAX_OT_REGISTER_S2, FRAC_OT_AW, 8, 0)
207REG32(TARGET_LATENCY_REGISTER_S2, 0x3130)
208 FIELD(TARGET_LATENCY_REGISTER_S2, AR_LAT, 12, 16)
209 FIELD(TARGET_LATENCY_REGISTER_S2, AW_LAT, 12, 0)
210REG32(LATENCY_REGULATION_REGISTER_S2, 0x3134)
211 FIELD(LATENCY_REGULATION_REGISTER_S2, AR_SCALE_FACT, 3, 8)
212 FIELD(LATENCY_REGULATION_REGISTER_S2, AW_SCALE_FACT, 3, 0)
213REG32(QOS_RANGE_REGISTER_S2, 0x3138)
214 FIELD(QOS_RANGE_REGISTER_S2, MAX_ARQOS, 4, 24)
215 FIELD(QOS_RANGE_REGISTER_S2, MIN_ARQOS, 4, 16)
216 FIELD(QOS_RANGE_REGISTER_S2, MAX_AWQOS, 4, 8)
217 FIELD(QOS_RANGE_REGISTER_S2, MIN_AWQOS, 4, 0)
218REG32(SNOOP_CONTROL_REGISTER_S3, 0x4000)
219 FIELD(SNOOP_CONTROL_REGISTER_S3, SUPPORT_DVMS, 1, 31)
220 FIELD(SNOOP_CONTROL_REGISTER_S3, SUPPORT_SNOOPS, 1, 30)
221 FIELD(SNOOP_CONTROL_REGISTER_S3, ENABLE_DVMS, 1, 1)
222 FIELD(SNOOP_CONTROL_REGISTER_S3, ENABLE_SNOOPS, 1, 0)
223REG32(READ_QOS_OVERRIDE_REGISTER_S3, 0x4100)
224 FIELD(READ_QOS_OVERRIDE_REGISTER_S3, ARQOS_OVERRIDE_READBACK, 4, 8)
225 FIELD(READ_QOS_OVERRIDE_REGISTER_S3, ARQOS_VALUE, 4, 0)
226REG32(WRITE_QOS_OVERRIDE_REGISTER_S3, 0x4104)
227 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S3, AWQOS_OVERRIDE_READBACK, 4, 8)
228 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S3, AWQOS_VALUE, 4, 0)
229REG32(QOS_CONTROL_REGISTER_S3, 0x410c)
230 FIELD(QOS_CONTROL_REGISTER_S3, QOS_REGULATION_DISABLED, 1, 31)
231 FIELD(QOS_CONTROL_REGISTER_S3, BANDWIDTH_REGULATION_MODE, 1, 21)
232 FIELD(QOS_CONTROL_REGISTER_S3, ARQOS_REGULATION_MODE, 1, 20)
233 FIELD(QOS_CONTROL_REGISTER_S3, AWQOS_REGULATION_MODE, 1, 16)
234 FIELD(QOS_CONTROL_REGISTER_S3, ARQOS_REGULATION, 1, 1)
235 FIELD(QOS_CONTROL_REGISTER_S3, AWQOS_REGULATION, 1, 0)
236REG32(TARGET_LATENCY_REGISTER_S3, 0x4130)
237 FIELD(TARGET_LATENCY_REGISTER_S3, AR_LAT, 12, 16)
238 FIELD(TARGET_LATENCY_REGISTER_S3, AW_LAT, 12, 0)
239REG32(LATENCY_REGULATION_REGISTER_S3, 0x4134)
240 FIELD(LATENCY_REGULATION_REGISTER_S3, AR_SCALE_FACT, 3, 8)
241 FIELD(LATENCY_REGULATION_REGISTER_S3, AW_SCALE_FACT, 3, 0)
242REG32(QOS_RANGE_REGISTER_S3, 0x4138)
243 FIELD(QOS_RANGE_REGISTER_S3, MAX_ARQOS, 4, 24)
244 FIELD(QOS_RANGE_REGISTER_S3, MIN_ARQOS, 4, 16)
245 FIELD(QOS_RANGE_REGISTER_S3, MAX_AWQOS, 4, 8)
246 FIELD(QOS_RANGE_REGISTER_S3, MIN_AWQOS, 4, 0)
247REG32(SNOOP_CONTROL_REGISTER_S4, 0x5000)
248 FIELD(SNOOP_CONTROL_REGISTER_S4, SUPPORT_DVMS, 1, 31)
249 FIELD(SNOOP_CONTROL_REGISTER_S4, SUPPORT_SNOOPS, 1, 30)
250 FIELD(SNOOP_CONTROL_REGISTER_S4, ENABLE_DVMS, 1, 1)
251 FIELD(SNOOP_CONTROL_REGISTER_S4, ENABLE_SNOOPS, 1, 0)
252REG32(READ_QOS_OVERRIDE_REGISTER_S4, 0x5100)
253 FIELD(READ_QOS_OVERRIDE_REGISTER_S4, ARQOS_OVERRIDE_READBACK, 4, 8)
254 FIELD(READ_QOS_OVERRIDE_REGISTER_S4, ARQOS_VALUE, 4, 0)
255REG32(WRITE_QOS_OVERRIDE_REGISTER_S4, 0x5104)
256 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S4, AWQOS_OVERRIDE_READBACK, 4, 8)
257 FIELD(WRITE_QOS_OVERRIDE_REGISTER_S4, AWQOS_VALUE, 4, 0)
258REG32(QOS_CONTROL_REGISTER_S4, 0x510c)
259 FIELD(QOS_CONTROL_REGISTER_S4, QOS_REGULATION_DISABLED, 1, 31)
260 FIELD(QOS_CONTROL_REGISTER_S4, BANDWIDTH_REGULATION_MODE, 1, 21)
261 FIELD(QOS_CONTROL_REGISTER_S4, ARQOS_REGULATION_MODE, 1, 20)
262 FIELD(QOS_CONTROL_REGISTER_S4, AWQOS_REGULATION_MODE, 1, 16)
263 FIELD(QOS_CONTROL_REGISTER_S4, ARQOS_REGULATION, 1, 1)
264 FIELD(QOS_CONTROL_REGISTER_S4, AWQOS_REGULATION, 1, 0)
265REG32(TARGET_LATENCY_REGISTER_S4, 0x5130)
266 FIELD(TARGET_LATENCY_REGISTER_S4, AR_LAT, 12, 16)
267 FIELD(TARGET_LATENCY_REGISTER_S4, AW_LAT, 12, 0)
268REG32(LATENCY_REGULATION_REGISTER_S4, 0x5134)
269 FIELD(LATENCY_REGULATION_REGISTER_S4, AR_SCALE_FACT, 3, 8)
270 FIELD(LATENCY_REGULATION_REGISTER_S4, AW_SCALE_FACT, 3, 0)
271REG32(QOS_RANGE_REGISTER_S4, 0x5138)
272 FIELD(QOS_RANGE_REGISTER_S4, MAX_ARQOS, 4, 24)
273 FIELD(QOS_RANGE_REGISTER_S4, MIN_ARQOS, 4, 16)
274 FIELD(QOS_RANGE_REGISTER_S4, MAX_AWQOS, 4, 8)
275 FIELD(QOS_RANGE_REGISTER_S4, MIN_AWQOS, 4, 0)
276REG32(CYCLE_COUNTER, 0x9004)
277REG32(CYCLE_COUNTER_CONTROL, 0x9008)
278 FIELD(CYCLE_COUNTER_CONTROL, CCNT_EN, 1, 0)
279REG32(CYCLE_COUNT_OVERFLOW, 0x900c)
280 FIELD(CYCLE_COUNT_OVERFLOW, CCNT_OVERFLOW, 1, 0)
281REG32(ESR0, 0xa000)
282 FIELD(ESR0, EVT_IF0, 3, 5)
283 FIELD(ESR0, EVT_CNT0, 5, 0)
284REG32(EVENT_COUNTER0, 0xa004)
285REG32(EVENT_COUNTER0_CONTROL, 0xa008)
286 FIELD(EVENT_COUNTER0_CONTROL, CNT0_EN, 1, 0)
287REG32(EVENT_COUNTER0_OVERFLOW, 0xa00c)
288 FIELD(EVENT_COUNTER0_OVERFLOW, CNT0_OVERFLOW, 1, 0)
289REG32(ESR1, 0xb000)
290 FIELD(ESR1, EVT_IF1, 3, 5)
291 FIELD(ESR1, EVT_CNT1, 5, 0)
292REG32(EVENT_COUNTER1, 0xb004)
293REG32(EVENT_COUNTER1_CONTROL, 0xb008)
294 FIELD(EVENT_COUNTER1_CONTROL, CNT1_EN, 1, 0)
295REG32(EVENT_COUNTER1_OVERFLOW, 0xb00c)
296 FIELD(EVENT_COUNTER1_OVERFLOW, CNT1_OVERFLOW, 1, 0)
297REG32(ESR2, 0xc000)
298 FIELD(ESR2, EVT_IF2, 3, 5)
299 FIELD(ESR2, EVT_CNT2, 5, 0)
300REG32(EVENT_COUNTER2, 0xc004)
301REG32(EVENT_COUNTER2_CONTROL, 0xc008)
302 FIELD(EVENT_COUNTER2_CONTROL, CNT2_EN, 1, 0)
303REG32(EVENT_COUNTER2_OVERFLOW, 0xc00c)
304 FIELD(EVENT_COUNTER2_OVERFLOW, CNT2_OVERFLOW, 1, 0)
305REG32(ESR3, 0xd000)
306 FIELD(ESR3, EVT_IF3, 3, 5)
307 FIELD(ESR3, EVT_CNT3, 5, 0)
308REG32(EVENT_COUNTER3, 0xd004)
309REG32(EVENT_COUNTER3_CONTROL, 0xd008)
310 FIELD(EVENT_COUNTER3_CONTROL, CNT3_EN, 1, 0)
311REG32(EVENT_COUNTER3_OVERFLOW, 0xd00c)
312 FIELD(EVENT_COUNTER3_OVERFLOW, CNT3_OVERFLOW, 1, 0)
313
314#define R_MAX (R_EVENT_COUNTER3_OVERFLOW + 1)
315
316typedef struct CCI {
317 SysBusDevice parent_obj;
318 MemoryRegion iomem;
319 MemoryRegion iommu;
320
321 struct {
322 uint64_t stripe_granule_sz;
323 } cfg;
324
325
326 AddressSpace *as[3];
327 MemoryRegion *M[3];
328
329 uint32_t regs[R_MAX];
330 RegisterInfo regs_info[R_MAX];
331
332 uint64_t enable_mask;
333} CCI;
334
335static RegisterAccessInfo cci400_regs_info[] = {
336 { .name = "CONTROL_OVERRIDE_REGISTER",
337 .decode.addr = A_CONTROL_OVERRIDE_REGISTER,
338 },{ .name = "SPECULATION_CONTROL_REGISTER",
339 .decode.addr = A_SPECULATION_CONTROL_REGISTER,
340 },{ .name = "SECURE_ACCESS_REGISTER",
341 .decode.addr = A_SECURE_ACCESS_REGISTER,
342 },{ .name = "STATUS_REGISTER", .decode.addr = A_STATUS_REGISTER,
343 .ro = 0x1,
344 },{ .name = "IMPRECISE_ERROR_REGISTER",
345 .decode.addr = A_IMPRECISE_ERROR_REGISTER,
346 .w1c = 0x1f0007,
347 },{ .name = "PERFORMANCE_MONITOR_CONTROL_REGISTER",
348 .decode.addr = A_PERFORMANCE_MONITOR_CONTROL_REGISTER,
349 .reset = 0x2000,
350 .ro = 0xf800,
351 },{ .name = "PERIPHERAL_ID4", .decode.addr = A_PERIPHERAL_ID4,
352 .reset = 0x44,
353 .ro = 0xff,
354 },{ .name = "PERIPHERAL_ID5", .decode.addr = A_PERIPHERAL_ID5,
355 .ro = 0xff,
356 },{ .name = "PERIPHERAL_ID6", .decode.addr = A_PERIPHERAL_ID6,
357 .ro = 0xff,
358 },{ .name = "PERIPHERAL_ID7", .decode.addr = A_PERIPHERAL_ID7,
359 .ro = 0xff,
360 },{ .name = "PERIPHERAL_ID0", .decode.addr = A_PERIPHERAL_ID0,
361 .reset = 0x20,
362 .ro = 0xff,
363 },{ .name = "PERIPHERAL_ID1", .decode.addr = A_PERIPHERAL_ID1,
364 .reset = 0xb4,
365 .ro = 0xff,
366 },{ .name = "PERIPHERAL_ID2", .decode.addr = A_PERIPHERAL_ID2,
367 .reset = 0x9b,
368 .ro = 0xff,
369 },{ .name = "PERIPHERAL_ID3", .decode.addr = A_PERIPHERAL_ID3,
370 .ro = 0xff,
371 },{ .name = "COMPONENT_ID0", .decode.addr = A_COMPONENT_ID0,
372 .reset = 0xd,
373 .ro = 0xff,
374 },{ .name = "COMPONENT_ID1", .decode.addr = A_COMPONENT_ID1,
375 .reset = 0xf0,
376 .ro = 0xff,
377 },{ .name = "COMPONENT_ID2", .decode.addr = A_COMPONENT_ID2,
378 .reset = 0x5,
379 .ro = 0xff,
380 },{ .name = "COMPONENT_ID3", .decode.addr = A_COMPONENT_ID3,
381 .reset = 0xb1,
382 .ro = 0xff,
383 },{ .name = "SNOOP_CONTROL_REGISTER_S0",
384 .decode.addr = A_SNOOP_CONTROL_REGISTER_S0,
385 .reset = 0x80000000,
386 .ro = 0xc0000000,
387 },{ .name = "SHAREABLE_OVERRIDE_REGISTER_S0",
388 .decode.addr = A_SHAREABLE_OVERRIDE_REGISTER_S0,
389 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S0",
390 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S0,
391 .ro = 0xf00,
392 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S0",
393 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S0,
394 .ro = 0xf00,
395 },{ .name = "QOS_CONTROL_REGISTER_S0",
396 .decode.addr = A_QOS_CONTROL_REGISTER_S0,
397 .ro = 0x80000000,
398 },{ .name = "MAX_OT_REGISTER_S0", .decode.addr = A_MAX_OT_REGISTER_S0,
399 },{ .name = "TARGET_LATENCY_REGISTER_S0",
400 .decode.addr = A_TARGET_LATENCY_REGISTER_S0,
401 },{ .name = "LATENCY_REGULATION_REGISTER_S0",
402 .decode.addr = A_LATENCY_REGULATION_REGISTER_S0,
403 },{ .name = "QOS_RANGE_REGISTER_S0",
404 .decode.addr = A_QOS_RANGE_REGISTER_S0,
405 },{ .name = "SNOOP_CONTROL_REGISTER_S1",
406 .decode.addr = A_SNOOP_CONTROL_REGISTER_S1,
407 .ro = 0xc0000002,
408 },{ .name = "SHAREABLE_OVERRIDE_REGISTER_S1",
409 .decode.addr = A_SHAREABLE_OVERRIDE_REGISTER_S1,
410 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S1",
411 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S1,
412 .ro = 0xf00,
413 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S1",
414 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S1,
415 .ro = 0xf00,
416 },{ .name = "QOS_CONTROL_REGISTER_S1",
417 .decode.addr = A_QOS_CONTROL_REGISTER_S1,
418 .ro = 0x80000000,
419 },{ .name = "MAX_OT_REGISTER_S1", .decode.addr = A_MAX_OT_REGISTER_S1,
420 },{ .name = "TARGET_LATENCY_REGISTER_S1",
421 .decode.addr = A_TARGET_LATENCY_REGISTER_S1,
422 },{ .name = "LATENCY_REGULATION_REGISTER_S1",
423 .decode.addr = A_LATENCY_REGULATION_REGISTER_S1,
424 },{ .name = "QOS_RANGE_REGISTER_S1",
425 .decode.addr = A_QOS_RANGE_REGISTER_S1,
426 },{ .name = "SNOOP_CONTROL_REGISTER_S2",
427 .decode.addr = A_SNOOP_CONTROL_REGISTER_S2,
428 .ro = 0xc0000002,
429 },{ .name = "SHAREABLE_OVERRIDE_REGISTER_S2",
430 .decode.addr = A_SHAREABLE_OVERRIDE_REGISTER_S2,
431 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S2",
432 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S2,
433 .ro = 0xf00,
434 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S2",
435 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S2,
436 .ro = 0xf00,
437 },{ .name = "QOS_CONTROL_REGISTER_S2",
438 .decode.addr = A_QOS_CONTROL_REGISTER_S2,
439 .ro = 0x80000000,
440 },{ .name = "MAX_OT_REGISTER_S2", .decode.addr = A_MAX_OT_REGISTER_S2,
441 },{ .name = "TARGET_LATENCY_REGISTER_S2",
442 .decode.addr = A_TARGET_LATENCY_REGISTER_S2,
443 },{ .name = "LATENCY_REGULATION_REGISTER_S2",
444 .decode.addr = A_LATENCY_REGULATION_REGISTER_S2,
445 },{ .name = "QOS_RANGE_REGISTER_S2",
446 .decode.addr = A_QOS_RANGE_REGISTER_S2,
447 },{ .name = "SNOOP_CONTROL_REGISTER_S3",
448 .decode.addr = A_SNOOP_CONTROL_REGISTER_S3,
449 .reset = 0xc0000000,
450 .ro = 0xc0000000,
451 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S3",
452 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S3,
453 .ro = 0xf00,
454 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S3",
455 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S3,
456 .ro = 0xf00,
457 },{ .name = "QOS_CONTROL_REGISTER_S3",
458 .decode.addr = A_QOS_CONTROL_REGISTER_S3,
459 .ro = 0x80000000,
460 },{ .name = "TARGET_LATENCY_REGISTER_S3",
461 .decode.addr = A_TARGET_LATENCY_REGISTER_S3,
462 },{ .name = "LATENCY_REGULATION_REGISTER_S3",
463 .decode.addr = A_LATENCY_REGULATION_REGISTER_S3,
464 },{ .name = "QOS_RANGE_REGISTER_S3",
465 .decode.addr = A_QOS_RANGE_REGISTER_S3,
466 },{ .name = "SNOOP_CONTROL_REGISTER_S4",
467 .decode.addr = A_SNOOP_CONTROL_REGISTER_S4,
468 .reset = 0xc0000000,
469 .ro = 0xc0000000,
470 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S4",
471 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S4,
472 .ro = 0xf00,
473 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S4",
474 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S4,
475 .ro = 0xf00,
476 },{ .name = "QOS_CONTROL_REGISTER_S4",
477 .decode.addr = A_QOS_CONTROL_REGISTER_S4,
478 .ro = 0x80000000,
479 },{ .name = "TARGET_LATENCY_REGISTER_S4",
480 .decode.addr = A_TARGET_LATENCY_REGISTER_S4,
481 },{ .name = "LATENCY_REGULATION_REGISTER_S4",
482 .decode.addr = A_LATENCY_REGULATION_REGISTER_S4,
483 },{ .name = "QOS_RANGE_REGISTER_S4",
484 .decode.addr = A_QOS_RANGE_REGISTER_S4,
485 },{ .name = "CYCLE_COUNTER", .decode.addr = A_CYCLE_COUNTER,
486 },{ .name = "CYCLE_COUNTER_CONTROL",
487 .decode.addr = A_CYCLE_COUNTER_CONTROL,
488 },{ .name = "CYCLE_COUNT_OVERFLOW", .decode.addr = A_CYCLE_COUNT_OVERFLOW,
489 .w1c = 0x1,
490 },{ .name = "ESR0", .decode.addr = A_ESR0,
491 },{ .name = "EVENT_COUNTER0", .decode.addr = A_EVENT_COUNTER0,
492 },{ .name = "EVENT_COUNTER0_CONTROL",
493 .decode.addr = A_EVENT_COUNTER0_CONTROL,
494 },{ .name = "EVENT_COUNTER0_OVERFLOW",
495 .decode.addr = A_EVENT_COUNTER0_OVERFLOW,
496 .w1c = 0x1,
497 },{ .name = "ESR1", .decode.addr = A_ESR1,
498 },{ .name = "EVENT_COUNTER1", .decode.addr = A_EVENT_COUNTER1,
499 },{ .name = "EVENT_COUNTER1_CONTROL",
500 .decode.addr = A_EVENT_COUNTER1_CONTROL,
501 },{ .name = "EVENT_COUNTER1_OVERFLOW",
502 .decode.addr = A_EVENT_COUNTER1_OVERFLOW,
503 .w1c = 0x1,
504 },{ .name = "ESR2", .decode.addr = A_ESR2,
505 },{ .name = "EVENT_COUNTER2", .decode.addr = A_EVENT_COUNTER2,
506 },{ .name = "EVENT_COUNTER2_CONTROL",
507 .decode.addr = A_EVENT_COUNTER2_CONTROL,
508 },{ .name = "EVENT_COUNTER2_OVERFLOW",
509 .decode.addr = A_EVENT_COUNTER2_OVERFLOW,
510 .w1c = 0x1,
511 },{ .name = "ESR3", .decode.addr = A_ESR3,
512 },{ .name = "EVENT_COUNTER3", .decode.addr = A_EVENT_COUNTER3,
513 },{ .name = "EVENT_COUNTER3_CONTROL",
514 .decode.addr = A_EVENT_COUNTER3_CONTROL,
515 },{ .name = "EVENT_COUNTER3_OVERFLOW",
516 .decode.addr = A_EVENT_COUNTER3_OVERFLOW,
517 .w1c = 0x1,
518 }
519};
520
521static void cci400_reset(DeviceState *dev)
522{
523 CCI *s = ARM_CCI400(dev);
524 unsigned int i;
525
526 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
527 register_reset(&s->regs_info[i]);
528 }
529
530}
531
532static uint64_t cci400_read(void *opaque, hwaddr addr, unsigned size)
533{
534 CCI *s = ARM_CCI400(opaque);
535 RegisterInfo *r = &s->regs_info[addr / 4];
536
537 if (!r->data) {
538 qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
539 object_get_canonical_path(OBJECT(s)),
540 addr);
541 return 0;
542 }
543 return register_read(r);
544}
545
546static void cci400_write(void *opaque, hwaddr addr, uint64_t value,
547 unsigned size)
548{
549 CCI *s = ARM_CCI400(opaque);
550 RegisterInfo *r = &s->regs_info[addr / 4];
551
552 if (!r->data) {
553 qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
554 object_get_canonical_path(OBJECT(s)),
555 addr, value);
556 return;
557 }
558 register_write(r, value, ~0);
559}
560
561static const MemoryRegionOps cci400_ops = {
562 .read = cci400_read,
563 .write = cci400_write,
564 .endianness = DEVICE_LITTLE_ENDIAN,
565 .valid = {
566 .min_access_size = 4,
567 .max_access_size = 4,
568 },
569};
570
571static IOMMUTLBEntry cci_translate(MemoryRegion *mr, hwaddr addr,
572 bool is_write, MemTxAttrs *attr)
573{
574 CCI *s = container_of(mr, CCI, iommu);;
575 IOMMUTLBEntry ret = {
576 .iova = addr,
577 .translated_addr = addr,
578 .addr_mask = s->cfg.stripe_granule_sz - 1,
579 .perm = IOMMU_RW,
580 };
581 unsigned int i, mi = 0;
582 bool valid = false;
583
584
585 for (i = 1; i < ARRAY_SIZE(s->as); i++) {
586 bool t;
587 t = address_space_access_valid(s->as[i], addr, 4, false, *attr);
588 if (i > 1) {
589 assert(valid == t);
590 }
591 valid = t;
592 }
593 if (valid) {
594 unsigned int stripe_idx = !!(addr & s->cfg.stripe_granule_sz);
595
596 mi = 1 + stripe_idx;
597 }
598
599 ret.target_as = s->as[mi];
600 return ret;
601}
602
603static MemoryRegionIOMMUOps cci_iommu_ops = {
604 .translate_attr = cci_translate,
605};
606
607static void cci400_realize(DeviceState *dev, Error **errp)
608{
609 CCI *s = ARM_CCI400(dev);
610 const char *prefix = object_get_canonical_path(OBJECT(dev));
611 unsigned int i;
612
613 for (i = 0; i < ARRAY_SIZE(cci400_regs_info); ++i) {
614 RegisterInfo *r = &s->regs_info[cci400_regs_info[i].decode.addr/4];
615
616 *r = (RegisterInfo) {
617 .data = (uint8_t *)&s->regs[
618 cci400_regs_info[i].decode.addr/4],
619 .data_size = sizeof(uint32_t),
620 .access = &cci400_regs_info[i],
621 .debug = ARM_CCI400_ERR_DEBUG,
622 .prefix = prefix,
623 .opaque = s,
624 };
625 }
626
627 for (i = 0; i < ARRAY_SIZE(s->M); i++) {
628 s->as[i] = address_space_init_shareable(s->M[i], NULL);
629 assert(s->as[i]);
630 }
631}
632
633static void sig_handler(void *opaque, int n, int level)
634{
635 CCI *s = ARM_CCI400(opaque);
636 uint64_t level64 = level;
637
638 s->enable_mask &= ~(1ULL << n);
639 s->enable_mask |= level64 << n;
640 memory_region_set_enabled(&s->iommu, !!s->enable_mask);
641}
642
643static void cci400_init(Object *obj)
644{
645 CCI *s = ARM_CCI400(obj);
646 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
647 unsigned int i;
648
649 memory_region_init_io(&s->iomem, obj, &cci400_ops, s,
650 TYPE_ARM_CCI400, R_MAX * 4);
651 sysbus_init_mmio(sbd, &s->iomem);
652
653 memory_region_init_iommu(&s->iommu, OBJECT(s), &cci_iommu_ops,
654 "cci-iommu", UINT64_MAX);
655 sysbus_init_mmio(sbd, &s->iommu);
656
657 for (i = 0; i < ARRAY_SIZE(s->M); i++) {
658 char *name = g_strdup_printf("M%d", i);
659 object_property_add_link(obj, name, TYPE_MEMORY_REGION,
660 (Object **)&s->M[i],
661 qdev_prop_allow_set_link_before_realize,
662 OBJ_PROP_LINK_UNREF_ON_RELEASE,
663 &error_abort);
664 g_free(name);
665 }
666
667 qdev_init_gpio_in_named(DEVICE(sbd), sig_handler, "enable", 16);
668
669
670 s->cfg.stripe_granule_sz = 4096;
671}
672
673static const VMStateDescription vmstate_cci400 = {
674 .name = TYPE_ARM_CCI400,
675 .version_id = 1,
676 .minimum_version_id = 1,
677 .minimum_version_id_old = 1,
678 .fields = (VMStateField[]) {
679 VMSTATE_UINT32_ARRAY(regs, CCI, R_MAX),
680 VMSTATE_END_OF_LIST(),
681 }
682};
683
684static const FDTGenericGPIOSet gpio_sets[] = {
685 {
686 .names = &fdt_generic_gpio_name_set_gpio,
687 .gpios = (FDTGenericGPIOConnection[]) {
688 { .name = "enable", .fdt_index = 0, .range = 16 },
689 { },
690 },
691 },
692 { },
693};
694
695static void cci400_class_init(ObjectClass *klass, void *data)
696{
697 DeviceClass *dc = DEVICE_CLASS(klass);
698 FDTGenericGPIOClass *fggc = FDT_GENERIC_GPIO_CLASS(klass);
699
700 dc->reset = cci400_reset;
701 dc->realize = cci400_realize;
702 dc->vmsd = &vmstate_cci400;
703 fggc->controller_gpios = gpio_sets;
704}
705
706static const TypeInfo cci400_info = {
707 .name = TYPE_ARM_CCI400,
708 .parent = TYPE_SYS_BUS_DEVICE,
709 .instance_size = sizeof(CCI),
710 .class_init = cci400_class_init,
711 .instance_init = cci400_init,
712 .interfaces = (InterfaceInfo[]) {
713 { TYPE_FDT_GENERIC_GPIO },
714 { }
715 },
716};
717
718static void cci400_register_types(void)
719{
720 type_register_static(&cci400_info);
721}
722
723type_init(cci400_register_types)
724
