LXR qemu/hw/misc/arm11scu.c

   1/*
   2 * ARM11MPCore Snoop Control Unit (SCU) emulation
   3 *
   4 * Copyright (c) 2006-2007 CodeSourcery.
   5 * Copyright (c) 2013 SUSE LINUX Products GmbH
   6 * Written by Paul Brook and Andreas Färber
   7 *
   8 * This code is licensed under the GPL.
   9 */
  10
  11#include "qemu/osdep.h"
  12#include "hw/misc/arm11scu.h"
  13#include "qemu/log.h"
  14
  15static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
  16                                unsigned size)
  17{
  18    ARM11SCUState *s = (ARM11SCUState *)opaque;
  19    int id;
  20    /* SCU */
  21    switch (offset) {
  22    case 0x00: /* Control.  */
  23        return s->control;
  24    case 0x04: /* Configuration.  */
  25        id = ((1 << s->num_cpu) - 1) << 4;
  26        return id | (s->num_cpu - 1);
  27    case 0x08: /* CPU status.  */
  28        return 0;
  29    case 0x0c: /* Invalidate all.  */
  30        return 0;
  31    default:
  32        qemu_log_mask(LOG_GUEST_ERROR,
  33                      "mpcore_priv_read: Bad offset %x\n", (int)offset);
  34        return 0;
  35    }
  36}
  37
  38static void mpcore_scu_write(void *opaque, hwaddr offset,
  39                             uint64_t value, unsigned size)
  40{
  41    ARM11SCUState *s = (ARM11SCUState *)opaque;
  42    /* SCU */
  43    switch (offset) {
  44    case 0: /* Control register.  */
  45        s->control = value & 1;
  46        break;
  47    case 0x0c: /* Invalidate all.  */
  48        /* This is a no-op as cache is not emulated.  */
  49        break;
  50    default:
  51        qemu_log_mask(LOG_GUEST_ERROR,
  52                      "mpcore_priv_read: Bad offset %x\n", (int)offset);
  53    }
  54}
  55
  56static const MemoryRegionOps mpcore_scu_ops = {
  57    .read = mpcore_scu_read,
  58    .write = mpcore_scu_write,
  59    .endianness = DEVICE_NATIVE_ENDIAN,
  60};
  61
  62static void arm11_scu_realize(DeviceState *dev, Error **errp)
  63{
  64}
  65
  66static void arm11_scu_init(Object *obj)
  67{
  68    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  69    ARM11SCUState *s = ARM11_SCU(obj);
  70
  71    memory_region_init_io(&s->iomem, OBJECT(s),
  72                          &mpcore_scu_ops, s, "mpcore-scu", 0x100);
  73    sysbus_init_mmio(sbd, &s->iomem);
  74}
  75
  76static Property arm11_scu_properties[] = {
  77    DEFINE_PROP_UINT32("num-cpu", ARM11SCUState, num_cpu, 1),
  78    DEFINE_PROP_END_OF_LIST()
  79};
  80
  81static void arm11_scu_class_init(ObjectClass *oc, void *data)
  82{
  83    DeviceClass *dc = DEVICE_CLASS(oc);
  84
  85    dc->realize = arm11_scu_realize;
  86    dc->props = arm11_scu_properties;
  87}
  88
  89static const TypeInfo arm11_scu_type_info = {
  90    .name          = TYPE_ARM11_SCU,
  91    .parent        = TYPE_SYS_BUS_DEVICE,
  92    .instance_size = sizeof(ARM11SCUState),
  93    .instance_init = arm11_scu_init,
  94    .class_init    = arm11_scu_class_init,
  95};
  96
  97static void arm11_scu_register_types(void)
  98{
  99    type_register_static(&arm11_scu_type_info);
 100}
 101
 102type_init(arm11_scu_register_types)
 103