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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/register.h"
30#include "qemu/bitops.h"
31#include "qemu/log.h"
32
33#ifndef XILINX_DDRC_ERR_DEBUG
34#define XILINX_DDRC_ERR_DEBUG 0
35#endif
36
37#define TYPE_XILINX_DDRC "xlnx.zynqmp-ddrc"
38
39#define XILINX_DDRC(obj) \
40 OBJECT_CHECK(DDRC, (obj), TYPE_XILINX_DDRC)
41
42REG32(MSTR, 0x0)
43 FIELD(MSTR, DEVICE_CONFIG, 2, 30)
44 FIELD(MSTR, FREQUENCY_MODE, 1, 29)
45 FIELD(MSTR, ACTIVE_RANKS, 2, 24)
46 FIELD(MSTR, BURST_RDWR, 4, 16)
47 FIELD(MSTR, DLL_OFF_MODE, 1, 15)
48 FIELD(MSTR, DATA_BUS_WIDTH, 2, 12)
49 FIELD(MSTR, GEARDOWN_MODE, 1, 11)
50 FIELD(MSTR, EN_2T_TIMING_MODE, 1, 10)
51 FIELD(MSTR, BURSTCHOP, 1, 9)
52 FIELD(MSTR, LPDDR4, 1, 5)
53 FIELD(MSTR, DDR4, 1, 4)
54 FIELD(MSTR, LPDDR3, 1, 3)
55 FIELD(MSTR, LPDDR2, 1, 2)
56 FIELD(MSTR, DDR3, 1, 0)
57REG32(STAT, 0x4)
58 FIELD(STAT, SELFREF_STATE, 2, 8)
59 FIELD(STAT, SELFREF_TYPE, 2, 4)
60 FIELD(STAT, OPERATING_MODE, 3, 0)
61REG32(MRCTRL0, 0x10)
62 FIELD(MRCTRL0, MR_WR, 1, 31)
63 FIELD(MRCTRL0, MR_ADDR, 4, 12)
64 FIELD(MRCTRL0, MR_RANK, 2, 4)
65 FIELD(MRCTRL0, SW_INIT_INT, 1, 3)
66 FIELD(MRCTRL0, PDA_EN, 1, 2)
67 FIELD(MRCTRL0, MPR_EN, 1, 1)
68 FIELD(MRCTRL0, MR_TYPE, 1, 0)
69REG32(MRCTRL1, 0x14)
70 FIELD(MRCTRL1, MR_DATA, 18, 0)
71REG32(MRSTAT, 0x18)
72 FIELD(MRSTAT, PDA_DONE, 1, 8)
73 FIELD(MRSTAT, MR_WR_BUSY, 1, 0)
74REG32(MRCTRL2, 0x1c)
75REG32(DERATEEN, 0x20)
76 FIELD(DERATEEN, RC_DERATE_VALUE, 2, 8)
77 FIELD(DERATEEN, DERATE_BYTE, 4, 4)
78 FIELD(DERATEEN, DERATE_VALUE, 1, 1)
79 FIELD(DERATEEN, DERATE_ENABLE, 1, 0)
80REG32(DERATEINT, 0x24)
81REG32(PWRCTL, 0x30)
82 FIELD(PWRCTL, STAY_IN_SELFREF, 1, 6)
83 FIELD(PWRCTL, SELFREF_SW, 1, 5)
84 FIELD(PWRCTL, MPSM_EN, 1, 4)
85 FIELD(PWRCTL, EN_DFI_DRAM_CLK_DISABLE, 1, 3)
86 FIELD(PWRCTL, DEEPPOWERDOWN_EN, 1, 2)
87 FIELD(PWRCTL, POWERDOWN_EN, 1, 1)
88 FIELD(PWRCTL, SELFREF_EN, 1, 0)
89REG32(PWRTMG, 0x34)
90 FIELD(PWRTMG, SELFREF_TO_X32, 8, 16)
91 FIELD(PWRTMG, T_DPD_X4096, 8, 8)
92 FIELD(PWRTMG, POWERDOWN_TO_X32, 5, 0)
93REG32(HWLPCTL, 0x38)
94 FIELD(HWLPCTL, HW_LP_IDLE_X32, 12, 16)
95 FIELD(HWLPCTL, HW_LP_EXIT_IDLE_EN, 1, 1)
96 FIELD(HWLPCTL, HW_LP_EN, 1, 0)
97REG32(RFSHCTL0, 0x50)
98 FIELD(RFSHCTL0, REFRESH_MARGIN, 4, 20)
99 FIELD(RFSHCTL0, REFRESH_TO_X32, 5, 12)
100 FIELD(RFSHCTL0, REFRESH_BURST, 5, 4)
101 FIELD(RFSHCTL0, PER_BANK_REFRESH, 1, 2)
102REG32(RFSHCTL1, 0x54)
103 FIELD(RFSHCTL1, REFRESH_TIMER1_START_VALUE_X32, 12, 16)
104 FIELD(RFSHCTL1, REFRESH_TIMER0_START_VALUE_X32, 12, 0)
105REG32(RFSHCTL3, 0x60)
106 FIELD(RFSHCTL3, REFRESH_MODE, 3, 4)
107 FIELD(RFSHCTL3, REFRESH_UPDATE_LEVEL, 1, 1)
108 FIELD(RFSHCTL3, DIS_AUTO_REFRESH, 1, 0)
109REG32(RFSHTMG, 0x64)
110 FIELD(RFSHTMG, T_RFC_NOM_X32, 12, 16)
111 FIELD(RFSHTMG, LPDDR3_TREFBW_EN, 1, 15)
112 FIELD(RFSHTMG, T_RFC_MIN, 10, 0)
113REG32(ECCCFG0, 0x70)
114 FIELD(ECCCFG0, DIS_SCRUB, 1, 4)
115 FIELD(ECCCFG0, ECC_MODE, 3, 0)
116REG32(ECCCFG1, 0x74)
117 FIELD(ECCCFG1, DATA_POISON_BIT, 1, 1)
118 FIELD(ECCCFG1, DATA_POISON_EN, 1, 0)
119REG32(ECCSTAT, 0x78)
120 FIELD(ECCSTAT, ECC_UNCORRECTED_ERR, 4, 16)
121 FIELD(ECCSTAT, ECC_CORRECTED_ERR, 4, 8)
122 FIELD(ECCSTAT, ECC_CORRECTED_BIT_NUM, 7, 0)
123REG32(ECCCLR, 0x7c)
124 FIELD(ECCCLR, ECC_CLR_UNCORR_ERR_CNT, 1, 3)
125 FIELD(ECCCLR, ECC_CLR_CORR_ERR_CNT, 1, 2)
126 FIELD(ECCCLR, ECC_CLR_UNCORR_ERR, 1, 1)
127 FIELD(ECCCLR, ECC_CLR_CORR_ERR, 1, 0)
128REG32(ECCERRCNT, 0x80)
129 FIELD(ECCERRCNT, ECC_UNCORR_ERR_CNT, 16, 16)
130 FIELD(ECCERRCNT, ECC_CORR_ERR_CNT, 16, 0)
131REG32(ECCCADDR0, 0x84)
132 FIELD(ECCCADDR0, ECC_CORR_RANK, 1, 24)
133 FIELD(ECCCADDR0, ECC_CORR_ROW, 18, 0)
134REG32(ECCCADDR1, 0x88)
135 FIELD(ECCCADDR1, ECC_CORR_BG, 2, 24)
136 FIELD(ECCCADDR1, ECC_CORR_BANK, 3, 16)
137 FIELD(ECCCADDR1, ECC_CORR_COL, 12, 0)
138REG32(ECCCSYN0, 0x8c)
139REG32(ECCCSYN1, 0x90)
140REG32(ECCCSYN2, 0x94)
141 FIELD(ECCCSYN2, ECC_CORR_SYNDROMES_71_64, 8, 0)
142REG32(ECCBITMASK0, 0x98)
143REG32(ECCBITMASK1, 0x9c)
144REG32(ECCBITMASK2, 0xa0)
145 FIELD(ECCBITMASK2, ECC_CORR_BIT_MASK_71_64, 8, 0)
146REG32(ECCUADDR0, 0xa4)
147 FIELD(ECCUADDR0, ECC_UNCORR_RANK, 1, 24)
148 FIELD(ECCUADDR0, ECC_UNCORR_ROW, 18, 0)
149REG32(ECCUADDR1, 0xa8)
150 FIELD(ECCUADDR1, ECC_UNCORR_BG, 2, 24)
151 FIELD(ECCUADDR1, ECC_UNCORR_BANK, 3, 16)
152 FIELD(ECCUADDR1, ECC_UNCORR_COL, 12, 0)
153REG32(ECCUSYN0, 0xac)
154REG32(ECCUSYN1, 0xb0)
155REG32(ECCUSYN2, 0xb4)
156 FIELD(ECCUSYN2, ECC_UNCORR_SYNDROMES_71_64, 8, 0)
157REG32(ECCPOISONADDR0, 0xb8)
158 FIELD(ECCPOISONADDR0, ECC_POISON_RANK, 1, 24)
159 FIELD(ECCPOISONADDR0, ECC_POISON_COL, 12, 0)
160REG32(ECCPOISONADDR1, 0xbc)
161 FIELD(ECCPOISONADDR1, ECC_POISON_BG, 2, 28)
162 FIELD(ECCPOISONADDR1, ECC_POISON_BANK, 3, 24)
163 FIELD(ECCPOISONADDR1, ECC_POISON_ROW, 18, 0)
164REG32(CRCPARCTL0, 0xc0)
165 FIELD(CRCPARCTL0, RETRY_CTRLUPD_ENABLE, 1, 15)
166 FIELD(CRCPARCTL0, DFI_ALERT_ERR_MAX_REACHED_INT_CLR, 1, 8)
167 FIELD(CRCPARCTL0, DFI_ALERT_ERR_FATL_INT_CLR, 1, 4)
168 FIELD(CRCPARCTL0, DFI_ALERT_ERR_CNT_CLR, 1, 2)
169 FIELD(CRCPARCTL0, DFI_ALERT_ERR_INT_CLR, 1, 1)
170 FIELD(CRCPARCTL0, DFI_ALERT_ERR_INT_EN, 1, 0)
171REG32(CRCPARCTL1, 0xc4)
172 FIELD(CRCPARCTL1, DFI_T_PHY_RDLAT, 6, 24)
173 FIELD(CRCPARCTL1, ALERT_WAIT_FOR_SW, 1, 9)
174 FIELD(CRCPARCTL1, CRC_PARITY_RETRY_ENABLE, 1, 8)
175 FIELD(CRCPARCTL1, CRC_INC_DM, 1, 7)
176 FIELD(CRCPARCTL1, CRC_ENABLE, 1, 4)
177 FIELD(CRCPARCTL1, PARITY_ENABLE, 1, 0)
178REG32(CRCPARCTL2, 0xc8)
179 FIELD(CRCPARCTL2, T_PAR_ALERT_PW_MAX, 9, 16)
180 FIELD(CRCPARCTL2, T_CRC_ALERT_PW_MAX, 5, 8)
181 FIELD(CRCPARCTL2, RETRY_FIFO_MAX_HOLD_TIMER_X4, 6, 0)
182REG32(CRCPARSTAT, 0xcc)
183 FIELD(CRCPARSTAT, CMD_IN_ERR_WINDOW, 1, 29)
184 FIELD(CRCPARSTAT, RETRY_OPERATING_MODE, 1, 28)
185 FIELD(CRCPARSTAT, DFI_ALERT_ERR_FATL_CODE, 3, 20)
186 FIELD(CRCPARSTAT, DFI_ALERT_ERR_NO_SW, 1, 19)
187 FIELD(CRCPARSTAT, DFI_ALERT_ERR_MAX_REACHED_INT, 1, 18)
188 FIELD(CRCPARSTAT, DFI_ALERT_ERR_FATL_INT, 1, 17)
189 FIELD(CRCPARSTAT, DFI_ALERT_ERR_INT, 1, 16)
190 FIELD(CRCPARSTAT, DFI_ALERT_ERR_CNT, 16, 0)
191REG32(INIT0, 0xd0)
192 FIELD(INIT0, SKIP_DRAM_INIT, 2, 30)
193 FIELD(INIT0, POST_CKE_X1024, 10, 16)
194 FIELD(INIT0, PRE_CKE_X1024, 12, 0)
195REG32(INIT1, 0xd4)
196 FIELD(INIT1, DRAM_RSTN_X1024, 9, 16)
197 FIELD(INIT1, FINAL_WAIT_X32, 7, 8)
198 FIELD(INIT1, PRE_OCD_X32, 4, 0)
199REG32(INIT2, 0xd8)
200 FIELD(INIT2, IDLE_AFTER_RESET_X32, 8, 8)
201 FIELD(INIT2, MIN_STABLE_CLOCK_X1, 4, 0)
202REG32(INIT3, 0xdc)
203 FIELD(INIT3, MR, 16, 16)
204 FIELD(INIT3, EMR, 16, 0)
205REG32(INIT4, 0xe0)
206 FIELD(INIT4, EMR2, 16, 16)
207 FIELD(INIT4, EMR3, 16, 0)
208REG32(INIT5, 0xe4)
209 FIELD(INIT5, DEV_ZQINIT_X32, 8, 16)
210 FIELD(INIT5, MAX_AUTO_INIT_X1024, 10, 0)
211REG32(INIT6, 0xe8)
212 FIELD(INIT6, MR4, 16, 16)
213 FIELD(INIT6, MR5, 16, 0)
214REG32(INIT7, 0xec)
215 FIELD(INIT7, MR6, 16, 16)
216REG32(DIMMCTL, 0xf0)
217 FIELD(DIMMCTL, DIMM_DIS_BG_MIRRORING, 1, 5)
218 FIELD(DIMMCTL, MRS_BG1_EN, 1, 4)
219 FIELD(DIMMCTL, MRS_A17_EN, 1, 3)
220 FIELD(DIMMCTL, DIMM_OUTPUT_INV_EN, 1, 2)
221 FIELD(DIMMCTL, DIMM_ADDR_MIRR_EN, 1, 1)
222 FIELD(DIMMCTL, DIMM_STAGGER_CS_EN, 1, 0)
223REG32(RANKCTL, 0xf4)
224 FIELD(RANKCTL, DIFF_RANK_WR_GAP, 4, 8)
225 FIELD(RANKCTL, DIFF_RANK_RD_GAP, 4, 4)
226 FIELD(RANKCTL, MAX_RANK_RD, 4, 0)
227REG32(DRAMTMG0, 0x100)
228 FIELD(DRAMTMG0, WR2PRE, 7, 24)
229 FIELD(DRAMTMG0, T_FAW, 6, 16)
230 FIELD(DRAMTMG0, T_RAS_MAX, 7, 8)
231 FIELD(DRAMTMG0, T_RAS_MIN, 6, 0)
232REG32(DRAMTMG1, 0x104)
233 FIELD(DRAMTMG1, T_XP, 5, 16)
234 FIELD(DRAMTMG1, RD2PRE, 5, 8)
235 FIELD(DRAMTMG1, T_RC, 7, 0)
236REG32(DRAMTMG2, 0x108)
237 FIELD(DRAMTMG2, WRITE_LATENCY, 6, 24)
238 FIELD(DRAMTMG2, READ_LATENCY, 6, 16)
239 FIELD(DRAMTMG2, RD2WR, 6, 8)
240 FIELD(DRAMTMG2, WR2RD, 6, 0)
241REG32(DRAMTMG3, 0x10c)
242 FIELD(DRAMTMG3, T_MRW, 10, 20)
243 FIELD(DRAMTMG3, T_MRD, 6, 12)
244 FIELD(DRAMTMG3, T_MOD, 10, 0)
245REG32(DRAMTMG4, 0x110)
246 FIELD(DRAMTMG4, T_RCD, 5, 24)
247 FIELD(DRAMTMG4, T_CCD, 4, 16)
248 FIELD(DRAMTMG4, T_RRD, 4, 8)
249 FIELD(DRAMTMG4, T_RP, 5, 0)
250REG32(DRAMTMG5, 0x114)
251 FIELD(DRAMTMG5, T_CKSRX, 4, 24)
252 FIELD(DRAMTMG5, T_CKSRE, 4, 16)
253 FIELD(DRAMTMG5, T_CKESR, 6, 8)
254 FIELD(DRAMTMG5, T_CKE, 5, 0)
255REG32(DRAMTMG6, 0x118)
256 FIELD(DRAMTMG6, T_CKDPDE, 4, 24)
257 FIELD(DRAMTMG6, T_CKDPDX, 4, 16)
258 FIELD(DRAMTMG6, T_CKCSX, 4, 0)
259REG32(DRAMTMG7, 0x11c)
260 FIELD(DRAMTMG7, T_CKPDE, 4, 8)
261 FIELD(DRAMTMG7, T_CKPDX, 4, 0)
262REG32(DRAMTMG8, 0x120)
263 FIELD(DRAMTMG8, T_XS_FAST_X32, 7, 24)
264 FIELD(DRAMTMG8, T_XS_ABORT_X32, 7, 16)
265 FIELD(DRAMTMG8, T_XS_DLL_X32, 7, 8)
266 FIELD(DRAMTMG8, T_XS_X32, 7, 0)
267REG32(DRAMTMG9, 0x124)
268 FIELD(DRAMTMG9, DDR4_WR_PREAMBLE, 1, 30)
269 FIELD(DRAMTMG9, T_CCD_S, 3, 16)
270 FIELD(DRAMTMG9, T_RRD_S, 4, 8)
271 FIELD(DRAMTMG9, WR2RD_S, 6, 0)
272REG32(DRAMTMG10, 0x128)
273 FIELD(DRAMTMG10, T_SYNC_GEAR, 5, 16)
274 FIELD(DRAMTMG10, T_CMD_GEAR, 5, 8)
275 FIELD(DRAMTMG10, T_GEAR_SETUP, 2, 2)
276 FIELD(DRAMTMG10, T_GEAR_HOLD, 2, 0)
277REG32(DRAMTMG11, 0x12c)
278 FIELD(DRAMTMG11, POST_MPSM_GAP_X32, 7, 24)
279 FIELD(DRAMTMG11, T_MPX_LH, 5, 16)
280 FIELD(DRAMTMG11, T_MPX_S, 2, 8)
281 FIELD(DRAMTMG11, T_CKMPE, 5, 0)
282REG32(DRAMTMG12, 0x130)
283 FIELD(DRAMTMG12, T_CMDCKE, 2, 16)
284 FIELD(DRAMTMG12, T_CKEHCMD, 4, 8)
285 FIELD(DRAMTMG12, T_MRD_PDA, 5, 0)
286REG32(DRAMTMG13, 0x134)
287 FIELD(DRAMTMG13, ODTLOFF, 7, 24)
288 FIELD(DRAMTMG13, T_CCD_MW, 6, 16)
289 FIELD(DRAMTMG13, T_PPD, 3, 0)
290REG32(DRAMTMG14, 0x138)
291 FIELD(DRAMTMG14, T_XSR, 12, 0)
292REG32(ZQCTL0, 0x180)
293 FIELD(ZQCTL0, DIS_AUTO_ZQ, 1, 31)
294 FIELD(ZQCTL0, DIS_SRX_ZQCL, 1, 30)
295 FIELD(ZQCTL0, ZQ_RESISTOR_SHARED, 1, 29)
296 FIELD(ZQCTL0, DIS_MPSMX_ZQCL, 1, 28)
297 FIELD(ZQCTL0, T_ZQ_LONG_NOP, 11, 16)
298 FIELD(ZQCTL0, T_ZQ_SHORT_NOP, 10, 0)
299REG32(ZQCTL1, 0x184)
300 FIELD(ZQCTL1, T_ZQ_RESET_NOP, 10, 20)
301 FIELD(ZQCTL1, T_ZQ_SHORT_INTERVAL_X1024, 20, 0)
302REG32(ZQCTL2, 0x188)
303 FIELD(ZQCTL2, ZQ_RESET, 1, 0)
304REG32(ZQSTAT, 0x18c)
305 FIELD(ZQSTAT, ZQ_RESET_BUSY, 1, 0)
306REG32(DFITMG0, 0x190)
307 FIELD(DFITMG0, DFI_T_CTRL_DELAY, 5, 24)
308 FIELD(DFITMG0, DFI_RDDATA_USE_SDR, 1, 23)
309 FIELD(DFITMG0, DFI_T_RDDATA_EN, 6, 16)
310 FIELD(DFITMG0, DFI_WRDATA_USE_SDR, 1, 15)
311 FIELD(DFITMG0, DFI_TPHY_WRDATA, 6, 8)
312 FIELD(DFITMG0, DFI_TPHY_WRLAT, 6, 0)
313REG32(DFITMG1, 0x194)
314 FIELD(DFITMG1, DFI_T_CMD_LAT, 4, 28)
315 FIELD(DFITMG1, DFI_T_PARIN_LAT, 2, 24)
316 FIELD(DFITMG1, DFI_T_WRDATA_DELAY, 5, 16)
317 FIELD(DFITMG1, DFI_T_DRAM_CLK_DISABLE, 4, 8)
318 FIELD(DFITMG1, DFI_T_DRAM_CLK_ENABLE, 4, 0)
319REG32(DFILPCFG0, 0x198)
320 FIELD(DFILPCFG0, DFI_TLP_RESP, 4, 24)
321 FIELD(DFILPCFG0, DFI_LP_WAKEUP_DPD, 4, 20)
322 FIELD(DFILPCFG0, DFI_LP_EN_DPD, 1, 16)
323 FIELD(DFILPCFG0, DFI_LP_WAKEUP_SR, 4, 12)
324 FIELD(DFILPCFG0, DFI_LP_EN_SR, 1, 8)
325 FIELD(DFILPCFG0, DFI_LP_WAKEUP_PD, 4, 4)
326 FIELD(DFILPCFG0, DFI_LP_EN_PD, 1, 0)
327REG32(DFILPCFG1, 0x19c)
328 FIELD(DFILPCFG1, DFI_LP_WAKEUP_MPSM, 4, 4)
329 FIELD(DFILPCFG1, DFI_LP_EN_MPSM, 1, 0)
330REG32(DFIUPD0, 0x1a0)
331 FIELD(DFIUPD0, DIS_AUTO_CTRLUPD, 1, 31)
332 FIELD(DFIUPD0, DIS_AUTO_CTRLUPD_SRX, 1, 30)
333 FIELD(DFIUPD0, DFI_T_CTRLUP_MAX, 10, 16)
334 FIELD(DFIUPD0, DFI_T_CTRLUP_MIN, 10, 0)
335REG32(DFIUPD1, 0x1a4)
336 FIELD(DFIUPD1, DFI_T_CTRLUPD_INTERVAL_MIN_X1024, 8, 16)
337 FIELD(DFIUPD1, DFI_T_CTRLUPD_INTERVAL_MAX_X1024, 8, 0)
338REG32(DFIUPD2, 0x1a8)
339 FIELD(DFIUPD2, DFI_PHYUPD_EN, 1, 31)
340REG32(DFIMISC, 0x1b0)
341 FIELD(DFIMISC, DFI_DATA_CS_POLARITY, 1, 2)
342 FIELD(DFIMISC, PHY_DBI_MODE, 1, 1)
343 FIELD(DFIMISC, DFI_INIT_COMPLETE_EN, 1, 0)
344REG32(DFITMG2, 0x1b4)
345 FIELD(DFITMG2, DFI_TPHY_RDCSLAT, 6, 8)
346 FIELD(DFITMG2, DFI_TPHY_WRCSLAT, 6, 0)
347REG32(DBICTL, 0x1c0)
348 FIELD(DBICTL, RD_DBI_EN, 1, 2)
349 FIELD(DBICTL, WR_DBI_EN, 1, 1)
350 FIELD(DBICTL, DM_EN, 1, 0)
351REG32(ADDRMAP0, 0x200)
352 FIELD(ADDRMAP0, ADDRMAP_CS_BIT0, 5, 0)
353REG32(ADDRMAP1, 0x204)
354 FIELD(ADDRMAP1, ADDRMAP_BANK_B2, 5, 16)
355 FIELD(ADDRMAP1, ADDRMAP_BANK_B1, 5, 8)
356 FIELD(ADDRMAP1, ADDRMAP_BANK_B0, 5, 0)
357REG32(ADDRMAP2, 0x208)
358 FIELD(ADDRMAP2, ADDRMAP_COL_B5, 4, 24)
359 FIELD(ADDRMAP2, ADDRMAP_COL_B4, 4, 16)
360 FIELD(ADDRMAP2, ADDRMAP_COL_B3, 4, 8)
361 FIELD(ADDRMAP2, ADDRMAP_COL_B2, 4, 0)
362REG32(ADDRMAP3, 0x20c)
363 FIELD(ADDRMAP3, ADDRMAP_COL_B9, 4, 24)
364 FIELD(ADDRMAP3, ADDRMAP_COL_B8, 4, 16)
365 FIELD(ADDRMAP3, ADDRMAP_COL_B7, 4, 8)
366 FIELD(ADDRMAP3, ADDRMAP_COL_B6, 4, 0)
367REG32(ADDRMAP4, 0x210)
368 FIELD(ADDRMAP4, ADDRMAP_COL_B11, 4, 8)
369 FIELD(ADDRMAP4, ADDRMAP_COL_B10, 4, 0)
370REG32(ADDRMAP5, 0x214)
371 FIELD(ADDRMAP5, ADDRMAP_ROW_B11, 4, 24)
372 FIELD(ADDRMAP5, ADDRMAP_ROW_B2_10, 4, 16)
373 FIELD(ADDRMAP5, ADDRMAP_ROW_B1, 4, 8)
374 FIELD(ADDRMAP5, ADDRMAP_ROW_B0, 4, 0)
375REG32(ADDRMAP6, 0x218)
376 FIELD(ADDRMAP6, LPDDR3_6GB_12GB, 1, 31)
377 FIELD(ADDRMAP6, ADDRMAP_ROW_B15, 4, 24)
378 FIELD(ADDRMAP6, ADDRMAP_ROW_B14, 4, 16)
379 FIELD(ADDRMAP6, ADDRMAP_ROW_B13, 4, 8)
380 FIELD(ADDRMAP6, ADDRMAP_ROW_B12, 4, 0)
381REG32(ADDRMAP7, 0x21c)
382 FIELD(ADDRMAP7, ADDRMAP_ROW_B17, 4, 8)
383 FIELD(ADDRMAP7, ADDRMAP_ROW_B16, 4, 0)
384REG32(ADDRMAP8, 0x220)
385 FIELD(ADDRMAP8, ADDRMAP_BG_B1, 5, 8)
386 FIELD(ADDRMAP8, ADDRMAP_BG_B0, 5, 0)
387REG32(ADDRMAP9, 0x224)
388 FIELD(ADDRMAP9, ADDRMAP_ROW_B5, 4, 24)
389 FIELD(ADDRMAP9, ADDRMAP_ROW_B4, 4, 16)
390 FIELD(ADDRMAP9, ADDRMAP_ROW_B3, 4, 8)
391 FIELD(ADDRMAP9, ADDRMAP_ROW_B2, 4, 0)
392REG32(ADDRMAP10, 0x228)
393 FIELD(ADDRMAP10, ADDRMAP_ROW_B9, 4, 24)
394 FIELD(ADDRMAP10, ADDRMAP_ROW_B8, 4, 16)
395 FIELD(ADDRMAP10, ADDRMAP_ROW_B7, 4, 8)
396 FIELD(ADDRMAP10, ADDRMAP_ROW_B6, 4, 0)
397REG32(ADDRMAP11, 0x22c)
398 FIELD(ADDRMAP11, ADDRMAP_ROW_B10, 4, 0)
399REG32(ODTCFG, 0x240)
400 FIELD(ODTCFG, WR_ODT_HOLD, 4, 24)
401 FIELD(ODTCFG, WR_ODT_DELAY, 5, 16)
402 FIELD(ODTCFG, RD_ODT_HOLD, 4, 8)
403 FIELD(ODTCFG, RD_ODT_DELAY, 5, 2)
404REG32(ODTMAP, 0x244)
405 FIELD(ODTMAP, RANK1_RD_ODT, 2, 12)
406 FIELD(ODTMAP, RANK1_WR_ODT, 2, 8)
407 FIELD(ODTMAP, RANK0_RD_ODT, 2, 4)
408 FIELD(ODTMAP, RANK0_WR_ODT, 2, 0)
409REG32(SCHED, 0x250)
410 FIELD(SCHED, RDWR_IDLE_GAP, 7, 24)
411 FIELD(SCHED, GO2CRITICAL_HYSTERESIS, 8, 16)
412 FIELD(SCHED, LPR_NUM_ENTRIES, 6, 8)
413 FIELD(SCHED, PAGECLOSE, 1, 2)
414 FIELD(SCHED, PREFER_WRITE, 1, 1)
415 FIELD(SCHED, FORCE_LOW_PRI_N, 1, 0)
416REG32(SCHED1, 0x254)
417 FIELD(SCHED1, PAGECLOSE_TIMER, 8, 0)
418REG32(PERFHPR1, 0x25c)
419 FIELD(PERFHPR1, HPR_XACT_RUN_LENGTH, 8, 24)
420 FIELD(PERFHPR1, HPR_MAX_STARVE, 16, 0)
421REG32(PERFLPR1, 0x264)
422 FIELD(PERFLPR1, LPR_XACT_RUN_LENGTH, 8, 24)
423 FIELD(PERFLPR1, LPR_MAX_STARVE, 16, 0)
424REG32(PERFWR1, 0x26c)
425 FIELD(PERFWR1, W_XACT_RUN_LENGTH, 8, 24)
426 FIELD(PERFWR1, W_MAX_STARVE, 16, 0)
427REG32(PERFVPR1, 0x274)
428 FIELD(PERFVPR1, VPR_TIMEOUT_RANGE, 11, 0)
429REG32(PERFVPW1, 0x278)
430 FIELD(PERFVPW1, VPW_TIMEOUT_RANGE, 11, 0)
431REG32(DQMAP0, 0x280)
432 FIELD(DQMAP0, DQ_NIBBLE_MAP_12_15, 8, 24)
433 FIELD(DQMAP0, DQ_NIBBLE_MAP_8_11, 8, 16)
434 FIELD(DQMAP0, DQ_NIBBLE_MAP_4_7, 8, 8)
435 FIELD(DQMAP0, DQ_NIBBLE_MAP_0_3, 8, 0)
436REG32(DQMAP1, 0x284)
437 FIELD(DQMAP1, DQ_NIBBLE_MAP_28_31, 8, 24)
438 FIELD(DQMAP1, DQ_NIBBLE_MAP_24_27, 8, 16)
439 FIELD(DQMAP1, DQ_NIBBLE_MAP_20_23, 8, 8)
440 FIELD(DQMAP1, DQ_NIBBLE_MAP_16_19, 8, 0)
441REG32(DQMAP2, 0x288)
442 FIELD(DQMAP2, DQ_NIBBLE_MAP_44_47, 8, 24)
443 FIELD(DQMAP2, DQ_NIBBLE_MAP_40_43, 8, 16)
444 FIELD(DQMAP2, DQ_NIBBLE_MAP_36_39, 8, 8)
445 FIELD(DQMAP2, DQ_NIBBLE_MAP_32_35, 8, 0)
446REG32(DQMAP3, 0x28c)
447 FIELD(DQMAP3, DQ_NIBBLE_MAP_60_63, 8, 24)
448 FIELD(DQMAP3, DQ_NIBBLE_MAP_56_59, 8, 16)
449 FIELD(DQMAP3, DQ_NIBBLE_MAP_52_55, 8, 8)
450 FIELD(DQMAP3, DQ_NIBBLE_MAP_48_51, 8, 0)
451REG32(DQMAP4, 0x290)
452 FIELD(DQMAP4, DQ_NIBBLE_MAP_CB_4_7, 8, 8)
453 FIELD(DQMAP4, DQ_NIBBLE_MAP_CB_0_3, 8, 0)
454REG32(DQMAP5, 0x294)
455 FIELD(DQMAP5, DIS_DQ_RANK_SWAP, 1, 0)
456REG32(DBG0, 0x300)
457 FIELD(DBG0, DIS_COLLISION_PAGE_OPT, 1, 4)
458 FIELD(DBG0, DIS_WC, 1, 0)
459REG32(DBG1, 0x304)
460 FIELD(DBG1, DIS_HIF, 1, 1)
461 FIELD(DBG1, DIS_DQ, 1, 0)
462REG32(DBGCAM, 0x308)
463 FIELD(DBGCAM, DBG_STALL_RD, 1, 31)
464 FIELD(DBGCAM, DBG_STALL_WR, 1, 30)
465 FIELD(DBGCAM, WR_DATA_PIPELINE_EMPTY, 1, 29)
466 FIELD(DBGCAM, RD_DATA_PIPELINE_EMPTY, 1, 28)
467 FIELD(DBGCAM, DBG_WR_Q_EMPTY, 1, 26)
468 FIELD(DBGCAM, DBG_RD_Q_EMPTY, 1, 25)
469 FIELD(DBGCAM, DBG_STALL, 1, 24)
470 FIELD(DBGCAM, DBG_W_Q_DEPTH, 7, 16)
471 FIELD(DBGCAM, DBG_LPR_Q_DEPTH, 7, 8)
472 FIELD(DBGCAM, DBG_HPR_Q_DEPTH, 7, 0)
473REG32(DBGCMD, 0x30c)
474 FIELD(DBGCMD, HW_REF_ZQ_EN, 1, 31)
475 FIELD(DBGCMD, CTRLUPD, 1, 5)
476 FIELD(DBGCMD, ZQ_CALIB_SHORT, 1, 4)
477 FIELD(DBGCMD, RANK1_REFRESH, 1, 1)
478 FIELD(DBGCMD, RANK0_REFRESH, 1, 0)
479REG32(DBGSTAT, 0x310)
480 FIELD(DBGSTAT, CTRLUPD_BUSY, 1, 5)
481 FIELD(DBGSTAT, ZQ_CALIB_SHORT_BUSY, 1, 4)
482 FIELD(DBGSTAT, RANK1_REFRESH_BUSY, 1, 1)
483 FIELD(DBGSTAT, RANK0_REFRESH_BUSY, 1, 0)
484REG32(SWCTL, 0x320)
485 FIELD(SWCTL, SW_DONE, 1, 0)
486REG32(SWSTAT, 0x324)
487 FIELD(SWSTAT, SW_DONE_ACK, 1, 0)
488REG32(POISONCFG, 0x36c)
489 FIELD(POISONCFG, RD_POISON_INTR_CLR, 1, 24)
490 FIELD(POISONCFG, RD_POISON_INTR_EN, 1, 20)
491 FIELD(POISONCFG, RD_POISON_SLVERR_EN, 1, 16)
492 FIELD(POISONCFG, WR_POISON_INTR_CLR, 1, 8)
493 FIELD(POISONCFG, WR_POISON_INTR_EN, 1, 4)
494 FIELD(POISONCFG, WR_POISON_SLVERR_EN, 1, 0)
495REG32(POISONSTAT, 0x370)
496 FIELD(POISONSTAT, RD_POISON_INTR_5, 1, 21)
497 FIELD(POISONSTAT, RD_POISON_INTR_4, 1, 20)
498 FIELD(POISONSTAT, RD_POISON_INTR_3, 1, 19)
499 FIELD(POISONSTAT, RD_POISON_INTR_2, 1, 18)
500 FIELD(POISONSTAT, RD_POISON_INTR_1, 1, 17)
501 FIELD(POISONSTAT, RD_POISON_INTR_0, 1, 16)
502 FIELD(POISONSTAT, WR_POISON_INTR_5, 1, 5)
503 FIELD(POISONSTAT, WR_POISON_INTR_4, 1, 4)
504 FIELD(POISONSTAT, WR_POISON_INTR_3, 1, 3)
505 FIELD(POISONSTAT, WR_POISON_INTR_2, 1, 2)
506 FIELD(POISONSTAT, WR_POISON_INTR_1, 1, 1)
507 FIELD(POISONSTAT, WR_POISON_INTR_0, 1, 0)
508REG32(PSTAT, 0x3fc)
509 FIELD(PSTAT, WR_PORT_BUSY_5, 1, 21)
510 FIELD(PSTAT, WR_PORT_BUSY_4, 1, 20)
511 FIELD(PSTAT, WR_PORT_BUSY_3, 1, 19)
512 FIELD(PSTAT, WR_PORT_BUSY_2, 1, 18)
513 FIELD(PSTAT, WR_PORT_BUSY_1, 1, 17)
514 FIELD(PSTAT, WR_PORT_BUSY_0, 1, 16)
515 FIELD(PSTAT, RD_PORT_BUSY_5, 1, 5)
516 FIELD(PSTAT, RD_PORT_BUSY_4, 1, 4)
517 FIELD(PSTAT, RD_PORT_BUSY_3, 1, 3)
518 FIELD(PSTAT, RD_PORT_BUSY_2, 1, 2)
519 FIELD(PSTAT, RD_PORT_BUSY_1, 1, 1)
520 FIELD(PSTAT, RD_PORT_BUSY_0, 1, 0)
521REG32(PCCFG, 0x400)
522 FIELD(PCCFG, BL_EXP_MODE, 1, 8)
523 FIELD(PCCFG, PAGEMATCH_LIMIT, 1, 4)
524 FIELD(PCCFG, GO2CRITICAL_EN, 1, 0)
525REG32(PCFGR_0, 0x404)
526 FIELD(PCFGR_0, RD_PORT_PAGEMATCH_EN, 1, 14)
527 FIELD(PCFGR_0, RD_PORT_URGENT_EN, 1, 13)
528 FIELD(PCFGR_0, RD_PORT_AGING_EN, 1, 12)
529 FIELD(PCFGR_0, RD_PORT_PRIORITY, 10, 0)
530REG32(PCFGW_0, 0x408)
531 FIELD(PCFGW_0, WR_PORT_PAGEMATCH_EN, 1, 14)
532 FIELD(PCFGW_0, WR_PORT_URGENT_EN, 1, 13)
533 FIELD(PCFGW_0, WR_PORT_AGING_EN, 1, 12)
534 FIELD(PCFGW_0, WR_PORT_PRIORITY, 10, 0)
535REG32(PCTRL_0, 0x490)
536 FIELD(PCTRL_0, PORT_EN, 1, 0)
537REG32(PCFGQOS0_0, 0x494)
538 FIELD(PCFGQOS0_0, RQOS_MAP_REGION1, 2, 20)
539 FIELD(PCFGQOS0_0, RQOS_MAP_REGION0, 2, 16)
540 FIELD(PCFGQOS0_0, RQOS_MAP_LEVEL1, 4, 0)
541REG32(PCFGQOS1_0, 0x498)
542 FIELD(PCFGQOS1_0, RQOS_MAP_TIMEOUTR, 11, 16)
543 FIELD(PCFGQOS1_0, RQOS_MAP_TIMEOUTB, 11, 0)
544REG32(PCFGWQOS0_0, 0x49c)
545 FIELD(PCFGWQOS0_0, WQOS_MAP_REGION1, 2, 20)
546 FIELD(PCFGWQOS0_0, WQOS_MAP_REGION0, 2, 16)
547 FIELD(PCFGWQOS0_0, WQOS_MAP_LEVEL, 4, 0)
548REG32(PCFGWQOS1_0, 0x4a0)
549 FIELD(PCFGWQOS1_0, WQOS_MAP_TIMEOUT, 11, 0)
550REG32(PCFGR_1, 0x4b4)
551 FIELD(PCFGR_1, RD_PORT_PAGEMATCH_EN, 1, 14)
552 FIELD(PCFGR_1, RD_PORT_URGENT_EN, 1, 13)
553 FIELD(PCFGR_1, RD_PORT_AGING_EN, 1, 12)
554 FIELD(PCFGR_1, RD_PORT_PRIORITY, 10, 0)
555REG32(PCFGW_1, 0x4b8)
556 FIELD(PCFGW_1, WR_PORT_PAGEMATCH_EN, 1, 14)
557 FIELD(PCFGW_1, WR_PORT_URGENT_EN, 1, 13)
558 FIELD(PCFGW_1, WR_PORT_AGING_EN, 1, 12)
559 FIELD(PCFGW_1, WR_PORT_PRIORITY, 10, 0)
560REG32(PCTRL_1, 0x540)
561 FIELD(PCTRL_1, PORT_EN, 1, 0)
562REG32(PCFGQOS0_1, 0x544)
563 FIELD(PCFGQOS0_1, RQOS_MAP_REGION2, 2, 24)
564 FIELD(PCFGQOS0_1, RQOS_MAP_REGION1, 2, 20)
565 FIELD(PCFGQOS0_1, RQOS_MAP_REGION0, 2, 16)
566 FIELD(PCFGQOS0_1, RQOS_MAP_LEVEL2, 4, 8)
567 FIELD(PCFGQOS0_1, RQOS_MAP_LEVEL1, 4, 0)
568REG32(PCFGQOS1_1, 0x548)
569 FIELD(PCFGQOS1_1, RQOS_MAP_TIMEOUTR, 11, 16)
570 FIELD(PCFGQOS1_1, RQOS_MAP_TIMEOUTB, 11, 0)
571REG32(PCFGWQOS0_1, 0x54c)
572 FIELD(PCFGWQOS0_1, WQOS_MAP_REGION1, 2, 20)
573 FIELD(PCFGWQOS0_1, WQOS_MAP_REGION0, 2, 16)
574 FIELD(PCFGWQOS0_1, WQOS_MAP_LEVEL, 4, 0)
575REG32(PCFGWQOS1_1, 0x550)
576 FIELD(PCFGWQOS1_1, WQOS_MAP_TIMEOUT, 11, 0)
577REG32(PCFGR_2, 0x564)
578 FIELD(PCFGR_2, RD_PORT_PAGEMATCH_EN, 1, 14)
579 FIELD(PCFGR_2, RD_PORT_URGENT_EN, 1, 13)
580 FIELD(PCFGR_2, RD_PORT_AGING_EN, 1, 12)
581 FIELD(PCFGR_2, RD_PORT_PRIORITY, 10, 0)
582REG32(PCFGW_2, 0x568)
583 FIELD(PCFGW_2, WR_PORT_PAGEMATCH_EN, 1, 14)
584 FIELD(PCFGW_2, WR_PORT_URGENT_EN, 1, 13)
585 FIELD(PCFGW_2, WR_PORT_AGING_EN, 1, 12)
586 FIELD(PCFGW_2, WR_PORT_PRIORITY, 10, 0)
587REG32(PCTRL_2, 0x5f0)
588 FIELD(PCTRL_2, PORT_EN, 1, 0)
589REG32(PCFGQOS0_2, 0x5f4)
590 FIELD(PCFGQOS0_2, RQOS_MAP_REGION2, 2, 24)
591 FIELD(PCFGQOS0_2, RQOS_MAP_REGION1, 2, 20)
592 FIELD(PCFGQOS0_2, RQOS_MAP_REGION0, 2, 16)
593 FIELD(PCFGQOS0_2, RQOS_MAP_LEVEL2, 4, 8)
594 FIELD(PCFGQOS0_2, RQOS_MAP_LEVEL1, 4, 0)
595REG32(PCFGQOS1_2, 0x5f8)
596 FIELD(PCFGQOS1_2, RQOS_MAP_TIMEOUTR, 11, 16)
597 FIELD(PCFGQOS1_2, RQOS_MAP_TIMEOUTB, 11, 0)
598REG32(PCFGWQOS0_2, 0x5fc)
599 FIELD(PCFGWQOS0_2, WQOS_MAP_REGION1, 2, 20)
600 FIELD(PCFGWQOS0_2, WQOS_MAP_REGION0, 2, 16)
601 FIELD(PCFGWQOS0_2, WQOS_MAP_LEVEL, 4, 0)
602REG32(PCFGWQOS1_2, 0x600)
603 FIELD(PCFGWQOS1_2, WQOS_MAP_TIMEOUT, 11, 0)
604REG32(PCFGR_3, 0x614)
605 FIELD(PCFGR_3, RD_PORT_PAGEMATCH_EN, 1, 14)
606 FIELD(PCFGR_3, RD_PORT_URGENT_EN, 1, 13)
607 FIELD(PCFGR_3, RD_PORT_AGING_EN, 1, 12)
608 FIELD(PCFGR_3, RD_PORT_PRIORITY, 10, 0)
609REG32(PCFGW_3, 0x618)
610 FIELD(PCFGW_3, WR_PORT_PAGEMATCH_EN, 1, 14)
611 FIELD(PCFGW_3, WR_PORT_URGENT_EN, 1, 13)
612 FIELD(PCFGW_3, WR_PORT_AGING_EN, 1, 12)
613 FIELD(PCFGW_3, WR_PORT_PRIORITY, 10, 0)
614REG32(PCTRL_3, 0x6a0)
615 FIELD(PCTRL_3, PORT_EN, 1, 0)
616REG32(PCFGQOS0_3, 0x6a4)
617 FIELD(PCFGQOS0_3, RQOS_MAP_REGION1, 2, 20)
618 FIELD(PCFGQOS0_3, RQOS_MAP_REGION0, 2, 16)
619 FIELD(PCFGQOS0_3, RQOS_MAP_LEVEL1, 4, 0)
620REG32(PCFGQOS1_3, 0x6a8)
621 FIELD(PCFGQOS1_3, RQOS_MAP_TIMEOUTR, 11, 16)
622 FIELD(PCFGQOS1_3, RQOS_MAP_TIMEOUTB, 11, 0)
623REG32(PCFGWQOS0_3, 0x6ac)
624 FIELD(PCFGWQOS0_3, WQOS_MAP_REGION1, 2, 20)
625 FIELD(PCFGWQOS0_3, WQOS_MAP_REGION0, 2, 16)
626 FIELD(PCFGWQOS0_3, WQOS_MAP_LEVEL, 4, 0)
627REG32(PCFGWQOS1_3, 0x6b0)
628 FIELD(PCFGWQOS1_3, WQOS_MAP_TIMEOUT, 11, 0)
629REG32(PCFGR_4, 0x6c4)
630 FIELD(PCFGR_4, RD_PORT_PAGEMATCH_EN, 1, 14)
631 FIELD(PCFGR_4, RD_PORT_URGENT_EN, 1, 13)
632 FIELD(PCFGR_4, RD_PORT_AGING_EN, 1, 12)
633 FIELD(PCFGR_4, RD_PORT_PRIORITY, 10, 0)
634REG32(PCFGW_4, 0x6c8)
635 FIELD(PCFGW_4, WR_PORT_PAGEMATCH_EN, 1, 14)
636 FIELD(PCFGW_4, WR_PORT_URGENT_EN, 1, 13)
637 FIELD(PCFGW_4, WR_PORT_AGING_EN, 1, 12)
638 FIELD(PCFGW_4, WR_PORT_PRIORITY, 10, 0)
639REG32(PCTRL_4, 0x750)
640 FIELD(PCTRL_4, PORT_EN, 1, 0)
641REG32(PCFGQOS0_4, 0x754)
642 FIELD(PCFGQOS0_4, RQOS_MAP_REGION1, 2, 20)
643 FIELD(PCFGQOS0_4, RQOS_MAP_REGION0, 2, 16)
644 FIELD(PCFGQOS0_4, RQOS_MAP_LEVEL1, 4, 0)
645REG32(PCFGQOS1_4, 0x758)
646 FIELD(PCFGQOS1_4, RQOS_MAP_TIMEOUTR, 11, 16)
647 FIELD(PCFGQOS1_4, RQOS_MAP_TIMEOUTB, 11, 0)
648REG32(PCFGWQOS0_4, 0x75c)
649 FIELD(PCFGWQOS0_4, WQOS_MAP_REGION1, 2, 20)
650 FIELD(PCFGWQOS0_4, WQOS_MAP_REGION0, 2, 16)
651 FIELD(PCFGWQOS0_4, WQOS_MAP_LEVEL, 4, 0)
652REG32(PCFGWQOS1_4, 0x760)
653 FIELD(PCFGWQOS1_4, WQOS_MAP_TIMEOUT, 11, 0)
654REG32(PCFGR_5, 0x774)
655 FIELD(PCFGR_5, RD_PORT_PAGEMATCH_EN, 1, 14)
656 FIELD(PCFGR_5, RD_PORT_URGENT_EN, 1, 13)
657 FIELD(PCFGR_5, RD_PORT_AGING_EN, 1, 12)
658 FIELD(PCFGR_5, RD_PORT_PRIORITY, 10, 0)
659REG32(PCFGW_5, 0x778)
660 FIELD(PCFGW_5, WR_PORT_PAGEMATCH_EN, 1, 14)
661 FIELD(PCFGW_5, WR_PORT_URGENT_EN, 1, 13)
662 FIELD(PCFGW_5, WR_PORT_AGING_EN, 1, 12)
663 FIELD(PCFGW_5, WR_PORT_PRIORITY, 10, 0)
664REG32(PCTRL_5, 0x800)
665 FIELD(PCTRL_5, PORT_EN, 1, 0)
666REG32(PCFGQOS0_5, 0x804)
667 FIELD(PCFGQOS0_5, RQOS_MAP_REGION1, 2, 20)
668 FIELD(PCFGQOS0_5, RQOS_MAP_REGION0, 2, 16)
669 FIELD(PCFGQOS0_5, RQOS_MAP_LEVEL1, 4, 0)
670REG32(PCFGQOS1_5, 0x808)
671 FIELD(PCFGQOS1_5, RQOS_MAP_TIMEOUTR, 11, 16)
672 FIELD(PCFGQOS1_5, RQOS_MAP_TIMEOUTB, 11, 0)
673REG32(PCFGWQOS0_5, 0x80c)
674 FIELD(PCFGWQOS0_5, WQOS_MAP_REGION1, 2, 20)
675 FIELD(PCFGWQOS0_5, WQOS_MAP_REGION0, 2, 16)
676 FIELD(PCFGWQOS0_5, WQOS_MAP_LEVEL, 4, 0)
677REG32(PCFGWQOS1_5, 0x810)
678 FIELD(PCFGWQOS1_5, WQOS_MAP_TIMEOUT, 11, 0)
679REG32(SARBASE0, 0xf04)
680 FIELD(SARBASE0, BASE_ADDR, 9, 0)
681REG32(SARSIZE0, 0xf08)
682 FIELD(SARSIZE0, NBLOCKS, 8, 0)
683REG32(SARBASE1, 0xf0c)
684 FIELD(SARBASE1, BASE_ADDR, 9, 0)
685REG32(SARSIZE1, 0xf10)
686 FIELD(SARSIZE1, NBLOCKS, 8, 0)
687REG32(DERATEINT_SHADOW, 0x2024)
688REG32(RFSHCTL0_SHADOW, 0x2050)
689 FIELD(RFSHCTL0_SHADOW, REFRESH_MARGIN, 4, 20)
690 FIELD(RFSHCTL0_SHADOW, REFRESH_TO_X32, 5, 12)
691 FIELD(RFSHCTL0_SHADOW, REFRESH_BURST, 5, 4)
692 FIELD(RFSHCTL0_SHADOW, PER_BANK_REFRESH, 1, 2)
693REG32(RFSHTMG_SHADOW, 0x2064)
694 FIELD(RFSHTMG_SHADOW, T_RFC_NOM_X32, 12, 16)
695 FIELD(RFSHTMG_SHADOW, LPDDR3_TREFBW_EN, 1, 15)
696 FIELD(RFSHTMG_SHADOW, T_RFC_MIN, 10, 0)
697REG32(INIT3_SHADOW, 0x20dc)
698 FIELD(INIT3_SHADOW, MR, 16, 16)
699 FIELD(INIT3_SHADOW, EMR, 16, 0)
700REG32(INIT4_SHADOW, 0x20e0)
701 FIELD(INIT4_SHADOW, EMR2, 16, 16)
702 FIELD(INIT4_SHADOW, EMR3, 16, 0)
703REG32(INIT6_SHADOW, 0x20e8)
704 FIELD(INIT6_SHADOW, MR4, 16, 16)
705 FIELD(INIT6_SHADOW, MR5, 16, 0)
706REG32(INIT7_SHADOW, 0x20ec)
707 FIELD(INIT7_SHADOW, MR6, 16, 16)
708REG32(DRAMTMG0_SHADOW, 0x2100)
709 FIELD(DRAMTMG0_SHADOW, WR2PRE, 7, 24)
710 FIELD(DRAMTMG0_SHADOW, T_FAW, 6, 16)
711 FIELD(DRAMTMG0_SHADOW, T_RAS_MAX, 7, 8)
712 FIELD(DRAMTMG0_SHADOW, T_RAS_MIN, 6, 0)
713REG32(DRAMTMG1_SHADOW, 0x2104)
714 FIELD(DRAMTMG1_SHADOW, T_XP, 5, 16)
715 FIELD(DRAMTMG1_SHADOW, RD2PRE, 5, 8)
716 FIELD(DRAMTMG1_SHADOW, T_RC, 7, 0)
717REG32(DRAMTMG2_SHADOW, 0x2108)
718 FIELD(DRAMTMG2_SHADOW, WRITE_LATENCY, 6, 24)
719 FIELD(DRAMTMG2_SHADOW, READ_LATENCY, 6, 16)
720 FIELD(DRAMTMG2_SHADOW, RD2WR, 6, 8)
721 FIELD(DRAMTMG2_SHADOW, WR2RD, 6, 0)
722REG32(DRAMTMG3_SHADOW, 0x210c)
723 FIELD(DRAMTMG3_SHADOW, T_MRW, 10, 20)
724 FIELD(DRAMTMG3_SHADOW, T_MRD, 6, 12)
725 FIELD(DRAMTMG3_SHADOW, T_MOD, 10, 0)
726REG32(DRAMTMG4_SHADOW, 0x2110)
727 FIELD(DRAMTMG4_SHADOW, T_RCD, 5, 24)
728 FIELD(DRAMTMG4_SHADOW, T_CCD, 4, 16)
729 FIELD(DRAMTMG4_SHADOW, T_RRD, 4, 8)
730 FIELD(DRAMTMG4_SHADOW, T_RP, 5, 0)
731REG32(DRAMTMG5_SHADOW, 0x2114)
732 FIELD(DRAMTMG5_SHADOW, T_CKSRX, 4, 24)
733 FIELD(DRAMTMG5_SHADOW, T_CKSRE, 4, 16)
734 FIELD(DRAMTMG5_SHADOW, T_CKESR, 6, 8)
735 FIELD(DRAMTMG5_SHADOW, T_CKE, 5, 0)
736REG32(DRAMTMG6_SHADOW, 0x2118)
737 FIELD(DRAMTMG6_SHADOW, T_CKDPDE, 4, 24)
738 FIELD(DRAMTMG6_SHADOW, T_CKDPDX, 4, 16)
739 FIELD(DRAMTMG6_SHADOW, T_CKCSX, 4, 0)
740REG32(DRAMTMG7_SHADOW, 0x211c)
741 FIELD(DRAMTMG7_SHADOW, T_CKPDE, 4, 8)
742 FIELD(DRAMTMG7_SHADOW, T_CKPDX, 4, 0)
743REG32(DRAMTMG8_SHADOW, 0x2120)
744 FIELD(DRAMTMG8_SHADOW, T_XS_FAST_X32, 7, 24)
745 FIELD(DRAMTMG8_SHADOW, T_XS_ABORT_X32, 7, 16)
746 FIELD(DRAMTMG8_SHADOW, T_XS_DLL_X32, 7, 8)
747 FIELD(DRAMTMG8_SHADOW, T_XS_X32, 7, 0)
748REG32(DRAMTMG9_SHADOW, 0x2124)
749 FIELD(DRAMTMG9_SHADOW, DDR4_WR_PREAMBLE, 1, 30)
750 FIELD(DRAMTMG9_SHADOW, T_CCD_S, 3, 16)
751 FIELD(DRAMTMG9_SHADOW, T_RRD_S, 4, 8)
752 FIELD(DRAMTMG9_SHADOW, WR2RD_S, 6, 0)
753REG32(DRAMTMG10_SHADOW, 0x2128)
754 FIELD(DRAMTMG10_SHADOW, T_SYNC_GEAR, 5, 16)
755 FIELD(DRAMTMG10_SHADOW, T_CMD_GEAR, 5, 8)
756 FIELD(DRAMTMG10_SHADOW, T_GEAR_SETUP, 2, 2)
757 FIELD(DRAMTMG10_SHADOW, T_GEAR_HOLD, 2, 0)
758REG32(DRAMTMG11_SHADOW, 0x212c)
759 FIELD(DRAMTMG11_SHADOW, POST_MPSM_GAP_X32, 7, 24)
760 FIELD(DRAMTMG11_SHADOW, T_MPX_LH, 5, 16)
761 FIELD(DRAMTMG11_SHADOW, T_MPX_S, 2, 8)
762 FIELD(DRAMTMG11_SHADOW, T_CKMPE, 5, 0)
763REG32(DRAMTMG12_SHADOW, 0x2130)
764 FIELD(DRAMTMG12_SHADOW, T_CMDCKE, 2, 16)
765 FIELD(DRAMTMG12_SHADOW, T_CKEHCMD, 4, 8)
766 FIELD(DRAMTMG12_SHADOW, T_MRD_PDA, 5, 0)
767REG32(DRAMTMG13_SHADOW, 0x2134)
768 FIELD(DRAMTMG13_SHADOW, ODTLOFF, 7, 24)
769 FIELD(DRAMTMG13_SHADOW, T_CCD_MW, 6, 16)
770 FIELD(DRAMTMG13_SHADOW, T_PPD, 3, 0)
771REG32(DRAMTMG14_SHADOW, 0x2138)
772 FIELD(DRAMTMG14_SHADOW, T_XSR, 12, 0)
773REG32(ZQCTL0_SHADOW, 0x2180)
774 FIELD(ZQCTL0_SHADOW, DIS_AUTO_ZQ, 1, 31)
775 FIELD(ZQCTL0_SHADOW, DIS_SRX_ZQCL, 1, 30)
776 FIELD(ZQCTL0_SHADOW, ZQ_RESISTOR_SHARED, 1, 29)
777 FIELD(ZQCTL0_SHADOW, DIS_MPSMX_ZQCL, 1, 28)
778 FIELD(ZQCTL0_SHADOW, T_ZQ_LONG_NOP, 11, 16)
779 FIELD(ZQCTL0_SHADOW, T_ZQ_SHORT_NOP, 10, 0)
780REG32(DFITMG0_SHADOW, 0x2190)
781 FIELD(DFITMG0_SHADOW, DFI_T_CTRL_DELAY, 5, 24)
782 FIELD(DFITMG0_SHADOW, DFI_RDDATA_USE_SDR, 1, 23)
783 FIELD(DFITMG0_SHADOW, DFI_T_RDDATA_EN, 6, 16)
784 FIELD(DFITMG0_SHADOW, DFI_WRDATA_USE_SDR, 1, 15)
785 FIELD(DFITMG0_SHADOW, DFI_TPHY_WRDATA, 6, 8)
786 FIELD(DFITMG0_SHADOW, DFI_TPHY_WRLAT, 6, 0)
787REG32(DFITMG1_SHADOW, 0x2194)
788 FIELD(DFITMG1_SHADOW, DFI_T_CMD_LAT, 4, 28)
789 FIELD(DFITMG1_SHADOW, DFI_T_PARIN_LAT, 2, 24)
790 FIELD(DFITMG1_SHADOW, DFI_T_WRDATA_DELAY, 5, 16)
791 FIELD(DFITMG1_SHADOW, DFI_T_DRAM_CLK_DISABLE, 4, 8)
792 FIELD(DFITMG1_SHADOW, DFI_T_DRAM_CLK_ENABLE, 4, 0)
793REG32(DFITMG2_SHADOW, 0x21b4)
794 FIELD(DFITMG2_SHADOW, DFI_TPHY_RDCSLAT, 6, 8)
795 FIELD(DFITMG2_SHADOW, DFI_TPHY_WRCSLAT, 6, 0)
796REG32(ODTCFG_SHADOW, 0x2240)
797 FIELD(ODTCFG_SHADOW, WR_ODT_HOLD, 4, 24)
798 FIELD(ODTCFG_SHADOW, WR_ODT_DELAY, 5, 16)
799 FIELD(ODTCFG_SHADOW, RD_ODT_HOLD, 4, 8)
800 FIELD(ODTCFG_SHADOW, RD_ODT_DELAY, 5, 2)
801
802#define R_MAX (R_ODTCFG_SHADOW + 1)
803
804#define R_STAT_OPERATING_MODE_SR 3
805#define R_STAT_OPERATING_MODE_NORMAL 1
806
807#define R_STAT_SELFREF_TYPE_SRSW 2
808#define R_STAT_SELFREF_TYPE_NONE 0
809
810typedef struct DDRC {
811 SysBusDevice parent_obj;
812 MemoryRegion iomem;
813
814 uint32_t regs[R_MAX];
815 RegisterInfo regs_info[R_MAX];
816} DDRC;
817
818static void ddrc_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
819{
820 DDRC *s = XILINX_DDRC(reg->opaque);
821
822
823
824
825
826 if (val & R_PWRCTL_SELFREF_SW_MASK) {
827 AF_DP32(s->regs, STAT, OPERATING_MODE, R_STAT_OPERATING_MODE_SR);
828 AF_DP32(s->regs, STAT, SELFREF_TYPE, R_STAT_SELFREF_TYPE_SRSW);
829 }
830
831
832 if (!(val & R_PWRCTL_SELFREF_SW_MASK)) {
833 AF_DP32(s->regs, STAT, OPERATING_MODE, R_STAT_OPERATING_MODE_NORMAL);
834 AF_DP32(s->regs, STAT, SELFREF_TYPE, R_STAT_SELFREF_TYPE_NONE);
835 }
836}
837
838static RegisterAccessInfo ddrc_regs_info[] = {
839 { .name = "MSTR", .decode.addr = A_MSTR,
840 .reset = 0x3040001,
841 },{ .name = "STAT", .decode.addr = A_STAT,
842 .ro = 0x337,
843
844 .reset = 0x1,
845 },{ .name = "MRCTRL0", .decode.addr = A_MRCTRL0,
846 .reset = 0x30,
847 },{ .name = "MRCTRL1", .decode.addr = A_MRCTRL1,
848 },{ .name = "MRSTAT", .decode.addr = A_MRSTAT,
849 .ro = 0x101,
850 },{ .name = "MRCTRL2", .decode.addr = A_MRCTRL2,
851 },{ .name = "DERATEEN", .decode.addr = A_DERATEEN,
852 },{ .name = "DERATEINT", .decode.addr = A_DERATEINT,
853 .reset = 0x800000,
854 },{ .name = "PWRCTL", .decode.addr = A_PWRCTL,
855 .post_write = ddrc_pwrctl_post_write,
856 },{ .name = "PWRTMG", .decode.addr = A_PWRTMG,
857 .reset = 0x402010,
858 },{ .name = "HWLPCTL", .decode.addr = A_HWLPCTL,
859 .reset = 0x3,
860 },{ .name = "RFSHCTL0", .decode.addr = A_RFSHCTL0,
861 .reset = 0x210000,
862 },{ .name = "RFSHCTL1", .decode.addr = A_RFSHCTL1,
863 },{ .name = "RFSHCTL3", .decode.addr = A_RFSHCTL3,
864 },{ .name = "RFSHTMG", .decode.addr = A_RFSHTMG,
865 .reset = 0x62008c,
866 },{ .name = "ECCCFG0", .decode.addr = A_ECCCFG0,
867 },{ .name = "ECCCFG1", .decode.addr = A_ECCCFG1,
868 },{ .name = "ECCSTAT", .decode.addr = A_ECCSTAT,
869 .ro = 0xf0f7f,
870 },{ .name = "ECCCLR", .decode.addr = A_ECCCLR,
871 .w1c = 0xf,
872 },{ .name = "ECCERRCNT", .decode.addr = A_ECCERRCNT,
873 .ro = 0xffffffff,
874 },{ .name = "ECCCADDR0", .decode.addr = A_ECCCADDR0,
875 .ro = 0x103ffff,
876 },{ .name = "ECCCADDR1", .decode.addr = A_ECCCADDR1,
877 .ro = 0x3070fff,
878 },{ .name = "ECCCSYN0", .decode.addr = A_ECCCSYN0,
879 .ro = 0xffffffff,
880 },{ .name = "ECCCSYN1", .decode.addr = A_ECCCSYN1,
881 .ro = 0xffffffff,
882 },{ .name = "ECCCSYN2", .decode.addr = A_ECCCSYN2,
883 .ro = 0xff,
884 },{ .name = "ECCBITMASK0", .decode.addr = A_ECCBITMASK0,
885 .ro = 0xffffffff,
886 },{ .name = "ECCBITMASK1", .decode.addr = A_ECCBITMASK1,
887 .ro = 0xffffffff,
888 },{ .name = "ECCBITMASK2", .decode.addr = A_ECCBITMASK2,
889 .ro = 0xff,
890 },{ .name = "ECCUADDR0", .decode.addr = A_ECCUADDR0,
891 .ro = 0x103ffff,
892 },{ .name = "ECCUADDR1", .decode.addr = A_ECCUADDR1,
893 .ro = 0x3070fff,
894 },{ .name = "ECCUSYN0", .decode.addr = A_ECCUSYN0,
895 .ro = 0xffffffff,
896 },{ .name = "ECCUSYN1", .decode.addr = A_ECCUSYN1,
897 .ro = 0xffffffff,
898 },{ .name = "ECCUSYN2", .decode.addr = A_ECCUSYN2,
899 .ro = 0xff,
900 },{ .name = "ECCPOISONADDR0", .decode.addr = A_ECCPOISONADDR0,
901 },{ .name = "ECCPOISONADDR1", .decode.addr = A_ECCPOISONADDR1,
902 },{ .name = "CRCPARCTL0", .decode.addr = A_CRCPARCTL0,
903 .reset = 0x8000,
904 .w1c = 0x116,
905 },{ .name = "CRCPARCTL1", .decode.addr = A_CRCPARCTL1,
906 .reset = 0x10000200,
907 },{ .name = "CRCPARCTL2", .decode.addr = A_CRCPARCTL2,
908 .reset = 0x30050c,
909 },{ .name = "CRCPARSTAT", .decode.addr = A_CRCPARSTAT,
910 .ro = 0x307fffff,
911 },{ .name = "INIT0", .decode.addr = A_INIT0,
912 .reset = 0x2004e,
913 },{ .name = "INIT1", .decode.addr = A_INIT1,
914 },{ .name = "INIT2", .decode.addr = A_INIT2,
915 .reset = 0xd05,
916 },{ .name = "INIT3", .decode.addr = A_INIT3,
917 .reset = 0x510,
918 },{ .name = "INIT4", .decode.addr = A_INIT4,
919 },{ .name = "INIT5", .decode.addr = A_INIT5,
920 .reset = 0x100004,
921 },{ .name = "INIT6", .decode.addr = A_INIT6,
922 },{ .name = "INIT7", .decode.addr = A_INIT7,
923 },{ .name = "DIMMCTL", .decode.addr = A_DIMMCTL,
924 },{ .name = "RANKCTL", .decode.addr = A_RANKCTL,
925 .reset = 0x66f,
926 },{ .name = "DRAMTMG0", .decode.addr = A_DRAMTMG0,
927 .reset = 0xf101b0f,
928 },{ .name = "DRAMTMG1", .decode.addr = A_DRAMTMG1,
929 .reset = 0x80414,
930 },{ .name = "DRAMTMG2", .decode.addr = A_DRAMTMG2,
931 .reset = 0x305060d,
932 },{ .name = "DRAMTMG3", .decode.addr = A_DRAMTMG3,
933 .reset = 0x50400c,
934 },{ .name = "DRAMTMG4", .decode.addr = A_DRAMTMG4,
935 .reset = 0x5040405,
936 },{ .name = "DRAMTMG5", .decode.addr = A_DRAMTMG5,
937 .reset = 0x5050403,
938 },{ .name = "DRAMTMG6", .decode.addr = A_DRAMTMG6,
939 .reset = 0x2020005,
940 },{ .name = "DRAMTMG7", .decode.addr = A_DRAMTMG7,
941 .reset = 0x202,
942 },{ .name = "DRAMTMG8", .decode.addr = A_DRAMTMG8,
943 .reset = 0x3034405,
944 },{ .name = "DRAMTMG9", .decode.addr = A_DRAMTMG9,
945 .reset = 0x4040d,
946 },{ .name = "DRAMTMG10", .decode.addr = A_DRAMTMG10,
947 .reset = 0x1c180a,
948 },{ .name = "DRAMTMG11", .decode.addr = A_DRAMTMG11,
949 .reset = 0x440c021c,
950 },{ .name = "DRAMTMG12", .decode.addr = A_DRAMTMG12,
951 .reset = 0x20610,
952 },{ .name = "DRAMTMG13", .decode.addr = A_DRAMTMG13,
953 .reset = 0x1c200004,
954 },{ .name = "DRAMTMG14", .decode.addr = A_DRAMTMG14,
955 .reset = 0xa0,
956 },{ .name = "ZQCTL0", .decode.addr = A_ZQCTL0,
957 .reset = 0x2000040,
958 },{ .name = "ZQCTL1", .decode.addr = A_ZQCTL1,
959 .reset = 0x2000100,
960 },{ .name = "ZQCTL2", .decode.addr = A_ZQCTL2,
961 },{ .name = "ZQSTAT", .decode.addr = A_ZQSTAT,
962 .ro = 0x1,
963 },{ .name = "DFITMG0", .decode.addr = A_DFITMG0,
964 .reset = 0x7020002,
965 },{ .name = "DFITMG1", .decode.addr = A_DFITMG1,
966 .reset = 0x404,
967 },{ .name = "DFILPCFG0", .decode.addr = A_DFILPCFG0,
968 .reset = 0x7000000,
969 },{ .name = "DFILPCFG1", .decode.addr = A_DFILPCFG1,
970 },{ .name = "DFIUPD0", .decode.addr = A_DFIUPD0,
971 .reset = 0x400003,
972 },{ .name = "DFIUPD1", .decode.addr = A_DFIUPD1,
973 },{ .name = "DFIUPD2", .decode.addr = A_DFIUPD2,
974 .reset = 0x80000000,
975 },{ .name = "DFIMISC", .decode.addr = A_DFIMISC,
976 .reset = 0x1,
977 },{ .name = "DFITMG2", .decode.addr = A_DFITMG2,
978 .reset = 0x202,
979 },{ .name = "DBICTL", .decode.addr = A_DBICTL,
980 .reset = 0x1,
981 },{ .name = "ADDRMAP0", .decode.addr = A_ADDRMAP0,
982 },{ .name = "ADDRMAP1", .decode.addr = A_ADDRMAP1,
983 },{ .name = "ADDRMAP2", .decode.addr = A_ADDRMAP2,
984 },{ .name = "ADDRMAP3", .decode.addr = A_ADDRMAP3,
985 },{ .name = "ADDRMAP4", .decode.addr = A_ADDRMAP4,
986 },{ .name = "ADDRMAP5", .decode.addr = A_ADDRMAP5,
987 },{ .name = "ADDRMAP6", .decode.addr = A_ADDRMAP6,
988 },{ .name = "ADDRMAP7", .decode.addr = A_ADDRMAP7,
989 },{ .name = "ADDRMAP8", .decode.addr = A_ADDRMAP8,
990 },{ .name = "ADDRMAP9", .decode.addr = A_ADDRMAP9,
991 },{ .name = "ADDRMAP10", .decode.addr = A_ADDRMAP10,
992 },{ .name = "ADDRMAP11", .decode.addr = A_ADDRMAP11,
993 },{ .name = "ODTCFG", .decode.addr = A_ODTCFG,
994 .reset = 0x4000400,
995 },{ .name = "ODTMAP", .decode.addr = A_ODTMAP,
996 .reset = 0x2211,
997 },{ .name = "SCHED", .decode.addr = A_SCHED,
998 .reset = 0x2005,
999 },{ .name = "SCHED1", .decode.addr = A_SCHED1,
1000 },{ .name = "PERFHPR1", .decode.addr = A_PERFHPR1,
1001 .reset = 0xf000001,
1002 },{ .name = "PERFLPR1", .decode.addr = A_PERFLPR1,
1003 .reset = 0xf00007f,
1004 },{ .name = "PERFWR1", .decode.addr = A_PERFWR1,
1005 .reset = 0xf00007f,
1006 },{ .name = "PERFVPR1", .decode.addr = A_PERFVPR1,
1007 },{ .name = "PERFVPW1", .decode.addr = A_PERFVPW1,
1008 },{ .name = "DQMAP0", .decode.addr = A_DQMAP0,
1009 },{ .name = "DQMAP1", .decode.addr = A_DQMAP1,
1010 },{ .name = "DQMAP2", .decode.addr = A_DQMAP2,
1011 },{ .name = "DQMAP3", .decode.addr = A_DQMAP3,
1012 },{ .name = "DQMAP4", .decode.addr = A_DQMAP4,
1013 },{ .name = "DQMAP5", .decode.addr = A_DQMAP5,
1014 },{ .name = "DBG0", .decode.addr = A_DBG0,
1015 },{ .name = "DBG1", .decode.addr = A_DBG1,
1016 },{ .name = "DBGCAM", .decode.addr = A_DBGCAM,
1017 .ro = 0xf77f7f7f,
1018 },{ .name = "DBGCMD", .decode.addr = A_DBGCMD,
1019 },{ .name = "DBGSTAT", .decode.addr = A_DBGSTAT,
1020 .ro = 0x33,
1021 },{ .name = "SWCTL", .decode.addr = A_SWCTL,
1022 .reset = 0x1,
1023 },{ .name = "SWSTAT", .decode.addr = A_SWSTAT,
1024 .ro = 0x1,
1025 },{ .name = "POISONCFG", .decode.addr = A_POISONCFG,
1026 .reset = 0x110011,
1027 .w1c = 0x1000100,
1028 },{ .name = "POISONSTAT", .decode.addr = A_POISONSTAT,
1029 .ro = 0x3f003f,
1030 },{ .name = "PSTAT", .decode.addr = A_PSTAT,
1031 .ro = 0x3f003f,
1032 },{ .name = "PCCFG", .decode.addr = A_PCCFG,
1033 },{ .name = "PCFGR_0", .decode.addr = A_PCFGR_0,
1034 },{ .name = "PCFGW_0", .decode.addr = A_PCFGW_0,
1035 .reset = 0x4000,
1036 },{ .name = "PCTRL_0", .decode.addr = A_PCTRL_0,
1037 },{ .name = "PCFGQOS0_0", .decode.addr = A_PCFGQOS0_0,
1038 },{ .name = "PCFGQOS1_0", .decode.addr = A_PCFGQOS1_0,
1039 },{ .name = "PCFGWQOS0_0", .decode.addr = A_PCFGWQOS0_0,
1040 },{ .name = "PCFGWQOS1_0", .decode.addr = A_PCFGWQOS1_0,
1041 },{ .name = "PCFGR_1", .decode.addr = A_PCFGR_1,
1042 },{ .name = "PCFGW_1", .decode.addr = A_PCFGW_1,
1043 .reset = 0x4000,
1044 },{ .name = "PCTRL_1", .decode.addr = A_PCTRL_1,
1045 },{ .name = "PCFGQOS0_1", .decode.addr = A_PCFGQOS0_1,
1046 .reset = 0x2000e00,
1047 },{ .name = "PCFGQOS1_1", .decode.addr = A_PCFGQOS1_1,
1048 },{ .name = "PCFGWQOS0_1", .decode.addr = A_PCFGWQOS0_1,
1049 },{ .name = "PCFGWQOS1_1", .decode.addr = A_PCFGWQOS1_1,
1050 },{ .name = "PCFGR_2", .decode.addr = A_PCFGR_2,
1051 },{ .name = "PCFGW_2", .decode.addr = A_PCFGW_2,
1052 .reset = 0x4000,
1053 },{ .name = "PCTRL_2", .decode.addr = A_PCTRL_2,
1054 },{ .name = "PCFGQOS0_2", .decode.addr = A_PCFGQOS0_2,
1055 .reset = 0x2000e00,
1056 },{ .name = "PCFGQOS1_2", .decode.addr = A_PCFGQOS1_2,
1057 },{ .name = "PCFGWQOS0_2", .decode.addr = A_PCFGWQOS0_2,
1058 },{ .name = "PCFGWQOS1_2", .decode.addr = A_PCFGWQOS1_2,
1059 },{ .name = "PCFGR_3", .decode.addr = A_PCFGR_3,
1060 },{ .name = "PCFGW_3", .decode.addr = A_PCFGW_3,
1061 .reset = 0x4000,
1062 },{ .name = "PCTRL_3", .decode.addr = A_PCTRL_3,
1063 },{ .name = "PCFGQOS0_3", .decode.addr = A_PCFGQOS0_3,
1064 },{ .name = "PCFGQOS1_3", .decode.addr = A_PCFGQOS1_3,
1065 },{ .name = "PCFGWQOS0_3", .decode.addr = A_PCFGWQOS0_3,
1066 },{ .name = "PCFGWQOS1_3", .decode.addr = A_PCFGWQOS1_3,
1067 },{ .name = "PCFGR_4", .decode.addr = A_PCFGR_4,
1068 },{ .name = "PCFGW_4", .decode.addr = A_PCFGW_4,
1069 .reset = 0x4000,
1070 },{ .name = "PCTRL_4", .decode.addr = A_PCTRL_4,
1071 },{ .name = "PCFGQOS0_4", .decode.addr = A_PCFGQOS0_4,
1072 },{ .name = "PCFGQOS1_4", .decode.addr = A_PCFGQOS1_4,
1073 },{ .name = "PCFGWQOS0_4", .decode.addr = A_PCFGWQOS0_4,
1074 },{ .name = "PCFGWQOS1_4", .decode.addr = A_PCFGWQOS1_4,
1075 },{ .name = "PCFGR_5", .decode.addr = A_PCFGR_5,
1076 },{ .name = "PCFGW_5", .decode.addr = A_PCFGW_5,
1077 .reset = 0x4000,
1078 },{ .name = "PCTRL_5", .decode.addr = A_PCTRL_5,
1079 },{ .name = "PCFGQOS0_5", .decode.addr = A_PCFGQOS0_5,
1080 },{ .name = "PCFGQOS1_5", .decode.addr = A_PCFGQOS1_5,
1081 },{ .name = "PCFGWQOS0_5", .decode.addr = A_PCFGWQOS0_5,
1082 },{ .name = "PCFGWQOS1_5", .decode.addr = A_PCFGWQOS1_5,
1083 },{ .name = "SARBASE0", .decode.addr = A_SARBASE0,
1084 },{ .name = "SARSIZE0", .decode.addr = A_SARSIZE0,
1085 },{ .name = "SARBASE1", .decode.addr = A_SARBASE1,
1086 .reset = 0x1,
1087 },{ .name = "SARSIZE1", .decode.addr = A_SARSIZE1,
1088 },{ .name = "DERATEINT_SHADOW", .decode.addr = A_DERATEINT_SHADOW,
1089 .reset = 0x800000,
1090 },{ .name = "RFSHCTL0_SHADOW", .decode.addr = A_RFSHCTL0_SHADOW,
1091 .reset = 0x210000,
1092 },{ .name = "RFSHTMG_SHADOW", .decode.addr = A_RFSHTMG_SHADOW,
1093 .reset = 0x62008c,
1094 },{ .name = "INIT3_SHADOW", .decode.addr = A_INIT3_SHADOW,
1095 .reset = 0x510,
1096 },{ .name = "INIT4_SHADOW", .decode.addr = A_INIT4_SHADOW,
1097 },{ .name = "INIT6_SHADOW", .decode.addr = A_INIT6_SHADOW,
1098 },{ .name = "INIT7_SHADOW", .decode.addr = A_INIT7_SHADOW,
1099 },{ .name = "DRAMTMG0_SHADOW", .decode.addr = A_DRAMTMG0_SHADOW,
1100 .reset = 0xf101b0f,
1101 },{ .name = "DRAMTMG1_SHADOW", .decode.addr = A_DRAMTMG1_SHADOW,
1102 .reset = 0x80414,
1103 },{ .name = "DRAMTMG2_SHADOW", .decode.addr = A_DRAMTMG2_SHADOW,
1104 .reset = 0x305060d,
1105 },{ .name = "DRAMTMG3_SHADOW", .decode.addr = A_DRAMTMG3_SHADOW,
1106 .reset = 0x50400c,
1107 },{ .name = "DRAMTMG4_SHADOW", .decode.addr = A_DRAMTMG4_SHADOW,
1108 .reset = 0x5040405,
1109 },{ .name = "DRAMTMG5_SHADOW", .decode.addr = A_DRAMTMG5_SHADOW,
1110 .reset = 0x5050403,
1111 },{ .name = "DRAMTMG6_SHADOW", .decode.addr = A_DRAMTMG6_SHADOW,
1112 .reset = 0x2020005,
1113 },{ .name = "DRAMTMG7_SHADOW", .decode.addr = A_DRAMTMG7_SHADOW,
1114 .reset = 0x202,
1115 },{ .name = "DRAMTMG8_SHADOW", .decode.addr = A_DRAMTMG8_SHADOW,
1116 .reset = 0x3034405,
1117 },{ .name = "DRAMTMG9_SHADOW", .decode.addr = A_DRAMTMG9_SHADOW,
1118 .reset = 0x4040d,
1119 },{ .name = "DRAMTMG10_SHADOW", .decode.addr = A_DRAMTMG10_SHADOW,
1120 .reset = 0x1c180a,
1121 },{ .name = "DRAMTMG11_SHADOW", .decode.addr = A_DRAMTMG11_SHADOW,
1122 .reset = 0x440c021c,
1123 },{ .name = "DRAMTMG12_SHADOW", .decode.addr = A_DRAMTMG12_SHADOW,
1124 .reset = 0x20610,
1125 },{ .name = "DRAMTMG13_SHADOW", .decode.addr = A_DRAMTMG13_SHADOW,
1126 .reset = 0x1c200004,
1127 },{ .name = "DRAMTMG14_SHADOW", .decode.addr = A_DRAMTMG14_SHADOW,
1128 .reset = 0xa0,
1129 },{ .name = "ZQCTL0_SHADOW", .decode.addr = A_ZQCTL0_SHADOW,
1130 .reset = 0x2000040,
1131 },{ .name = "DFITMG0_SHADOW", .decode.addr = A_DFITMG0_SHADOW,
1132 .reset = 0x7020002,
1133 },{ .name = "DFITMG1_SHADOW", .decode.addr = A_DFITMG1_SHADOW,
1134 .reset = 0x404,
1135 },{ .name = "DFITMG2_SHADOW", .decode.addr = A_DFITMG2_SHADOW,
1136 .reset = 0x202,
1137 },{ .name = "ODTCFG_SHADOW", .decode.addr = A_ODTCFG_SHADOW,
1138 .reset = 0x4000400,
1139 }
1140};
1141
1142static void ddrc_reset(DeviceState *dev)
1143{
1144 DDRC *s = XILINX_DDRC(dev);
1145 unsigned int i;
1146
1147 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
1148 register_reset(&s->regs_info[i]);
1149 }
1150
1151}
1152
1153static uint64_t ddrc_read(void *opaque, hwaddr addr, unsigned size)
1154{
1155 DDRC *s = XILINX_DDRC(opaque);
1156 RegisterInfo *r = &s->regs_info[addr / 4];
1157
1158 if (!r->data) {
1159 qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
1160 object_get_canonical_path(OBJECT(s)),
1161 addr);
1162 return 0;
1163 }
1164 return register_read(r);
1165}
1166
1167static void ddrc_write(void *opaque, hwaddr addr, uint64_t value,
1168 unsigned size)
1169{
1170 DDRC *s = XILINX_DDRC(opaque);
1171 RegisterInfo *r = &s->regs_info[addr / 4];
1172
1173 if (!r->data) {
1174 qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
1175 object_get_canonical_path(OBJECT(s)),
1176 addr, value);
1177 return;
1178 }
1179 register_write(r, value, ~0);
1180}
1181
1182static const MemoryRegionOps ddrc_ops = {
1183 .read = ddrc_read,
1184 .write = ddrc_write,
1185 .endianness = DEVICE_LITTLE_ENDIAN,
1186 .valid = {
1187 .min_access_size = 4,
1188 .max_access_size = 4,
1189 },
1190};
1191
1192static void ddrc_realize(DeviceState *dev, Error **errp)
1193{
1194 DDRC *s = XILINX_DDRC(dev);
1195 const char *prefix = object_get_canonical_path(OBJECT(dev));
1196 unsigned int i;
1197
1198 for (i = 0; i < ARRAY_SIZE(ddrc_regs_info); ++i) {
1199 RegisterInfo *r = &s->regs_info[ddrc_regs_info[i].decode.addr/4];
1200
1201 *r = (RegisterInfo) {
1202 .data = (uint8_t *)&s->regs[
1203 ddrc_regs_info[i].decode.addr/4],
1204 .data_size = sizeof(uint32_t),
1205 .access = &ddrc_regs_info[i],
1206 .debug = XILINX_DDRC_ERR_DEBUG,
1207 .prefix = prefix,
1208 .opaque = s,
1209 };
1210 }
1211}
1212
1213static void ddrc_init(Object *obj)
1214{
1215 DDRC *s = XILINX_DDRC(obj);
1216 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1217
1218 memory_region_init_io(&s->iomem, obj, &ddrc_ops, s,
1219 TYPE_XILINX_DDRC, R_MAX * 4);
1220 sysbus_init_mmio(sbd, &s->iomem);
1221}
1222
1223static const VMStateDescription vmstate_ddrc = {
1224 .name = TYPE_XILINX_DDRC,
1225 .version_id = 1,
1226 .minimum_version_id = 1,
1227 .minimum_version_id_old = 1,
1228 .fields = (VMStateField[]) {
1229 VMSTATE_UINT32_ARRAY(regs, DDRC, R_MAX),
1230 VMSTATE_END_OF_LIST(),
1231 }
1232};
1233
1234static void ddrc_class_init(ObjectClass *klass, void *data)
1235{
1236 DeviceClass *dc = DEVICE_CLASS(klass);
1237
1238 dc->reset = ddrc_reset;
1239 dc->realize = ddrc_realize;
1240 dc->vmsd = &vmstate_ddrc;
1241}
1242
1243static const TypeInfo ddrc_info = {
1244 .name = TYPE_XILINX_DDRC,
1245 .parent = TYPE_SYS_BUS_DEVICE,
1246 .instance_size = sizeof(DDRC),
1247 .class_init = ddrc_class_init,
1248 .instance_init = ddrc_init,
1249};
1250
1251static void ddrc_register_types(void)
1252{
1253 type_register_static(&ddrc_info);
1254}
1255
1256type_init(ddrc_register_types)
1257
