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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33#include "qemu/config-file.h"
34#include "sysemu/sysemu.h"
35
36#include "hw/fdt_generic_util.h"
37
38#ifndef XILINX_CRL_APB_ERR_DEBUG
39#define XILINX_CRL_APB_ERR_DEBUG 0
40#endif
41
42#define TYPE_XILINX_CRL_APB "xlnx.zynqmp-crl"
43
44#define XILINX_CRL_APB(obj) \
45 OBJECT_CHECK(CRL_APB, (obj), TYPE_XILINX_CRL_APB)
46
47REG32(ERR_CTRL, 0x0)
48 FIELD(ERR_CTRL, SLVERR_ENABLE, 1, 0)
49REG32(IR_STATUS, 0x4)
50 FIELD(IR_STATUS, ADDR_DECODE_ERR, 1, 0)
51REG32(IR_MASK, 0x8)
52 FIELD(IR_MASK, ADDR_DECODE_ERR, 1, 0)
53REG32(IR_ENABLE, 0xc)
54 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 1, 0)
55REG32(IR_DISABLE, 0x10)
56 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 1, 0)
57REG32(CRL_WPROT, 0x1C)
58 FIELD(CRL_WPROT, ACTIVE, 1, 0)
59REG32(IOPLL_CTRL, 0x20)
60 FIELD(IOPLL_CTRL, POST_SRC, 3, 24)
61 FIELD(IOPLL_CTRL, PRE_SRC, 3, 20)
62 FIELD(IOPLL_CTRL, DIV2, 1, 16)
63 FIELD(IOPLL_CTRL, FBDIV, 7, 8)
64 FIELD(IOPLL_CTRL, BYPASS, 1, 3)
65 FIELD(IOPLL_CTRL, RESET, 1, 0)
66REG32(IOPLL_CFG, 0x24)
67 FIELD(IOPLL_CFG, LOCK_DLY, 7, 25)
68 FIELD(IOPLL_CFG, LOCK_CNT, 10, 13)
69 FIELD(IOPLL_CFG, LFHF, 2, 10)
70 FIELD(IOPLL_CFG, CP, 4, 5)
71 FIELD(IOPLL_CFG, RES, 4, 0)
72REG32(IOPLL_FRAC_CFG, 0x28)
73 FIELD(IOPLL_FRAC_CFG, ENABLED, 1, 31)
74 FIELD(IOPLL_FRAC_CFG, SEED, 3, 22)
75 FIELD(IOPLL_FRAC_CFG, ALGRTHM, 1, 19)
76 FIELD(IOPLL_FRAC_CFG, ORDER, 1, 18)
77 FIELD(IOPLL_FRAC_CFG, DATA, 16, 0)
78REG32(RPLL_CTRL, 0x30)
79 FIELD(RPLL_CTRL, POST_SRC, 3, 24)
80 FIELD(RPLL_CTRL, PRE_SRC, 3, 20)
81 FIELD(RPLL_CTRL, DIV2, 1, 16)
82 FIELD(RPLL_CTRL, FBDIV, 7, 8)
83 FIELD(RPLL_CTRL, BYPASS, 1, 3)
84 FIELD(RPLL_CTRL, RESET, 1, 0)
85REG32(RPLL_CFG, 0x34)
86 FIELD(RPLL_CFG, LOCK_DLY, 7, 25)
87 FIELD(RPLL_CFG, LOCK_CNT, 10, 13)
88 FIELD(RPLL_CFG, LFHF, 2, 10)
89 FIELD(RPLL_CFG, CP, 4, 5)
90 FIELD(RPLL_CFG, RES, 4, 0)
91REG32(RPLL_FRAC_CFG, 0x38)
92 FIELD(RPLL_FRAC_CFG, ENABLED, 1, 31)
93 FIELD(RPLL_FRAC_CFG, SEED, 3, 22)
94 FIELD(RPLL_FRAC_CFG, ALGRTHM, 1, 19)
95 FIELD(RPLL_FRAC_CFG, ORDER, 1, 18)
96 FIELD(RPLL_FRAC_CFG, DATA, 16, 0)
97REG32(PLL_STATUS, 0x40)
98 FIELD(PLL_STATUS, RPLL_STABLE, 1, 4)
99 FIELD(PLL_STATUS, IOPLL_STABLE, 1, 3)
100 FIELD(PLL_STATUS, RPLL_LOCK, 1, 1)
101 FIELD(PLL_STATUS, IOPLL_LOCK, 1, 0)
102REG32(IOPLL_TO_FPD_CTRL, 0x44)
103 FIELD(IOPLL_TO_FPD_CTRL, DIVISOR0, 6, 8)
104REG32(RPLL_TO_FPD_CTRL, 0x48)
105 FIELD(RPLL_TO_FPD_CTRL, DIVISOR0, 6, 8)
106REG32(USB3_DUAL_REF_CTRL, 0x4c)
107 FIELD(USB3_DUAL_REF_CTRL, CLKACT, 1, 25)
108 FIELD(USB3_DUAL_REF_CTRL, DIVISOR1, 6, 16)
109 FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 6, 8)
110 FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 3, 0)
111REG32(GEM0_REF_CTRL, 0x50)
112 FIELD(GEM0_REF_CTRL, RX_CLKACT, 1, 26)
113 FIELD(GEM0_REF_CTRL, CLKACT, 1, 25)
114 FIELD(GEM0_REF_CTRL, DIVISOR1, 6, 16)
115 FIELD(GEM0_REF_CTRL, DIVISOR0, 6, 8)
116 FIELD(GEM0_REF_CTRL, SRCSEL, 3, 0)
117REG32(GEM1_REF_CTRL, 0x54)
118 FIELD(GEM1_REF_CTRL, RX_CLKACT, 1, 26)
119 FIELD(GEM1_REF_CTRL, CLKACT, 1, 25)
120 FIELD(GEM1_REF_CTRL, DIVISOR1, 6, 16)
121 FIELD(GEM1_REF_CTRL, DIVISOR0, 6, 8)
122 FIELD(GEM1_REF_CTRL, SRCSEL, 3, 0)
123REG32(GEM2_REF_CTRL, 0x58)
124 FIELD(GEM2_REF_CTRL, RX_CLKACT, 1, 26)
125 FIELD(GEM2_REF_CTRL, CLKACT, 1, 25)
126 FIELD(GEM2_REF_CTRL, DIVISOR1, 6, 16)
127 FIELD(GEM2_REF_CTRL, DIVISOR0, 6, 8)
128 FIELD(GEM2_REF_CTRL, SRCSEL, 3, 0)
129REG32(GEM3_REF_CTRL, 0x5c)
130 FIELD(GEM3_REF_CTRL, RX_CLKACT, 1, 26)
131 FIELD(GEM3_REF_CTRL, CLKACT, 1, 25)
132 FIELD(GEM3_REF_CTRL, DIVISOR1, 6, 16)
133 FIELD(GEM3_REF_CTRL, DIVISOR0, 6, 8)
134 FIELD(GEM3_REF_CTRL, SRCSEL, 3, 0)
135REG32(USB0_BUS_REF_CTRL, 0x60)
136 FIELD(USB0_BUS_REF_CTRL, CLKACT, 1, 25)
137 FIELD(USB0_BUS_REF_CTRL, DIVISOR1, 6, 16)
138 FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 6, 8)
139 FIELD(USB0_BUS_REF_CTRL, SRCSEL, 3, 0)
140REG32(USB1_BUS_REF_CTRL, 0x64)
141 FIELD(USB1_BUS_REF_CTRL, CLKACT, 1, 25)
142 FIELD(USB1_BUS_REF_CTRL, DIVISOR1, 6, 16)
143 FIELD(USB1_BUS_REF_CTRL, DIVISOR0, 6, 8)
144 FIELD(USB1_BUS_REF_CTRL, SRCSEL, 3, 0)
145REG32(QSPI_REF_CTRL, 0x68)
146 FIELD(QSPI_REF_CTRL, CLKACT, 1, 24)
147 FIELD(QSPI_REF_CTRL, DIVISOR1, 6, 16)
148 FIELD(QSPI_REF_CTRL, DIVISOR0, 6, 8)
149 FIELD(QSPI_REF_CTRL, SRCSEL, 3, 0)
150REG32(SDIO0_REF_CTRL, 0x6c)
151 FIELD(SDIO0_REF_CTRL, CLKACT, 1, 24)
152 FIELD(SDIO0_REF_CTRL, DIVISOR1, 6, 16)
153 FIELD(SDIO0_REF_CTRL, DIVISOR0, 6, 8)
154 FIELD(SDIO0_REF_CTRL, SRCSEL, 3, 0)
155REG32(SDIO1_REF_CTRL, 0x70)
156 FIELD(SDIO1_REF_CTRL, CLKACT, 1, 24)
157 FIELD(SDIO1_REF_CTRL, DIVISOR1, 6, 16)
158 FIELD(SDIO1_REF_CTRL, DIVISOR0, 6, 8)
159 FIELD(SDIO1_REF_CTRL, SRCSEL, 3, 0)
160REG32(UART0_REF_CTRL, 0x74)
161 FIELD(UART0_REF_CTRL, CLKACT, 1, 24)
162 FIELD(UART0_REF_CTRL, DIVISOR1, 6, 16)
163 FIELD(UART0_REF_CTRL, DIVISOR0, 6, 8)
164 FIELD(UART0_REF_CTRL, SRCSEL, 3, 0)
165REG32(UART1_REF_CTRL, 0x78)
166 FIELD(UART1_REF_CTRL, CLKACT, 1, 24)
167 FIELD(UART1_REF_CTRL, DIVISOR1, 6, 16)
168 FIELD(UART1_REF_CTRL, DIVISOR0, 6, 8)
169 FIELD(UART1_REF_CTRL, SRCSEL, 3, 0)
170REG32(SPI0_REF_CTRL, 0x7c)
171 FIELD(SPI0_REF_CTRL, CLKACT, 1, 24)
172 FIELD(SPI0_REF_CTRL, DIVISOR1, 6, 16)
173 FIELD(SPI0_REF_CTRL, DIVISOR0, 6, 8)
174 FIELD(SPI0_REF_CTRL, SRCSEL, 3, 0)
175REG32(SPI1_REF_CTRL, 0x80)
176 FIELD(SPI1_REF_CTRL, CLKACT, 1, 24)
177 FIELD(SPI1_REF_CTRL, DIVISOR1, 6, 16)
178 FIELD(SPI1_REF_CTRL, DIVISOR0, 6, 8)
179 FIELD(SPI1_REF_CTRL, SRCSEL, 3, 0)
180REG32(CAN0_REF_CTRL, 0x84)
181 FIELD(CAN0_REF_CTRL, CLKACT, 1, 24)
182 FIELD(CAN0_REF_CTRL, DIVISOR1, 6, 16)
183 FIELD(CAN0_REF_CTRL, DIVISOR0, 6, 8)
184 FIELD(CAN0_REF_CTRL, SRCSEL, 3, 0)
185REG32(CAN1_REF_CTRL, 0x88)
186 FIELD(CAN1_REF_CTRL, CLKACT, 1, 24)
187 FIELD(CAN1_REF_CTRL, DIVISOR1, 6, 16)
188 FIELD(CAN1_REF_CTRL, DIVISOR0, 6, 8)
189 FIELD(CAN1_REF_CTRL, SRCSEL, 3, 0)
190REG32(CPU_R5_CTRL, 0x90)
191 FIELD(CPU_R5_CTRL, CLKACT_CORE, 1, 25)
192 FIELD(CPU_R5_CTRL, CLKACT, 1, 24)
193 FIELD(CPU_R5_CTRL, DIVISOR0, 6, 8)
194 FIELD(CPU_R5_CTRL, SRCSEL, 3, 0)
195REG32(IOU_SWITCH_CTRL, 0x9c)
196 FIELD(IOU_SWITCH_CTRL, CLKACT, 1, 24)
197 FIELD(IOU_SWITCH_CTRL, DIVISOR0, 6, 8)
198 FIELD(IOU_SWITCH_CTRL, SRCSEL, 3, 0)
199REG32(CSU_PLL_CTRL, 0xa0)
200 FIELD(CSU_PLL_CTRL, CLKACT, 1, 24)
201 FIELD(CSU_PLL_CTRL, DIVISOR0, 6, 8)
202 FIELD(CSU_PLL_CTRL, SRCSEL, 3, 0)
203REG32(PCAP_CTRL, 0xa4)
204 FIELD(PCAP_CTRL, CLKACT, 1, 24)
205 FIELD(PCAP_CTRL, DIVISOR0, 6, 8)
206 FIELD(PCAP_CTRL, SRCSEL, 3, 0)
207REG32(LPD_SWITCH_CTRL, 0xa8)
208 FIELD(LPD_SWITCH_CTRL, CLKACT, 1, 24)
209 FIELD(LPD_SWITCH_CTRL, DIVISOR0, 6, 8)
210 FIELD(LPD_SWITCH_CTRL, SRCSEL, 3, 0)
211REG32(LPD_LSBUS_CTRL, 0xac)
212 FIELD(LPD_LSBUS_CTRL, CLKACT, 1, 24)
213 FIELD(LPD_LSBUS_CTRL, DIVISOR0, 6, 8)
214 FIELD(LPD_LSBUS_CTRL, SRCSEL, 3, 0)
215REG32(DBG_LPD_CTRL, 0xb0)
216 FIELD(DBG_LPD_CTRL, CLKACT, 1, 24)
217 FIELD(DBG_LPD_CTRL, DIVISOR0, 6, 8)
218 FIELD(DBG_LPD_CTRL, SRCSEL, 3, 0)
219REG32(NAND_REF_CTRL, 0xb4)
220 FIELD(NAND_REF_CTRL, CLKACT, 1, 24)
221 FIELD(NAND_REF_CTRL, DIVISOR1, 6, 16)
222 FIELD(NAND_REF_CTRL, DIVISOR0, 6, 8)
223 FIELD(NAND_REF_CTRL, SRCSEL, 3, 0)
224REG32(ADMA_REF_CTRL, 0xb8)
225 FIELD(ADMA_REF_CTRL, CLKACT, 1, 24)
226 FIELD(ADMA_REF_CTRL, DIVISOR0, 6, 8)
227 FIELD(ADMA_REF_CTRL, SRCSEL, 3, 0)
228REG32(PL0_REF_CTRL, 0xc0)
229 FIELD(PL0_REF_CTRL, CLKACT, 1, 24)
230 FIELD(PL0_REF_CTRL, DIVISOR1, 6, 16)
231 FIELD(PL0_REF_CTRL, DIVISOR0, 6, 8)
232 FIELD(PL0_REF_CTRL, SRCSEL, 3, 0)
233REG32(PL1_REF_CTRL, 0xc4)
234 FIELD(PL1_REF_CTRL, CLKACT, 1, 24)
235 FIELD(PL1_REF_CTRL, DIVISOR1, 6, 16)
236 FIELD(PL1_REF_CTRL, DIVISOR0, 6, 8)
237 FIELD(PL1_REF_CTRL, SRCSEL, 3, 0)
238REG32(PL2_REF_CTRL, 0xc8)
239 FIELD(PL2_REF_CTRL, CLKACT, 1, 24)
240 FIELD(PL2_REF_CTRL, DIVISOR1, 6, 16)
241 FIELD(PL2_REF_CTRL, DIVISOR0, 6, 8)
242 FIELD(PL2_REF_CTRL, SRCSEL, 3, 0)
243REG32(PL3_REF_CTRL, 0xcc)
244 FIELD(PL3_REF_CTRL, CLKACT, 1, 24)
245 FIELD(PL3_REF_CTRL, DIVISOR1, 6, 16)
246 FIELD(PL3_REF_CTRL, DIVISOR0, 6, 8)
247 FIELD(PL3_REF_CTRL, SRCSEL, 3, 0)
248REG32(PL0_THR_CTRL, 0xd0)
249 FIELD(PL0_THR_CTRL, CURR_VAL, 16, 16)
250 FIELD(PL0_THR_CTRL, RUNNING, 1, 15)
251 FIELD(PL0_THR_CTRL, CPU_START, 1, 1)
252 FIELD(PL0_THR_CTRL, CNT_RST, 1, 0)
253REG32(PL0_THR_CNT, 0xd4)
254 FIELD(PL0_THR_CNT, LAST_CNT, 16, 0)
255REG32(PL1_THR_CTRL, 0xd8)
256 FIELD(PL1_THR_CTRL, CURR_VAL, 16, 16)
257 FIELD(PL1_THR_CTRL, RUNNING, 1, 15)
258 FIELD(PL1_THR_CTRL, CPU_START, 1, 1)
259 FIELD(PL1_THR_CTRL, CNT_RST, 1, 0)
260REG32(PL1_THR_CNT, 0xdc)
261 FIELD(PL1_THR_CNT, LAST_CNT, 16, 0)
262REG32(PL2_THR_CTRL, 0xe0)
263 FIELD(PL2_THR_CTRL, CURR_VAL, 16, 16)
264 FIELD(PL2_THR_CTRL, RUNNING, 1, 15)
265 FIELD(PL2_THR_CTRL, CPU_START, 1, 1)
266 FIELD(PL2_THR_CTRL, CNT_RST, 1, 0)
267REG32(PL2_THR_CNT, 0xe4)
268 FIELD(PL2_THR_CNT, LAST_CNT, 16, 0)
269REG32(PL3_THR_CTRL, 0xe8)
270 FIELD(PL3_THR_CTRL, CURR_VAL, 16, 16)
271 FIELD(PL3_THR_CTRL, RUNNING, 1, 15)
272 FIELD(PL3_THR_CTRL, CPU_START, 1, 1)
273 FIELD(PL3_THR_CTRL, CNT_RST, 1, 0)
274REG32(PL3_THR_CNT, 0xfc)
275 FIELD(PL3_THR_CNT, LAST_CNT, 16, 0)
276REG32(GEM_TSU_REF_CTRL, 0x100)
277 FIELD(GEM_TSU_REF_CTRL, CLKACT, 1, 24)
278 FIELD(GEM_TSU_REF_CTRL, DIVISOR1, 6, 16)
279 FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 6, 8)
280 FIELD(GEM_TSU_REF_CTRL, SRCSEL, 3, 0)
281REG32(DLL_REF_CTRL, 0x104)
282 FIELD(DLL_REF_CTRL, SRCSEL, 3, 0)
283REG32(AMS_REF_CTRL, 0x108)
284 FIELD(AMS_REF_CTRL, CLKACT, 1, 24)
285 FIELD(AMS_REF_CTRL, DIVISOR1, 6, 16)
286 FIELD(AMS_REF_CTRL, DIVISOR0, 6, 8)
287 FIELD(AMS_REF_CTRL, SRCSEL, 3, 0)
288REG32(I2C0_REF_CTRL, 0x120)
289 FIELD(I2C0_REF_CTRL, CLKACT, 1, 24)
290 FIELD(I2C0_REF_CTRL, DIVISOR1, 6, 16)
291 FIELD(I2C0_REF_CTRL, DIVISOR0, 6, 8)
292 FIELD(I2C0_REF_CTRL, SRCSEL, 3, 0)
293REG32(I2C1_REF_CTRL, 0x124)
294 FIELD(I2C1_REF_CTRL, CLKACT, 1, 24)
295 FIELD(I2C1_REF_CTRL, DIVISOR1, 6, 16)
296 FIELD(I2C1_REF_CTRL, DIVISOR0, 6, 8)
297 FIELD(I2C1_REF_CTRL, SRCSEL, 3, 0)
298REG32(TIMESTAMP_REF_CTRL, 0x128)
299 FIELD(TIMESTAMP_REF_CTRL, CLKACT, 1, 24)
300 FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 6, 8)
301 FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 3, 0)
302REG32(SAFETY_CHK, 0x130)
303 FIELD(SAFETY_CHK, CHK_VAL, 32, 0)
304REG32(CLKMON_STATUS, 0x140)
305 FIELD(CLKMON_STATUS, CNTA7_OVER_ERR, 1, 15)
306 FIELD(CLKMON_STATUS, MON7_ERR, 1, 14)
307 FIELD(CLKMON_STATUS, CNTA6_OVER_ERR, 1, 13)
308 FIELD(CLKMON_STATUS, MON6_ERR, 1, 12)
309 FIELD(CLKMON_STATUS, CNTA5_OVER_ERR, 1, 11)
310 FIELD(CLKMON_STATUS, MON5_ERR, 1, 10)
311 FIELD(CLKMON_STATUS, CNTA4_OVER_ERR, 1, 9)
312 FIELD(CLKMON_STATUS, MON4_ERR, 1, 8)
313 FIELD(CLKMON_STATUS, CNTA3_OVER_ERR, 1, 7)
314 FIELD(CLKMON_STATUS, MON3_ERR, 1, 6)
315 FIELD(CLKMON_STATUS, CNTA2_OVER_ERR, 1, 5)
316 FIELD(CLKMON_STATUS, MON2_ERR, 1, 4)
317 FIELD(CLKMON_STATUS, CNTA1_OVER_ERR, 1, 3)
318 FIELD(CLKMON_STATUS, MON1_ERR, 1, 2)
319 FIELD(CLKMON_STATUS, CNTA0_OVER_ERR, 1, 1)
320 FIELD(CLKMON_STATUS, MON0_ERR, 1, 0)
321REG32(CLKMON_MASK, 0x144)
322 FIELD(CLKMON_MASK, CNTA7_OVER_ERR, 1, 15)
323 FIELD(CLKMON_MASK, MON7_ERR, 1, 14)
324 FIELD(CLKMON_MASK, CNTA6_OVER_ERR, 1, 13)
325 FIELD(CLKMON_MASK, MON6_ERR, 1, 12)
326 FIELD(CLKMON_MASK, CNTA5_OVER_ERR, 1, 11)
327 FIELD(CLKMON_MASK, MON5_ERR, 1, 10)
328 FIELD(CLKMON_MASK, CNTA4_OVER_ERR, 1, 9)
329 FIELD(CLKMON_MASK, MON4_ERR, 1, 8)
330 FIELD(CLKMON_MASK, CNTA3_OVER_ERR, 1, 7)
331 FIELD(CLKMON_MASK, MON3_ERR, 1, 6)
332 FIELD(CLKMON_MASK, CNTA2_OVER_ERR, 1, 5)
333 FIELD(CLKMON_MASK, MON2_ERR, 1, 4)
334 FIELD(CLKMON_MASK, CNTA1_OVER_ERR, 1, 3)
335 FIELD(CLKMON_MASK, MON1_ERR, 1, 2)
336 FIELD(CLKMON_MASK, CNTA0_OVER_ERR, 1, 1)
337 FIELD(CLKMON_MASK, MON0_ERR, 1, 0)
338REG32(CLKMON_ENABLE, 0x148)
339 FIELD(CLKMON_ENABLE, CNTA7_OVER_ERR, 1, 15)
340 FIELD(CLKMON_ENABLE, MON7_ERR, 1, 14)
341 FIELD(CLKMON_ENABLE, CNTA6_OVER_ERR, 1, 13)
342 FIELD(CLKMON_ENABLE, MON6_ERR, 1, 12)
343 FIELD(CLKMON_ENABLE, CNTA5_OVER_ERR, 1, 11)
344 FIELD(CLKMON_ENABLE, MON5_ERR, 1, 10)
345 FIELD(CLKMON_ENABLE, CNTA4_OVER_ERR, 1, 9)
346 FIELD(CLKMON_ENABLE, MON4_ERR, 1, 8)
347 FIELD(CLKMON_ENABLE, CNTA3_OVER_ERR, 1, 7)
348 FIELD(CLKMON_ENABLE, MON3_ERR, 1, 6)
349 FIELD(CLKMON_ENABLE, CNTA2_OVER_ERR, 1, 5)
350 FIELD(CLKMON_ENABLE, MON2_ERR, 1, 4)
351 FIELD(CLKMON_ENABLE, CNTA1_OVER_ERR, 1, 3)
352 FIELD(CLKMON_ENABLE, MON1_ERR, 1, 2)
353 FIELD(CLKMON_ENABLE, CNTA0_OVER_ERR, 1, 1)
354 FIELD(CLKMON_ENABLE, MON0_ERR, 1, 0)
355REG32(CLKMON_DISABLE, 0x14C)
356 FIELD(CLKMON_DISABLE, CNTA7_OVER_ERR, 1, 15)
357 FIELD(CLKMON_DISABLE, MON7_ERR, 1, 14)
358 FIELD(CLKMON_DISABLE, CNTA6_OVER_ERR, 1, 13)
359 FIELD(CLKMON_DISABLE, MON6_ERR, 1, 12)
360 FIELD(CLKMON_DISABLE, CNTA5_OVER_ERR, 1, 11)
361 FIELD(CLKMON_DISABLE, MON5_ERR, 1, 10)
362 FIELD(CLKMON_DISABLE, CNTA4_OVER_ERR, 1, 9)
363 FIELD(CLKMON_DISABLE, MON4_ERR, 1, 8)
364 FIELD(CLKMON_DISABLE, CNTA3_OVER_ERR, 1, 7)
365 FIELD(CLKMON_DISABLE, MON3_ERR, 1, 6)
366 FIELD(CLKMON_DISABLE, CNTA2_OVER_ERR, 1, 5)
367 FIELD(CLKMON_DISABLE, MON2_ERR, 1, 4)
368 FIELD(CLKMON_DISABLE, CNTA1_OVER_ERR, 1, 3)
369 FIELD(CLKMON_DISABLE, MON1_ERR, 1, 2)
370 FIELD(CLKMON_DISABLE, CNTA0_OVER_ERR, 1, 1)
371 FIELD(CLKMON_DISABLE, MON0_ERR, 1, 0)
372REG32(CLKMON_TRIGGER, 0x150)
373 FIELD(CLKMON_TRIGGER, CNTA7_OVER_ERR, 1, 15)
374 FIELD(CLKMON_TRIGGER, MON7_ERR, 1, 14)
375 FIELD(CLKMON_TRIGGER, CNTA6_OVER_ERR, 1, 13)
376 FIELD(CLKMON_TRIGGER, MON6_ERR, 1, 12)
377 FIELD(CLKMON_TRIGGER, CNTA5_OVER_ERR, 1, 11)
378 FIELD(CLKMON_TRIGGER, MON5_ERR, 1, 10)
379 FIELD(CLKMON_TRIGGER, CNTA4_OVER_ERR, 1, 9)
380 FIELD(CLKMON_TRIGGER, MON4_ERR, 1, 8)
381 FIELD(CLKMON_TRIGGER, CNTA3_OVER_ERR, 1, 7)
382 FIELD(CLKMON_TRIGGER, MON3_ERR, 1, 6)
383 FIELD(CLKMON_TRIGGER, CNTA2_OVER_ERR, 1, 5)
384 FIELD(CLKMON_TRIGGER, MON2_ERR, 1, 4)
385 FIELD(CLKMON_TRIGGER, CNTA1_OVER_ERR, 1, 3)
386 FIELD(CLKMON_TRIGGER, MON1_ERR, 1, 2)
387 FIELD(CLKMON_TRIGGER, CNTA0_OVER_ERR, 1, 1)
388 FIELD(CLKMON_TRIGGER, MON0_ERR, 1, 0)
389REG32(CHKR0_CLKA_UPPER, 0x160)
390 FIELD(CHKR0_CLKA_UPPER, THRSHLD, 32, 0)
391REG32(CHKR0_CLKA_LOWER, 0x164)
392 FIELD(CHKR0_CLKA_LOWER, THRSHLD, 32, 0)
393REG32(CHKR0_CLKB_CNT, 0x168)
394 FIELD(CHKR0_CLKB_CNT, VALUE, 32, 0)
395REG32(CHKR0_CTRL, 0x16C)
396 FIELD(CHKR0_CTRL, START_SINGLE, 1, 8)
397 FIELD(CHKR0_CTRL, START_CONTINUOUS, 1, 7)
398 FIELD(CHKR0_CTRL, CLKB_MUX_CTRL, 1, 5)
399 FIELD(CHKR0_CTRL, CLKA_MUX_CTRL, 3, 1)
400 FIELD(CHKR0_CTRL, ENABLE, 1, 0)
401REG32(CHKR1_CLKA_UPPER, 0x170)
402 FIELD(CHKR1_CLKA_UPPER, THRSHLD, 32, 0)
403REG32(CHKR1_CLKA_LOWER, 0x174)
404 FIELD(CHKR1_CLKA_LOWER, THRSHLD, 32, 0)
405REG32(CHKR1_CLKB_CNT, 0x178)
406 FIELD(CHKR1_CLKB_CNT, VALUE, 32, 0)
407REG32(CHKR1_CTRL, 0x17C)
408 FIELD(CHKR1_CTRL, START_SINGLE, 1, 8)
409 FIELD(CHKR1_CTRL, START_CONTINUOUS, 1, 7)
410 FIELD(CHKR1_CTRL, CLKB_MUX_CTRL, 1, 5)
411 FIELD(CHKR1_CTRL, CLKA_MUX_CTRL, 3, 1)
412 FIELD(CHKR1_CTRL, ENABLE, 1, 0)
413REG32(CHKR2_CLKA_UPPER, 0x180)
414 FIELD(CHKR2_CLKA_UPPER, THRSHLD, 32, 0)
415REG32(CHKR2_CLKA_LOWER, 0x184)
416 FIELD(CHKR2_CLKA_LOWER, THRSHLD, 32, 0)
417REG32(CHKR2_CLKB_CNT, 0x188)
418 FIELD(CHKR2_CLKB_CNT, VALUE, 32, 0)
419REG32(CHKR2_CTRL, 0x18C)
420 FIELD(CHKR2_CTRL, START_SINGLE, 1, 8)
421 FIELD(CHKR2_CTRL, START_CONTINUOUS, 1, 7)
422 FIELD(CHKR2_CTRL, CLKB_MUX_CTRL, 1, 5)
423 FIELD(CHKR2_CTRL, CLKA_MUX_CTRL, 3, 1)
424 FIELD(CHKR2_CTRL, ENABLE, 1, 0)
425REG32(CHKR3_CLKA_UPPER, 0x190)
426 FIELD(CHKR3_CLKA_UPPER, THRSHLD, 32, 0)
427REG32(CHKR3_CLKA_LOWER, 0x194)
428 FIELD(CHKR3_CLKA_LOWER, THRSHLD, 32, 0)
429REG32(CHKR3_CLKB_CNT, 0x198)
430 FIELD(CHKR3_CLKB_CNT, VALUE, 32, 0)
431REG32(CHKR3_CTRL, 0x19C)
432 FIELD(CHKR3_CTRL, START_SINGLE, 1, 8)
433 FIELD(CHKR3_CTRL, START_CONTINUOUS, 1, 7)
434 FIELD(CHKR3_CTRL, CLKB_MUX_CTRL, 1, 5)
435 FIELD(CHKR3_CTRL, CLKA_MUX_CTRL, 3, 1)
436 FIELD(CHKR3_CTRL, ENABLE, 1, 0)
437REG32(CHKR4_CLKA_UPPER, 0x1A0)
438 FIELD(CHKR4_CLKA_UPPER, THRSHLD, 32, 0)
439REG32(CHKR4_CLKA_LOWER, 0x1A4)
440 FIELD(CHKR4_CLKA_LOWER, THRSHLD, 32, 0)
441REG32(CHKR4_CLKB_CNT, 0x1A8)
442 FIELD(CHKR4_CLKB_CNT, VALUE, 32, 0)
443REG32(CHKR4_CTRL, 0x1AC)
444 FIELD(CHKR4_CTRL, START_SINGLE, 1, 8)
445 FIELD(CHKR4_CTRL, START_CONTINUOUS, 1, 7)
446 FIELD(CHKR4_CTRL, CLKB_MUX_CTRL, 1, 5)
447 FIELD(CHKR4_CTRL, CLKA_MUX_CTRL, 3, 1)
448 FIELD(CHKR4_CTRL, ENABLE, 1, 0)
449REG32(CHKR5_CLKA_UPPER, 0x1B0)
450 FIELD(CHKR5_CLKA_UPPER, THRSHLD, 32, 0)
451REG32(CHKR5_CLKA_LOWER, 0x1B4)
452 FIELD(CHKR5_CLKA_LOWER, THRSHLD, 32, 0)
453REG32(CHKR5_CLKB_CNT, 0x1B8)
454 FIELD(CHKR5_CLKB_CNT, VALUE, 32, 0)
455REG32(CHKR5_CTRL, 0x1BC)
456 FIELD(CHKR5_CTRL, START_SINGLE, 1, 8)
457 FIELD(CHKR5_CTRL, START_CONTINUOUS, 1, 7)
458 FIELD(CHKR5_CTRL, CLKB_MUX_CTRL, 1, 5)
459 FIELD(CHKR5_CTRL, CLKA_MUX_CTRL, 3, 1)
460 FIELD(CHKR5_CTRL, ENABLE, 1, 0)
461REG32(CHKR6_CLKA_UPPER, 0x1C0)
462 FIELD(CHKR6_CLKA_UPPER, THRSHLD, 32, 0)
463REG32(CHKR6_CLKA_LOWER, 0x1C4)
464 FIELD(CHKR6_CLKA_LOWER, THRSHLD, 32, 0)
465REG32(CHKR6_CLKB_CNT, 0x1C8)
466 FIELD(CHKR6_CLKB_CNT, VALUE, 32, 0)
467REG32(CHKR6_CTRL, 0x1CC)
468 FIELD(CHKR6_CTRL, START_SINGLE, 1, 8)
469 FIELD(CHKR6_CTRL, START_CONTINUOUS, 1, 7)
470 FIELD(CHKR6_CTRL, CLKB_MUX_CTRL, 1, 5)
471 FIELD(CHKR6_CTRL, CLKA_MUX_CTRL, 3, 1)
472 FIELD(CHKR6_CTRL, ENABLE, 1, 0)
473REG32(CHKR7_CLKA_UPPER, 0x1D0)
474 FIELD(CHKR7_CLKA_UPPER, THRSHLD, 32, 0)
475REG32(CHKR7_CLKA_LOWER, 0x1D4)
476 FIELD(CHKR7_CLKA_LOWER, THRSHLD, 32, 0)
477REG32(CHKR7_CLKB_CNT, 0x1D8)
478 FIELD(CHKR7_CLKB_CNT, VALUE, 32, 0)
479REG32(CHKR7_CTRL, 0x1DC)
480 FIELD(CHKR7_CTRL, START_SINGLE, 1, 8)
481 FIELD(CHKR7_CTRL, START_CONTINUOUS, 1, 7)
482 FIELD(CHKR7_CTRL, CLKB_MUX_CTRL, 1, 5)
483 FIELD(CHKR7_CTRL, CLKA_MUX_CTRL, 3, 1)
484 FIELD(CHKR7_CTRL, ENABLE, 1, 0)
485REG32(BOOT_MODE_USER, 0x200)
486 FIELD(BOOT_MODE_USER, ALT_BOOT_MODE, 4, 12)
487 FIELD(BOOT_MODE_USER, USE_ALT, 1, 8)
488 FIELD(BOOT_MODE_USER, BOOT_MODE, 4, 0)
489REG32(BOOT_MODE_POR, 0x204)
490 FIELD(BOOT_MODE_POR, BOOT_MODE2, 4, 8)
491 FIELD(BOOT_MODE_POR, BOOT_MODE1, 4, 4)
492 FIELD(BOOT_MODE_POR, BOOT_MODE0, 4, 0)
493REG32(RESET_CTRL, 0x218)
494 FIELD(RESET_CTRL, SOFT_RESET, 1, 4)
495 FIELD(RESET_CTRL, SRST_DIS, 1, 0)
496REG32(BLOCKONLY_RST, 0x21c)
497 FIELD(BLOCKONLY_RST, DEBUG_ONLY, 1, 0)
498REG32(RESET_REASON, 0x220)
499 FIELD(RESET_REASON, DEBUG_SYS, 1, 6)
500 FIELD(RESET_REASON, SOFT, 1, 5)
501 FIELD(RESET_REASON, SRST, 1, 4)
502 FIELD(RESET_REASON, PSONLY_RESET_REQ, 1, 3)
503 FIELD(RESET_REASON, PMU_SYS_RESET, 1, 2)
504 FIELD(RESET_REASON, EXTERNAL_POR, 1, 0)
505REG32(RST_LPD_IOU0, 0x230)
506 FIELD(RST_LPD_IOU0, GEM3_RESET, 1, 3)
507 FIELD(RST_LPD_IOU0, GEM2_RESET, 1, 2)
508 FIELD(RST_LPD_IOU0, GEM1_RESET, 1, 1)
509 FIELD(RST_LPD_IOU0, GEM0_RESET, 1, 0)
510REG32(RST_LPD_IOU1, 0x234)
511REG32(RST_LPD_IOU2, 0x238)
512 FIELD(RST_LPD_IOU2, TIMESTAMP_RESET, 1, 20)
513 FIELD(RST_LPD_IOU2, IOU_CC_RESET, 1, 19)
514 FIELD(RST_LPD_IOU2, GPIO_RESET, 1, 18)
515 FIELD(RST_LPD_IOU2, ADMA_RESET, 1, 17)
516 FIELD(RST_LPD_IOU2, NAND_RESET, 1, 16)
517 FIELD(RST_LPD_IOU2, SWDT_RESET, 1, 15)
518 FIELD(RST_LPD_IOU2, TTC3_RESET, 1, 14)
519 FIELD(RST_LPD_IOU2, TTC2_RESET, 1, 13)
520 FIELD(RST_LPD_IOU2, TTC1_RESET, 1, 12)
521 FIELD(RST_LPD_IOU2, TTC0_RESET, 1, 11)
522 FIELD(RST_LPD_IOU2, I2C1_RESET, 1, 10)
523 FIELD(RST_LPD_IOU2, I2C0_RESET, 1, 9)
524 FIELD(RST_LPD_IOU2, CAN1_RESET, 1, 8)
525 FIELD(RST_LPD_IOU2, CAN0_RESET, 1, 7)
526 FIELD(RST_LPD_IOU2, SDIO1_RESET, 1, 6)
527 FIELD(RST_LPD_IOU2, SDIO0_RESET, 1, 5)
528 FIELD(RST_LPD_IOU2, SPI1_RESET, 1, 4)
529 FIELD(RST_LPD_IOU2, SPI0_RESET, 1, 3)
530 FIELD(RST_LPD_IOU2, UART1_RESET, 1, 2)
531 FIELD(RST_LPD_IOU2, UART0_RESET, 1, 1)
532 FIELD(RST_LPD_IOU2, QSPI_RESET, 1, 0)
533REG32(RST_LPD_TOP, 0x23c)
534 FIELD(RST_LPD_TOP, FPD_RESET, 1, 23)
535 FIELD(RST_LPD_TOP, LPD_SWDT_RESET, 1, 20)
536 FIELD(RST_LPD_TOP, AFI_FM6_RESET, 1, 19)
537 FIELD(RST_LPD_TOP, SYSMON_RESET, 1, 17)
538 FIELD(RST_LPD_TOP, RTC_RESET, 1, 16)
539 FIELD(RST_LPD_TOP, APM_RESET, 1, 15)
540 FIELD(RST_LPD_TOP, IPI_RESET, 1, 14)
541 FIELD(RST_LPD_TOP, USB1_APB_RESET, 1, 11)
542 FIELD(RST_LPD_TOP, USB0_APB_RESET, 1, 10)
543 FIELD(RST_LPD_TOP, USB1_HIBERRESET, 1, 9)
544 FIELD(RST_LPD_TOP, USB0_HIBERRESET, 1, 8)
545 FIELD(RST_LPD_TOP, USB1_CORERESET, 1, 7)
546 FIELD(RST_LPD_TOP, USB0_CORERESET, 1, 6)
547 FIELD(RST_LPD_TOP, RPU_PGE_RESET, 1, 4)
548 FIELD(RST_LPD_TOP, RPU_OCM_RESET, 1, 3)
549 FIELD(RST_LPD_TOP, RPU_AMBA_RESET, 1, 2)
550 FIELD(RST_LPD_TOP, RPU_R51_RESET, 1, 1)
551 FIELD(RST_LPD_TOP, RPU_R50_RESET, 1, 0)
552REG32(RST_LPD_DBG, 0x240)
553 FIELD(RST_LPD_DBG, DBG_ACK, 1, 15)
554 FIELD(RST_LPD_DBG, RPU_DBG1_RESET, 1, 5)
555 FIELD(RST_LPD_DBG, RPU_DBG0_RESET, 1, 4)
556 FIELD(RST_LPD_DBG, DBG_LPD_RESET, 1, 1)
557 FIELD(RST_LPD_DBG, DBG_FPD_RESET, 1, 0)
558REG32(BANK3_CTRL0, 0x270)
559 FIELD(BANK3_CTRL0, DRIVE0, 10, 0)
560REG32(BANK3_CTRL1, 0x274)
561 FIELD(BANK3_CTRL1, DRIVE1, 10, 0)
562REG32(BANK3_CTRL2, 0x278)
563 FIELD(BANK3_CTRL2, SCHMITT_CMOS_N, 10, 0)
564REG32(BANK3_CTRL3, 0x27C)
565 FIELD(BANK3_CTRL3, PULL_HIGH_LOW_N, 10, 0)
566REG32(BANK3_CTRL4, 0x280)
567 FIELD(BANK3_CTRL4, PULL_ENABLE, 10, 0)
568REG32(BANK3_CTRL5, 0x284)
569 FIELD(BANK3_CTRL5, SLOW_FAST_SLEW_N, 10, 0)
570REG32(BANK3_STATUS, 0x288)
571 FIELD(BANK3_STATUS, VMODE_1P8_3P3_N, 1, 0)
572
573#define R_MAX (R_BANK3_STATUS + 1)
574
575typedef struct CRL_APB {
576 SysBusDevice parent_obj;
577 MemoryRegion iomem;
578 qemu_irq irq_ir;
579 qemu_irq mon_irq_ir;
580
581 uint32_t regs[R_MAX];
582 RegisterInfo regs_info[R_MAX];
583} CRL_APB;
584
585static void ir_update_irq(CRL_APB *s)
586{
587 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
588 qemu_set_irq(s->irq_ir, pending);
589}
590
591static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
592{
593 CRL_APB *s = XILINX_CRL_APB(reg->opaque);
594 ir_update_irq(s);
595}
596
597static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
598{
599 CRL_APB *s = XILINX_CRL_APB(reg->opaque);
600 uint32_t val = val64;
601
602 s->regs[R_IR_MASK] &= ~val;
603 ir_update_irq(s);
604 return 0;
605}
606
607static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
608{
609 CRL_APB *s = XILINX_CRL_APB(reg->opaque);
610 uint32_t val = val64;
611
612 s->regs[R_IR_MASK] |= val;
613 ir_update_irq(s);
614 return 0;
615}
616
617static void mon_ir_update_irq(CRL_APB *s)
618{
619 bool pending = s->regs[R_CLKMON_STATUS] & ~s->regs[R_CLKMON_MASK];
620 qemu_set_irq(s->mon_irq_ir, pending);
621}
622
623static void mon_ir_status_postw(RegisterInfo *reg, uint64_t val64)
624{
625 CRL_APB *s = XILINX_CRL_APB(reg->opaque);
626
627 mon_ir_update_irq(s);
628}
629
630static uint64_t mon_ir_enable_prew(RegisterInfo *reg, uint64_t val64)
631{
632 CRL_APB *s = XILINX_CRL_APB(reg->opaque);
633 uint32_t val = val64;
634
635 s->regs[R_CLKMON_MASK] &= ~val;
636 mon_ir_update_irq(s);
637 return 0;
638}
639
640static uint64_t mon_ir_disable_prew(RegisterInfo *reg, uint64_t val64)
641{
642 CRL_APB *s = XILINX_CRL_APB(reg->opaque);
643 uint32_t val = val64;
644
645 s->regs[R_CLKMON_MASK] |= val;
646 mon_ir_update_irq(s);
647 return 0;
648}
649
650static uint64_t mon_ir_trigger_prew(RegisterInfo *reg, uint64_t val64)
651{
652 CRL_APB *s = XILINX_CRL_APB(reg->opaque);
653 uint32_t val = val64;
654
655 s->regs[R_CLKMON_STATUS] |= (~s->regs[R_CLKMON_MASK]) & val;
656 mon_ir_update_irq(s);
657 return 0;
658}
659
660static RegisterAccessInfo crl_apb_regs_info[] = {
661 { .name = "ERR_CTRL", .decode.addr = A_ERR_CTRL,
662 },{ .name = "IR_STATUS", .decode.addr = A_IR_STATUS,
663 .w1c = 0x1,
664 .post_write = ir_status_postw,
665 },{ .name = "IR_MASK", .decode.addr = A_IR_MASK,
666 .reset = 0x1,
667 .ro = 0x1,
668 },{ .name = "IR_ENABLE", .decode.addr = A_IR_ENABLE,
669 .pre_write = ir_enable_prew,
670 },{ .name = "IR_DISABLE", .decode.addr = A_IR_DISABLE,
671 .pre_write = ir_disable_prew,
672 },{ .name = "CRL_WPROT", .decode.addr = A_CRL_WPROT,
673 },{ .name = "IOPLL_CTRL", .decode.addr = A_IOPLL_CTRL,
674 .reset = 0x2809,
675 .rsvd = 0xf88c80f6L,
676 },{ .name = "IOPLL_CFG", .decode.addr = A_IOPLL_CFG,
677 .rsvd = 0x1801210,
678 },{ .name = "IOPLL_FRAC_CFG", .decode.addr = A_IOPLL_FRAC_CFG,
679 .rsvd = 0x7e330000,
680 },{ .name = "RPLL_CTRL", .decode.addr = A_RPLL_CTRL,
681 .reset = 0x2809,
682 .rsvd = 0xf88c80f6L,
683 },{ .name = "RPLL_CFG", .decode.addr = A_RPLL_CFG,
684 .rsvd = 0x1801210,
685 },{ .name = "RPLL_FRAC_CFG", .decode.addr = A_RPLL_FRAC_CFG,
686 .rsvd = 0x7e330000,
687 },{ .name = "PLL_STATUS", .decode.addr = A_PLL_STATUS,
688 .reset = 0x1b,
689 .rsvd = 0xffffffc4L,
690 .ro = 0x1b,
691 },{ .name = "IOPLL_TO_FPD_CTRL", .decode.addr = A_IOPLL_TO_FPD_CTRL,
692 .reset = 0x400,
693 .rsvd = 0xc0ff,
694 },{ .name = "RPLL_TO_FPD_CTRL", .decode.addr = A_RPLL_TO_FPD_CTRL,
695 .reset = 0x400,
696 .rsvd = 0xc0ff,
697 },{ .name = "USB3_DUAL_REF_CTRL", .decode.addr = A_USB3_DUAL_REF_CTRL,
698 .reset = 0x52000,
699 .rsvd = 0xfdc0c0f8L,
700 },{ .name = "GEM0_REF_CTRL", .decode.addr = A_GEM0_REF_CTRL,
701 .reset = 0x2500,
702 .rsvd = 0xf9c0c0f8L,
703 },{ .name = "GEM1_REF_CTRL", .decode.addr = A_GEM1_REF_CTRL,
704 .reset = 0x2500,
705 .rsvd = 0xf9c0c0f8L,
706 },{ .name = "GEM2_REF_CTRL", .decode.addr = A_GEM2_REF_CTRL,
707 .reset = 0x2500,
708 .rsvd = 0xf9c0c0f8L,
709 },{ .name = "GEM3_REF_CTRL", .decode.addr = A_GEM3_REF_CTRL,
710 .reset = 0x2500,
711 .rsvd = 0xf9c0c0f8L,
712 },{ .name = "USB0_BUS_REF_CTRL", .decode.addr = A_USB0_BUS_REF_CTRL,
713 .reset = 0x52000,
714 .rsvd = 0xfdc0c0f8L,
715 },{ .name = "USB1_BUS_REF_CTRL", .decode.addr = A_USB1_BUS_REF_CTRL,
716 .reset = 0x12200,
717 .rsvd = 0xfdc0c0f8L,
718 },{ .name = "QSPI_REF_CTRL", .decode.addr = A_QSPI_REF_CTRL,
719 .reset = 0x1000800,
720 .rsvd = 0xfec0c0f8L,
721 },{ .name = "SDIO0_REF_CTRL", .decode.addr = A_SDIO0_REF_CTRL,
722 .reset = 0x1003000,
723 .rsvd = 0xfeffc0f8L,
724 },{ .name = "SDIO1_REF_CTRL", .decode.addr = A_SDIO1_REF_CTRL,
725 .reset = 0x1003f00,
726 .rsvd = 0xfeffc0f8L,
727 },{ .name = "UART0_REF_CTRL", .decode.addr = A_UART0_REF_CTRL,
728 .reset = 0x1000500,
729 .rsvd = 0xfeffc0f8L,
730 },{ .name = "UART1_REF_CTRL", .decode.addr = A_UART1_REF_CTRL,
731 .reset = 0x1500,
732 .rsvd = 0xfeffc0f8L,
733 },{ .name = "SPI0_REF_CTRL", .decode.addr = A_SPI0_REF_CTRL,
734 .reset = 0x1000500,
735 .rsvd = 0xfeffc0f8L,
736 },{ .name = "SPI1_REF_CTRL", .decode.addr = A_SPI1_REF_CTRL,
737 .reset = 0x1500,
738 .rsvd = 0xfeffc0f8L,
739 },{ .name = "CAN0_REF_CTRL", .decode.addr = A_CAN0_REF_CTRL,
740 .reset = 0x1000500,
741 .rsvd = 0xfeffc0f8L,
742 },{ .name = "CAN1_REF_CTRL", .decode.addr = A_CAN1_REF_CTRL,
743 .reset = 0x1500,
744 .rsvd = 0xfeffc0f8L,
745 },{ .name = "CPU_R5_CTRL", .decode.addr = A_CPU_R5_CTRL,
746 .reset = 0x600,
747 .rsvd = 0xfeffc0f8L,
748 },{ .name = "IOU_SWITCH_CTRL", .decode.addr = A_IOU_SWITCH_CTRL,
749 .reset = 0x1500,
750 .rsvd = 0xfeffc0f8L,
751 },{ .name = "CSU_PLL_CTRL", .decode.addr = A_CSU_PLL_CTRL,
752 .reset = 0x1001504,
753 .rsvd = 0xfeffc0f8L,
754 },{ .name = "PCAP_CTRL", .decode.addr = A_PCAP_CTRL,
755 .reset = 0x1500,
756 .rsvd = 0xfeffc0f8L,
757 },{ .name = "LPD_SWITCH_CTRL", .decode.addr = A_LPD_SWITCH_CTRL,
758 .reset = 0x1002000,
759 .rsvd = 0xfeffc0f8L,
760 },{ .name = "LPD_LSBUS_CTRL", .decode.addr = A_LPD_LSBUS_CTRL,
761 .reset = 0x1002000,
762 .rsvd = 0xfeffc0f8L,
763 },{ .name = "DBG_LPD_CTRL", .decode.addr = A_DBG_LPD_CTRL,
764 .reset = 0x2000,
765 .rsvd = 0xfeffc0f8L,
766 },{ .name = "NAND_REF_CTRL", .decode.addr = A_NAND_REF_CTRL,
767 .reset = 0x52000,
768 .rsvd = 0xfec0c0f8L,
769 },{ .name = "ADMA_REF_CTRL", .decode.addr = A_ADMA_REF_CTRL,
770 .reset = 0x2000,
771 .rsvd = 0xfeffc0f8L,
772 },{ .name = "PL0_REF_CTRL", .decode.addr = A_PL0_REF_CTRL,
773 .reset = 0x52000,
774 .rsvd = 0xfec0c0f8L,
775 },{ .name = "PL1_REF_CTRL", .decode.addr = A_PL1_REF_CTRL,
776 .reset = 0x52000,
777 .rsvd = 0xfec0c0f8L,
778 },{ .name = "PL2_REF_CTRL", .decode.addr = A_PL2_REF_CTRL,
779 .reset = 0x52000,
780 .rsvd = 0xfec0c0f8L,
781 },{ .name = "PL3_REF_CTRL", .decode.addr = A_PL3_REF_CTRL,
782 .reset = 0x52000,
783 .rsvd = 0xfec0c0f8L,
784 },{ .name = "PL0_THR_CTRL", .decode.addr = A_PL0_THR_CTRL,
785 .reset = 0x1,
786 .rsvd = 0x7ffc,
787 .ro = 0xffff8000L,
788 },{ .name = "PL0_THR_CNT", .decode.addr = A_PL0_THR_CNT,
789 },{ .name = "PL1_THR_CTRL", .decode.addr = A_PL1_THR_CTRL,
790 .reset = 0x1,
791 .rsvd = 0x7ffc,
792 .ro = 0xffff8000L,
793 },{ .name = "PL1_THR_CNT", .decode.addr = A_PL1_THR_CNT,
794 },{ .name = "PL2_THR_CTRL", .decode.addr = A_PL2_THR_CTRL,
795 .reset = 0x1,
796 .rsvd = 0x7ffc,
797 .ro = 0xffff8000L,
798 },{ .name = "PL2_THR_CNT", .decode.addr = A_PL2_THR_CNT,
799 },{ .name = "PL3_THR_CTRL", .decode.addr = A_PL3_THR_CTRL,
800 .reset = 0x1,
801 .rsvd = 0x7ffc,
802 .ro = 0xffff8000L,
803 },{ .name = "PL3_THR_CNT", .decode.addr = A_PL3_THR_CNT,
804 },{ .name = "GEM_TSU_REF_CTRL", .decode.addr = A_GEM_TSU_REF_CTRL,
805 .reset = 0x51000,
806 .rsvd = 0xfec0c0f8L,
807 },{ .name = "DLL_REF_CTRL", .decode.addr = A_DLL_REF_CTRL,
808 .rsvd = 0xf8,
809 },{ .name = "AMS_REF_CTRL", .decode.addr = A_AMS_REF_CTRL,
810 .reset = 0x1800,
811 .rsvd = 0xfeffc0f8L,
812 },{ .name = "I2C0_REF_CTRL", .decode.addr = A_I2C0_REF_CTRL,
813 .reset = 0x01000500,
814 .rsvd = 0xfec0c0f8L,
815 },{ .name = "I2C1_REF_CTRL", .decode.addr = A_I2C1_REF_CTRL,
816 .reset = 0x01000500,
817 .rsvd = 0xfec0c0f8L,
818 },{ .name = "TIMESTAMP_REF_CTRL", .decode.addr = A_TIMESTAMP_REF_CTRL,
819 .reset = 0x01001800,
820 .rsvd = 0xfeffc0f8L,
821 },{ .name = "SAFETY_CHK", .decode.addr = A_SAFETY_CHK,
822 .reset = 0x00000000,
823 },{ .name = "CLKMON_STATUS", .decode.addr = A_CLKMON_STATUS,
824 .reset = 0x00000000,
825 .w1c = 0xFFFF,
826 .post_write = mon_ir_status_postw,
827 },{ .name = "CLKMON_MASK", .decode.addr = A_CLKMON_MASK,
828 .reset = 0x0000FFFF,
829 .ro = 0xFFFF,
830 },{ .name = "CLKMON_ENABLE", .decode.addr = A_CLKMON_ENABLE,
831 .pre_write = mon_ir_enable_prew,
832 },{ .name = "CLKMON_DISABLE", .decode.addr = A_CLKMON_DISABLE,
833 .pre_write = mon_ir_disable_prew,
834 },{ .name = "CLKMON_TRIGGER", .decode.addr = A_CLKMON_TRIGGER,
835 .pre_write = mon_ir_trigger_prew,
836 },{ .name = "CHKR0_CLKA_UPPER", .decode.addr = A_CHKR0_CLKA_UPPER,
837 },{ .name = "CHKR0_CLKA_LOWER", .decode.addr = A_CHKR0_CLKA_LOWER,
838 },{ .name = "CHKR0_CLKB_CNT", .decode.addr = A_CHKR0_CLKB_CNT,
839 },{ .name = "CHKR0_CTRL", .decode.addr = A_CHKR0_CTRL,
840 },{ .name = "CHKR1_CLKA_UPPER", .decode.addr = A_CHKR1_CLKA_UPPER,
841 },{ .name = "CHKR1_CLKA_LOWER", .decode.addr = A_CHKR1_CLKA_LOWER,
842 },{ .name = "CHKR1_CLKB_CNT", .decode.addr = A_CHKR1_CLKB_CNT,
843 },{ .name = "CHKR1_CTRL", .decode.addr = A_CHKR1_CTRL,
844 },{ .name = "CHKR2_CLKA_UPPER", .decode.addr = A_CHKR2_CLKA_UPPER,
845 },{ .name = "CHKR2_CLKA_LOWER", .decode.addr = A_CHKR2_CLKA_LOWER,
846 },{ .name = "CHKR2_CLKB_CNT", .decode.addr = A_CHKR2_CLKB_CNT,
847 },{ .name = "CHKR2_CTRL", .decode.addr = A_CHKR2_CTRL,
848 },{ .name = "CHKR3_CLKA_UPPER", .decode.addr = A_CHKR3_CLKA_UPPER,
849 },{ .name = "CHKR3_CLKA_LOWER", .decode.addr = A_CHKR3_CLKA_LOWER,
850 },{ .name = "CHKR3_CLKB_CNT", .decode.addr = A_CHKR3_CLKB_CNT,
851 },{ .name = "CHKR3_CTRL", .decode.addr = A_CHKR3_CTRL,
852 },{ .name = "CHKR4_CLKA_UPPER", .decode.addr = A_CHKR4_CLKA_UPPER,
853 },{ .name = "CHKR4_CLKA_LOWER", .decode.addr = A_CHKR4_CLKA_LOWER,
854 },{ .name = "CHKR4_CLKB_CNT", .decode.addr = A_CHKR4_CLKB_CNT,
855 },{ .name = "CHKR4_CTRL", .decode.addr = A_CHKR4_CTRL,
856 },{ .name = "CHKR5_CLKA_UPPER", .decode.addr = A_CHKR5_CLKA_UPPER,
857 },{ .name = "CHKR5_CLKA_LOWER", .decode.addr = A_CHKR5_CLKA_LOWER,
858 },{ .name = "CHKR5_CLKB_CNT", .decode.addr = A_CHKR5_CLKB_CNT,
859 },{ .name = "CHKR5_CTRL", .decode.addr = A_CHKR5_CTRL,
860 },{ .name = "CHKR6_CLKA_UPPER", .decode.addr = A_CHKR6_CLKA_UPPER,
861 },{ .name = "CHKR6_CLKA_LOWER", .decode.addr = A_CHKR6_CLKA_LOWER,
862 },{ .name = "CHKR6_CLKB_CNT", .decode.addr = A_CHKR6_CLKB_CNT,
863 },{ .name = "CHKR6_CTRL", .decode.addr = A_CHKR6_CTRL,
864 },{ .name = "CHKR7_CLKA_UPPER", .decode.addr = A_CHKR7_CLKA_UPPER,
865 },{ .name = "CHKR7_CLKA_LOWER", .decode.addr = A_CHKR7_CLKA_LOWER,
866 },{ .name = "CHKR7_CLKB_CNT", .decode.addr = A_CHKR7_CLKB_CNT,
867 },{ .name = "CHKR7_CTRL", .decode.addr = A_CHKR7_CTRL,
868 },
869 { .name = "BOOT_MODE_USER", .decode.addr = A_BOOT_MODE_USER,
870 .reset = 0x4,
871 .rsvd = 0xf0,
872 },{ .name = "BOOT_MODE_POR", .decode.addr = A_BOOT_MODE_POR,
873 .rsvd = 0xf000,
874 .ro = 0xfff,
875 },{ .name = "RESET_CTRL", .decode.addr = A_RESET_CTRL,
876 .reset = 0x40,
877 .rsvd = 0xff8c,
878 .gpios = (RegisterGPIOMapping[]) {
879 { .name = "SRST_B", .bit_pos = 4, .width = 1 },
880 {},
881 },
882 },{ .name = "BLOCKONLY_RST", .decode.addr = A_BLOCKONLY_RST,
883 .rsvd = 0x7dcc,
884 .ro = 0x7dcc,
885 .w1c = 0x8233,
886 },{ .name = "RESET_REASON", .decode.addr = A_RESET_REASON,
887 .rsvd = 0x7e0c,
888 .ro = 0x7e0c,
889 .w1c = 0x81f3,
890 .reset = 0x1,
891 },{ .name = "RST_LPD_IOU0", .decode.addr = A_RST_LPD_IOU0,
892 .reset = 0xf,
893 .rsvd = 0xfff0,
894 },{ .name = "RST_LPD_IOU1", .decode.addr = A_RST_LPD_IOU1,
895 .rsvd = 0xff,
896 },{ .name = "RST_LPD_IOU2", .decode.addr = A_RST_LPD_IOU2,
897 .reset = 0x7ffff,
898 .rsvd = 0xfff00000L,
899 },{ .name = "RST_LPD_TOP", .decode.addr = A_RST_LPD_TOP,
900 .reset = 0x188fdf,
901 .rsvd = 0x643020,
902 .gpios = (RegisterGPIOMapping[]) {
903 { .name = "RST_R5", .bit_pos = 0, .num = 2 },
904 {},
905 },
906 .inhibit_reset = 1u << 31,
907 },{ .name = "RST_LPD_DBG", .decode.addr = A_RST_LPD_DBG,
908 .reset = 0x33,
909 .rsvd = 0xffcc,
910 },{ .name = "BANK3_CTRL0", .decode.addr = A_BANK3_CTRL0,
911 .reset = 0x3ff,
912 },{ .name = "BANK3_CTRL1", .decode.addr = A_BANK3_CTRL1,
913 .reset = 0x3ff,
914 },{ .name = "BANK3_CTRL2", .decode.addr = A_BANK3_CTRL2,
915 .reset = 0x3ff,
916 },{ .name = "BANK3_CTRL3", .decode.addr = A_BANK3_CTRL3,
917 .reset = 0x3ff,
918 },{ .name = "BANK3_CTRL4", .decode.addr = A_BANK3_CTRL4,
919 .reset = 0x3ff,
920 },{ .name = "BANK3_CTRL5", .decode.addr = A_BANK3_CTRL5,
921 .reset = 0x3ff,
922 },{ .name = "BANK3_STATUS", .decode.addr = A_BANK3_STATUS,
923 .reset = 0,
924 .ro = 1
925 }
926};
927
928static void crl_apb_reset(DeviceState *dev)
929{
930 CRL_APB *s = XILINX_CRL_APB(dev);
931 unsigned int i;
932 QemuOpts *opts = qemu_find_opts_singleton("boot-opts");
933 uint32_t boot_mode = qemu_opt_get_number(opts, "mode", 0);
934
935 assert(boot_mode < (1 << R_BOOT_MODE_USER_BOOT_MODE_LENGTH));
936
937 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
938 register_reset(&s->regs_info[i]);
939 }
940
941 s->regs[R_BOOT_MODE_POR] = deposit32(s->regs[R_BOOT_MODE_POR],
942 R_BOOT_MODE_POR_BOOT_MODE0_SHIFT,
943 R_BOOT_MODE_POR_BOOT_MODE0_LENGTH,
944 boot_mode);
945
946 s->regs[R_BOOT_MODE_USER] = deposit32(s->regs[R_BOOT_MODE_USER],
947 R_BOOT_MODE_USER_BOOT_MODE_SHIFT,
948 R_BOOT_MODE_USER_BOOT_MODE_LENGTH,
949 boot_mode);
950 ir_update_irq(s);
951}
952
953static uint64_t crl_apb_read(void *opaque, hwaddr addr, unsigned size)
954{
955 CRL_APB *s = XILINX_CRL_APB(opaque);
956 RegisterInfo *r = &s->regs_info[addr / 4];
957
958 if (!r->data) {
959 qemu_log_mask(LOG_GUEST_ERROR,
960 "%s: Decode error: read from 0x%" HWADDR_PRIx "\n",
961 object_get_canonical_path(OBJECT(s)),
962 addr);
963 return 0;
964 }
965 return register_read(r);
966}
967
968static void crl_apb_write(void *opaque, hwaddr addr, uint64_t value,
969 unsigned size)
970{
971 CRL_APB *s = XILINX_CRL_APB(opaque);
972 RegisterInfo *r = &s->regs_info[addr / 4];
973
974 if (!r->data) {
975 qemu_log_mask(LOG_GUEST_ERROR,
976 "%s: Decode error: write from 0x%" HWADDR_PRIx "=0x%" PRIx64 "\n",
977 object_get_canonical_path(OBJECT(s)),
978 addr, value);
979 return;
980 }
981 register_write(r, value, ~0);
982}
983
984static const MemoryRegionOps crl_apb_ops = {
985 .read = crl_apb_read,
986 .write = crl_apb_write,
987 .endianness = DEVICE_LITTLE_ENDIAN,
988 .valid = {
989 .min_access_size = 4,
990 .max_access_size = 4,
991 },
992};
993
994static void crl_apb_realize(DeviceState *dev, Error **errp)
995{
996 CRL_APB *s = XILINX_CRL_APB(dev);
997 const char *prefix = object_get_canonical_path(OBJECT(dev));
998 unsigned int i;
999
1000 for (i = 0; i < ARRAY_SIZE(crl_apb_regs_info); ++i) {
1001 RegisterInfo *r = &s->regs_info[crl_apb_regs_info[i].decode.addr/4];
1002
1003 *r = (RegisterInfo) {
1004 .data = (uint8_t *)&s->regs[
1005 crl_apb_regs_info[i].decode.addr/4],
1006 .data_size = sizeof(uint32_t),
1007 .access = &crl_apb_regs_info[i],
1008 .debug = XILINX_CRL_APB_ERR_DEBUG,
1009 .prefix = prefix,
1010 .opaque = s,
1011 };
1012 register_init(r);
1013 qdev_pass_all_gpios(DEVICE(r), dev);
1014 }
1015}
1016
1017static void crl_apb_init(Object *obj)
1018{
1019 CRL_APB *s = XILINX_CRL_APB(obj);
1020 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1021
1022 memory_region_init_io(&s->iomem, obj, &crl_apb_ops, s,
1023 TYPE_XILINX_CRL_APB, R_MAX * 4);
1024 sysbus_init_mmio(sbd, &s->iomem);
1025 sysbus_init_irq(sbd, &s->irq_ir);
1026 qdev_init_gpio_out_named(DEVICE(obj), &s->mon_irq_ir, "clkmon_error_out",
1027 1);
1028}
1029
1030static const VMStateDescription vmstate_crl_apb = {
1031 .name = TYPE_XILINX_CRL_APB,
1032 .version_id = 1,
1033 .minimum_version_id = 1,
1034 .minimum_version_id_old = 1,
1035 .fields = (VMStateField[]) {
1036 VMSTATE_UINT32_ARRAY(regs, CRL_APB, R_MAX),
1037 VMSTATE_END_OF_LIST(),
1038 }
1039};
1040
1041static const FDTGenericGPIOSet crl_gpios[] = {
1042 {
1043 .names = &fdt_generic_gpio_name_set_gpio,
1044 .gpios = (FDTGenericGPIOConnection[]) {
1045 { .name = "RST_R5", .fdt_index = 0, .range = 2 },
1046 { .name = "SRST_B", .fdt_index = 2 },
1047 { },
1048 }
1049 },
1050 { },
1051};
1052
1053static const FDTGenericGPIOSet crl_client_gpios [] = {
1054 {
1055 .names = &fdt_generic_gpio_name_set_gpio,
1056 .gpios = (FDTGenericGPIOConnection []) {
1057 { .name = "clkmon_error_out", .fdt_index = 0, .range = 1 },
1058 { },
1059 },
1060 },
1061 { },
1062};
1063
1064static void crl_apb_class_init(ObjectClass *klass, void *data)
1065{
1066 DeviceClass *dc = DEVICE_CLASS(klass);
1067 FDTGenericGPIOClass *fggc = FDT_GENERIC_GPIO_CLASS(klass);
1068
1069 dc->reset = crl_apb_reset;
1070 dc->realize = crl_apb_realize;
1071 dc->vmsd = &vmstate_crl_apb;
1072 fggc->controller_gpios = crl_gpios;
1073 fggc->client_gpios = crl_client_gpios;
1074}
1075
1076static const TypeInfo crl_apb_info = {
1077 .name = TYPE_XILINX_CRL_APB,
1078 .parent = TYPE_SYS_BUS_DEVICE,
1079 .instance_size = sizeof(CRL_APB),
1080 .class_init = crl_apb_class_init,
1081 .instance_init = crl_apb_init,
1082 .interfaces = (InterfaceInfo[]) {
1083 { TYPE_FDT_GENERIC_GPIO },
1084 { }
1085 },
1086};
1087
1088static void crl_apb_register_types(void)
1089{
1090 type_register_static(&crl_apb_info);
1091}
1092
1093type_init(crl_apb_register_types)
1094
