qemu/hw/misc/xilinx_zynqmp_pmu_global.c
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   1/*
   2 * QEMU model of the PMU_GLOBAL
   3 *
   4 * Copyright (c) 2014 Xilinx Inc.
   5 *
   6 * Partly autogenerated by xregqemu.py 2014-09-01.
   7 * Written by Edgar E. Iglesias.
   8 *
   9 * Permission is hereby granted, free of charge, to any person obtaining a copy
  10 * of this software and associated documentation files (the "Software"), to deal
  11 * in the Software without restriction, including without limitation the rights
  12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13 * copies of the Software, and to permit persons to whom the Software is
  14 * furnished to do so, subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in
  17 * all copies or substantial portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25 * THE SOFTWARE.
  26 */
  27
  28#include "qemu/osdep.h"
  29#include "hw/sysbus.h"
  30#include "hw/register.h"
  31#include "qemu/bitops.h"
  32#include "qemu/log.h"
  33
  34#include "hw/fdt_generic_util.h"
  35
  36#ifndef XILINX_PMU_GLOBAL_ERR_DEBUG
  37#define XILINX_PMU_GLOBAL_ERR_DEBUG 0
  38#endif
  39
  40#define TYPE_XILINX_PMU_GLOBAL "xlnx.pmu_global"
  41
  42#define XILINX_PMU_GLOBAL(obj) \
  43     OBJECT_CHECK(PMU_GLOBAL, (obj), TYPE_XILINX_PMU_GLOBAL)
  44
  45REG32(GLOBAL_CNTRL, 0x0)
  46    FIELD(GLOBAL_CNTRL, MB_SLEEP, 1, 16)
  47    FIELD(GLOBAL_CNTRL, WRITE_QOS, 4, 12)
  48    FIELD(GLOBAL_CNTRL, READ_QOS, 4, 8)
  49    FIELD(GLOBAL_CNTRL, FW_IS_PRESENT, 1, 4)
  50    FIELD(GLOBAL_CNTRL, COHERENT, 1, 2)
  51    FIELD(GLOBAL_CNTRL, SLVERR_ENABLE, 1, 1)
  52    FIELD(GLOBAL_CNTRL, DONT_SLEEP, 1, 0)
  53REG32(PS_CNTRL, 0x4)
  54    FIELD(PS_CNTRL, PROG_GATE_STATUS, 1, 16)
  55    FIELD(PS_CNTRL, PROG_ENABLE, 1, 1)
  56    FIELD(PS_CNTRL, PROG_GATE, 1, 0)
  57REG32(APU_PWR_STATUS_INIT, 0x8)
  58    FIELD(APU_PWR_STATUS_INIT, ACPU3, 1, 3)
  59    FIELD(APU_PWR_STATUS_INIT, ACPU2, 1, 2)
  60    FIELD(APU_PWR_STATUS_INIT, ACPU1, 1, 1)
  61    FIELD(APU_PWR_STATUS_INIT, ACPU0, 1, 0)
  62REG32(ADDR_ERROR_STATUS, 0x10)
  63    FIELD(ADDR_ERROR_STATUS, STATUS, 1, 0)
  64REG32(ADDR_ERROR_INT_MASK, 0x14)
  65    FIELD(ADDR_ERROR_INT_MASK, MASK, 1, 0)
  66REG32(ADDR_ERROR_INT_EN, 0x18)
  67    FIELD(ADDR_ERROR_INT_EN, ENABLE, 1, 0)
  68REG32(ADDR_ERROR_INT_DIS, 0x1c)
  69    FIELD(ADDR_ERROR_INT_DIS, DISABLE, 1, 0)
  70REG32(GLOBAL_GEN_STORAGE0, 0x30)
  71REG32(GLOBAL_GEN_STORAGE1, 0x34)
  72REG32(GLOBAL_GEN_STORAGE2, 0x38)
  73REG32(GLOBAL_GEN_STORAGE3, 0x3c)
  74REG32(GLOBAL_GEN_STORAGE4, 0x40)
  75REG32(GLOBAL_GEN_STORAGE5, 0x44)
  76REG32(GLOBAL_GEN_STORAGE6, 0x48)
  77REG32(PERS_GLOB_GEN_STORAGE0, 0x50)
  78REG32(PERS_GLOB_GEN_STORAGE1, 0x54)
  79REG32(PERS_GLOB_GEN_STORAGE2, 0x58)
  80REG32(PERS_GLOB_GEN_STORAGE3, 0x5c)
  81REG32(PERS_GLOB_GEN_STORAGE4, 0x60)
  82REG32(PERS_GLOB_GEN_STORAGE5, 0x64)
  83REG32(PERS_GLOB_GEN_STORAGE6, 0x68)
  84REG32(PERS_GLOB_GEN_STORAGE7, 0x6c)
  85REG32(DDR_CNTRL, 0x70)
  86    FIELD(DDR_CNTRL, RET, 1, 0)
  87REG32(PWR_STATE, 0x100)
  88    FIELD(PWR_STATE, PL, 1, 23)
  89    FIELD(PWR_STATE, FP, 1, 22)
  90    FIELD(PWR_STATE, USB1, 1, 21)
  91    FIELD(PWR_STATE, USB0, 1, 20)
  92    FIELD(PWR_STATE, OCM_BANK3, 1, 19)
  93    FIELD(PWR_STATE, OCM_BANK2, 1, 18)
  94    FIELD(PWR_STATE, OCM_BANK1, 1, 17)
  95    FIELD(PWR_STATE, OCM_BANK0, 1, 16)
  96    FIELD(PWR_STATE, TCM1B, 1, 15)
  97    FIELD(PWR_STATE, TCM1A, 1, 14)
  98    FIELD(PWR_STATE, TCM0B, 1, 13)
  99    FIELD(PWR_STATE, TCM0A, 1, 12)
 100    FIELD(PWR_STATE, R5_1, 1, 11)
 101    FIELD(PWR_STATE, R5_0, 1, 10)
 102    FIELD(PWR_STATE, L2_BANK0, 1, 7)
 103    FIELD(PWR_STATE, PP1, 1, 5)
 104    FIELD(PWR_STATE, PP0, 1, 4)
 105    FIELD(PWR_STATE, ACPU3, 1, 3)
 106    FIELD(PWR_STATE, ACPU2, 1, 2)
 107    FIELD(PWR_STATE, ACPU1, 1, 1)
 108    FIELD(PWR_STATE, ACPU0, 1, 0)
 109REG32(AUX_PWR_STATE, 0x104)
 110    FIELD(AUX_PWR_STATE, ACPU3_EMULATION, 1, 31)
 111    FIELD(AUX_PWR_STATE, ACPU2_EMULATION, 1, 30)
 112    FIELD(AUX_PWR_STATE, ACPU1_EMULATION, 1, 29)
 113    FIELD(AUX_PWR_STATE, ACPU0_EMULATION, 1, 28)
 114    FIELD(AUX_PWR_STATE, RPU_EMULATION, 1, 27)
 115    FIELD(AUX_PWR_STATE, OCM_BANK3, 1, 19)
 116    FIELD(AUX_PWR_STATE, OCM_BANK2, 1, 18)
 117    FIELD(AUX_PWR_STATE, OCM_BANK1, 1, 17)
 118    FIELD(AUX_PWR_STATE, OCM_BANK0, 1, 16)
 119    FIELD(AUX_PWR_STATE, TCM1B, 1, 15)
 120    FIELD(AUX_PWR_STATE, TCM1A, 1, 14)
 121    FIELD(AUX_PWR_STATE, TCM0B, 1, 13)
 122    FIELD(AUX_PWR_STATE, TCM0A, 1, 12)
 123    FIELD(AUX_PWR_STATE, L2_BANK0, 1, 7)
 124REG32(RAM_RET_CNTRL, 0x108)
 125    FIELD(RAM_RET_CNTRL, OCM_BANK3, 1, 19)
 126    FIELD(RAM_RET_CNTRL, OCM_BANK2, 1, 18)
 127    FIELD(RAM_RET_CNTRL, OCM_BANK1, 1, 17)
 128    FIELD(RAM_RET_CNTRL, OCM_BANK0, 1, 16)
 129    FIELD(RAM_RET_CNTRL, TCM1B, 1, 15)
 130    FIELD(RAM_RET_CNTRL, TCM1A, 1, 14)
 131    FIELD(RAM_RET_CNTRL, TCM0B, 1, 13)
 132    FIELD(RAM_RET_CNTRL, TCM0A, 1, 12)
 133    FIELD(RAM_RET_CNTRL, L2_BANK0, 1, 7)
 134REG32(PWR_SUPPLY_STATUS, 0x10c)
 135    FIELD(PWR_SUPPLY_STATUS, VCC_INT, 1, 1)
 136    FIELD(PWR_SUPPLY_STATUS, VCC_PSINTFP, 1, 0)
 137REG32(REQ_PWRUP_STATUS, 0x110)
 138    FIELD(REQ_PWRUP_STATUS, PL, 1, 23)
 139    FIELD(REQ_PWRUP_STATUS, FP, 1, 22)
 140    FIELD(REQ_PWRUP_STATUS, USB1, 1, 21)
 141    FIELD(REQ_PWRUP_STATUS, USB0, 1, 20)
 142    FIELD(REQ_PWRUP_STATUS, OCM_BANK3, 1, 19)
 143    FIELD(REQ_PWRUP_STATUS, OCM_BANK2, 1, 18)
 144    FIELD(REQ_PWRUP_STATUS, OCM_BANK1, 1, 17)
 145    FIELD(REQ_PWRUP_STATUS, OCM_BANK0, 1, 16)
 146    FIELD(REQ_PWRUP_STATUS, TCM1B, 1, 15)
 147    FIELD(REQ_PWRUP_STATUS, TCM1A, 1, 14)
 148    FIELD(REQ_PWRUP_STATUS, TCM0B, 1, 13)
 149    FIELD(REQ_PWRUP_STATUS, TCM0A, 1, 12)
 150    FIELD(REQ_PWRUP_STATUS, RPU, 1, 10)
 151    FIELD(REQ_PWRUP_STATUS, L2_BANK0, 1, 7)
 152    FIELD(REQ_PWRUP_STATUS, PP1, 1, 5)
 153    FIELD(REQ_PWRUP_STATUS, PP0, 1, 4)
 154    FIELD(REQ_PWRUP_STATUS, ACPU3, 1, 3)
 155    FIELD(REQ_PWRUP_STATUS, ACPU2, 1, 2)
 156    FIELD(REQ_PWRUP_STATUS, ACPU1, 1, 1)
 157    FIELD(REQ_PWRUP_STATUS, ACPU0, 1, 0)
 158REG32(REQ_PWRUP_INT_MASK, 0x114)
 159    FIELD(REQ_PWRUP_INT_MASK, PL, 1, 23)
 160    FIELD(REQ_PWRUP_INT_MASK, FP, 1, 22)
 161    FIELD(REQ_PWRUP_INT_MASK, USB1, 1, 21)
 162    FIELD(REQ_PWRUP_INT_MASK, USB0, 1, 20)
 163    FIELD(REQ_PWRUP_INT_MASK, OCM_BANK3, 1, 19)
 164    FIELD(REQ_PWRUP_INT_MASK, OCM_BANK2, 1, 18)
 165    FIELD(REQ_PWRUP_INT_MASK, OCM_BANK1, 1, 17)
 166    FIELD(REQ_PWRUP_INT_MASK, OCM_BANK0, 1, 16)
 167    FIELD(REQ_PWRUP_INT_MASK, TCM1B, 1, 15)
 168    FIELD(REQ_PWRUP_INT_MASK, TCM1A, 1, 14)
 169    FIELD(REQ_PWRUP_INT_MASK, TCM0B, 1, 13)
 170    FIELD(REQ_PWRUP_INT_MASK, TCM0A, 1, 12)
 171    FIELD(REQ_PWRUP_INT_MASK, RPU, 1, 10)
 172    FIELD(REQ_PWRUP_INT_MASK, L2_BANK0, 1, 7)
 173    FIELD(REQ_PWRUP_INT_MASK, PP1, 1, 5)
 174    FIELD(REQ_PWRUP_INT_MASK, PP0, 1, 4)
 175    FIELD(REQ_PWRUP_INT_MASK, ACPU3, 1, 3)
 176    FIELD(REQ_PWRUP_INT_MASK, ACPU2, 1, 2)
 177    FIELD(REQ_PWRUP_INT_MASK, ACPU1, 1, 1)
 178    FIELD(REQ_PWRUP_INT_MASK, ACPU0, 1, 0)
 179REG32(REQ_PWRUP_INT_EN, 0x118)
 180    FIELD(REQ_PWRUP_INT_EN, PL, 1, 23)
 181    FIELD(REQ_PWRUP_INT_EN, FP, 1, 22)
 182    FIELD(REQ_PWRUP_INT_EN, USB1, 1, 21)
 183    FIELD(REQ_PWRUP_INT_EN, USB0, 1, 20)
 184    FIELD(REQ_PWRUP_INT_EN, OCM_BANK3, 1, 19)
 185    FIELD(REQ_PWRUP_INT_EN, OCM_BANK2, 1, 18)
 186    FIELD(REQ_PWRUP_INT_EN, OCM_BANK1, 1, 17)
 187    FIELD(REQ_PWRUP_INT_EN, OCM_BANK0, 1, 16)
 188    FIELD(REQ_PWRUP_INT_EN, TCM1B, 1, 15)
 189    FIELD(REQ_PWRUP_INT_EN, TCM1A, 1, 14)
 190    FIELD(REQ_PWRUP_INT_EN, TCM0B, 1, 13)
 191    FIELD(REQ_PWRUP_INT_EN, TCM0A, 1, 12)
 192    FIELD(REQ_PWRUP_INT_EN, RPU, 1, 10)
 193    FIELD(REQ_PWRUP_INT_EN, L2_BANK0, 1, 7)
 194    FIELD(REQ_PWRUP_INT_EN, PP1, 1, 5)
 195    FIELD(REQ_PWRUP_INT_EN, PP0, 1, 4)
 196    FIELD(REQ_PWRUP_INT_EN, ACPU3, 1, 3)
 197    FIELD(REQ_PWRUP_INT_EN, ACPU2, 1, 2)
 198    FIELD(REQ_PWRUP_INT_EN, ACPU1, 1, 1)
 199    FIELD(REQ_PWRUP_INT_EN, ACPU0, 1, 0)
 200REG32(REQ_PWRUP_INT_DIS, 0x11c)
 201    FIELD(REQ_PWRUP_INT_DIS, PL, 1, 23)
 202    FIELD(REQ_PWRUP_INT_DIS, FP, 1, 22)
 203    FIELD(REQ_PWRUP_INT_DIS, USB1, 1, 21)
 204    FIELD(REQ_PWRUP_INT_DIS, USB0, 1, 20)
 205    FIELD(REQ_PWRUP_INT_DIS, OCM_BANK3, 1, 19)
 206    FIELD(REQ_PWRUP_INT_DIS, OCM_BANK2, 1, 18)
 207    FIELD(REQ_PWRUP_INT_DIS, OCM_BANK1, 1, 17)
 208    FIELD(REQ_PWRUP_INT_DIS, OCM_BANK0, 1, 16)
 209    FIELD(REQ_PWRUP_INT_DIS, TCM1B, 1, 15)
 210    FIELD(REQ_PWRUP_INT_DIS, TCM1A, 1, 14)
 211    FIELD(REQ_PWRUP_INT_DIS, TCM0B, 1, 13)
 212    FIELD(REQ_PWRUP_INT_DIS, TCM0A, 1, 12)
 213    FIELD(REQ_PWRUP_INT_DIS, RPU, 1, 10)
 214    FIELD(REQ_PWRUP_INT_DIS, L2_BANK0, 1, 7)
 215    FIELD(REQ_PWRUP_INT_DIS, PP1, 1, 5)
 216    FIELD(REQ_PWRUP_INT_DIS, PP0, 1, 4)
 217    FIELD(REQ_PWRUP_INT_DIS, ACPU3, 1, 3)
 218    FIELD(REQ_PWRUP_INT_DIS, ACPU2, 1, 2)
 219    FIELD(REQ_PWRUP_INT_DIS, ACPU1, 1, 1)
 220    FIELD(REQ_PWRUP_INT_DIS, ACPU0, 1, 0)
 221REG32(REQ_PWRUP_TRIG, 0x120)
 222    FIELD(REQ_PWRUP_TRIG, PL, 1, 23)
 223    FIELD(REQ_PWRUP_TRIG, FP, 1, 22)
 224    FIELD(REQ_PWRUP_TRIG, USB1, 1, 21)
 225    FIELD(REQ_PWRUP_TRIG, USB0, 1, 20)
 226    FIELD(REQ_PWRUP_TRIG, OCM_BANK3, 1, 19)
 227    FIELD(REQ_PWRUP_TRIG, OCM_BANK2, 1, 18)
 228    FIELD(REQ_PWRUP_TRIG, OCM_BANK1, 1, 17)
 229    FIELD(REQ_PWRUP_TRIG, OCM_BANK0, 1, 16)
 230    FIELD(REQ_PWRUP_TRIG, TCM1B, 1, 15)
 231    FIELD(REQ_PWRUP_TRIG, TCM1A, 1, 14)
 232    FIELD(REQ_PWRUP_TRIG, TCM0B, 1, 13)
 233    FIELD(REQ_PWRUP_TRIG, TCM0A, 1, 12)
 234    FIELD(REQ_PWRUP_TRIG, RPU, 1, 10)
 235    FIELD(REQ_PWRUP_TRIG, L2_BANK0, 1, 7)
 236    FIELD(REQ_PWRUP_TRIG, PP1, 1, 5)
 237    FIELD(REQ_PWRUP_TRIG, PP0, 1, 4)
 238    FIELD(REQ_PWRUP_TRIG, ACPU3, 1, 3)
 239    FIELD(REQ_PWRUP_TRIG, ACPU2, 1, 2)
 240    FIELD(REQ_PWRUP_TRIG, ACPU1, 1, 1)
 241    FIELD(REQ_PWRUP_TRIG, ACPU0, 1, 0)
 242REG32(REQ_PWRDWN_STATUS, 0x210)
 243    FIELD(REQ_PWRDWN_STATUS, PL, 1, 23)
 244    FIELD(REQ_PWRDWN_STATUS, FP, 1, 22)
 245    FIELD(REQ_PWRDWN_STATUS, USB1, 1, 21)
 246    FIELD(REQ_PWRDWN_STATUS, USB0, 1, 20)
 247    FIELD(REQ_PWRDWN_STATUS, OCM_BANK3, 1, 19)
 248    FIELD(REQ_PWRDWN_STATUS, OCM_BANK2, 1, 18)
 249    FIELD(REQ_PWRDWN_STATUS, OCM_BANK1, 1, 17)
 250    FIELD(REQ_PWRDWN_STATUS, OCM_BANK0, 1, 16)
 251    FIELD(REQ_PWRDWN_STATUS, TCM1B, 1, 15)
 252    FIELD(REQ_PWRDWN_STATUS, TCM1A, 1, 14)
 253    FIELD(REQ_PWRDWN_STATUS, TCM0B, 1, 13)
 254    FIELD(REQ_PWRDWN_STATUS, TCM0A, 1, 12)
 255    FIELD(REQ_PWRDWN_STATUS, RPU, 1, 10)
 256    FIELD(REQ_PWRDWN_STATUS, L2_BANK0, 1, 7)
 257    FIELD(REQ_PWRDWN_STATUS, PP1, 1, 5)
 258    FIELD(REQ_PWRDWN_STATUS, PP0, 1, 4)
 259    FIELD(REQ_PWRDWN_STATUS, ACPU3, 1, 3)
 260    FIELD(REQ_PWRDWN_STATUS, ACPU2, 1, 2)
 261    FIELD(REQ_PWRDWN_STATUS, ACPU1, 1, 1)
 262    FIELD(REQ_PWRDWN_STATUS, ACPU0, 1, 0)
 263REG32(REQ_PWRDWN_INT_MASK, 0x214)
 264    FIELD(REQ_PWRDWN_INT_MASK, PL, 1, 23)
 265    FIELD(REQ_PWRDWN_INT_MASK, FP, 1, 22)
 266    FIELD(REQ_PWRDWN_INT_MASK, USB1, 1, 21)
 267    FIELD(REQ_PWRDWN_INT_MASK, USB0, 1, 20)
 268    FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK3, 1, 19)
 269    FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK2, 1, 18)
 270    FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK1, 1, 17)
 271    FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK0, 1, 16)
 272    FIELD(REQ_PWRDWN_INT_MASK, TCM1B, 1, 15)
 273    FIELD(REQ_PWRDWN_INT_MASK, TCM1A, 1, 14)
 274    FIELD(REQ_PWRDWN_INT_MASK, TCM0B, 1, 13)
 275    FIELD(REQ_PWRDWN_INT_MASK, TCM0A, 1, 12)
 276    FIELD(REQ_PWRDWN_INT_MASK, RPU, 1, 10)
 277    FIELD(REQ_PWRDWN_INT_MASK, L2_BANK0, 1, 7)
 278    FIELD(REQ_PWRDWN_INT_MASK, PP1, 1, 5)
 279    FIELD(REQ_PWRDWN_INT_MASK, PP0, 1, 4)
 280    FIELD(REQ_PWRDWN_INT_MASK, ACPU3, 1, 3)
 281    FIELD(REQ_PWRDWN_INT_MASK, ACPU2, 1, 2)
 282    FIELD(REQ_PWRDWN_INT_MASK, ACPU1, 1, 1)
 283    FIELD(REQ_PWRDWN_INT_MASK, ACPU0, 1, 0)
 284REG32(REQ_PWRDWN_INT_EN, 0x218)
 285    FIELD(REQ_PWRDWN_INT_EN, PL, 1, 23)
 286    FIELD(REQ_PWRDWN_INT_EN, FP, 1, 22)
 287    FIELD(REQ_PWRDWN_INT_EN, USB1, 1, 21)
 288    FIELD(REQ_PWRDWN_INT_EN, USB0, 1, 20)
 289    FIELD(REQ_PWRDWN_INT_EN, OCM_BANK3, 1, 19)
 290    FIELD(REQ_PWRDWN_INT_EN, OCM_BANK2, 1, 18)
 291    FIELD(REQ_PWRDWN_INT_EN, OCM_BANK1, 1, 17)
 292    FIELD(REQ_PWRDWN_INT_EN, OCM_BANK0, 1, 16)
 293    FIELD(REQ_PWRDWN_INT_EN, TCM1B, 1, 15)
 294    FIELD(REQ_PWRDWN_INT_EN, TCM1A, 1, 14)
 295    FIELD(REQ_PWRDWN_INT_EN, TCM0B, 1, 13)
 296    FIELD(REQ_PWRDWN_INT_EN, TCM0A, 1, 12)
 297    FIELD(REQ_PWRDWN_INT_EN, RPU, 1, 10)
 298    FIELD(REQ_PWRDWN_INT_EN, L2_BANK0, 1, 7)
 299    FIELD(REQ_PWRDWN_INT_EN, PP1, 1, 5)
 300    FIELD(REQ_PWRDWN_INT_EN, PP0, 1, 4)
 301    FIELD(REQ_PWRDWN_INT_EN, ACPU3, 1, 3)
 302    FIELD(REQ_PWRDWN_INT_EN, ACPU2, 1, 2)
 303    FIELD(REQ_PWRDWN_INT_EN, ACPU1, 1, 1)
 304    FIELD(REQ_PWRDWN_INT_EN, ACPU0, 1, 0)
 305REG32(REQ_PWRDWN_INT_DIS, 0x21c)
 306    FIELD(REQ_PWRDWN_INT_DIS, PL, 1, 23)
 307    FIELD(REQ_PWRDWN_INT_DIS, FP, 1, 22)
 308    FIELD(REQ_PWRDWN_INT_DIS, USB1, 1, 21)
 309    FIELD(REQ_PWRDWN_INT_DIS, USB0, 1, 20)
 310    FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK3, 1, 19)
 311    FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK2, 1, 18)
 312    FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK1, 1, 17)
 313    FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK0, 1, 16)
 314    FIELD(REQ_PWRDWN_INT_DIS, TCM1B, 1, 15)
 315    FIELD(REQ_PWRDWN_INT_DIS, TCM1A, 1, 14)
 316    FIELD(REQ_PWRDWN_INT_DIS, TCM0B, 1, 13)
 317    FIELD(REQ_PWRDWN_INT_DIS, TCM0A, 1, 12)
 318    FIELD(REQ_PWRDWN_INT_DIS, RPU, 1, 10)
 319    FIELD(REQ_PWRDWN_INT_DIS, L2_BANK0, 1, 7)
 320    FIELD(REQ_PWRDWN_INT_DIS, PP1, 1, 5)
 321    FIELD(REQ_PWRDWN_INT_DIS, PP0, 1, 4)
 322    FIELD(REQ_PWRDWN_INT_DIS, ACPU3, 1, 3)
 323    FIELD(REQ_PWRDWN_INT_DIS, ACPU2, 1, 2)
 324    FIELD(REQ_PWRDWN_INT_DIS, ACPU1, 1, 1)
 325    FIELD(REQ_PWRDWN_INT_DIS, ACPU0, 1, 0)
 326REG32(REQ_PWRDWN_TRIG, 0x220)
 327    FIELD(REQ_PWRDWN_TRIG, PL, 1, 23)
 328    FIELD(REQ_PWRDWN_TRIG, FP, 1, 22)
 329    FIELD(REQ_PWRDWN_TRIG, USB1, 1, 21)
 330    FIELD(REQ_PWRDWN_TRIG, USB0, 1, 20)
 331    FIELD(REQ_PWRDWN_TRIG, OCM_BANK3, 1, 19)
 332    FIELD(REQ_PWRDWN_TRIG, OCM_BANK2, 1, 18)
 333    FIELD(REQ_PWRDWN_TRIG, OCM_BANK1, 1, 17)
 334    FIELD(REQ_PWRDWN_TRIG, OCM_BANK0, 1, 16)
 335    FIELD(REQ_PWRDWN_TRIG, TCM1B, 1, 15)
 336    FIELD(REQ_PWRDWN_TRIG, TCM1A, 1, 14)
 337    FIELD(REQ_PWRDWN_TRIG, TCM0B, 1, 13)
 338    FIELD(REQ_PWRDWN_TRIG, TCM0A, 1, 12)
 339    FIELD(REQ_PWRDWN_TRIG, RPU, 1, 10)
 340    FIELD(REQ_PWRDWN_TRIG, L2_BANK0, 1, 7)
 341    FIELD(REQ_PWRDWN_TRIG, PP1, 1, 5)
 342    FIELD(REQ_PWRDWN_TRIG, PP0, 1, 4)
 343    FIELD(REQ_PWRDWN_TRIG, ACPU3, 1, 3)
 344    FIELD(REQ_PWRDWN_TRIG, ACPU2, 1, 2)
 345    FIELD(REQ_PWRDWN_TRIG, ACPU1, 1, 1)
 346    FIELD(REQ_PWRDWN_TRIG, ACPU0, 1, 0)
 347REG32(REQ_ISO_STATUS, 0x310)
 348    FIELD(REQ_ISO_STATUS, FP_LOCKED, 1, 4)
 349    FIELD(REQ_ISO_STATUS, PL, 1, 1)
 350    FIELD(REQ_ISO_STATUS, FP, 1, 0)
 351REG32(REQ_ISO_INT_MASK, 0x314)
 352    FIELD(REQ_ISO_INT_MASK, FP_LOCKED, 1, 4)
 353    FIELD(REQ_ISO_INT_MASK, PL, 1, 1)
 354    FIELD(REQ_ISO_INT_MASK, FP, 1, 0)
 355REG32(REQ_ISO_INT_EN, 0x318)
 356    FIELD(REQ_ISO_INT_EN, FP_LOCKED, 1, 4)
 357    FIELD(REQ_ISO_INT_EN, PL, 1, 1)
 358    FIELD(REQ_ISO_INT_EN, FP, 1, 0)
 359REG32(REQ_ISO_INT_DIS, 0x31c)
 360    FIELD(REQ_ISO_INT_DIS, FP_LOCKED, 1, 4)
 361    FIELD(REQ_ISO_INT_DIS, PL, 1, 1)
 362    FIELD(REQ_ISO_INT_DIS, FP, 1, 0)
 363REG32(REQ_ISO_TRIG, 0x320)
 364    FIELD(REQ_ISO_TRIG, FP_LOCKED, 1, 4)
 365    FIELD(REQ_ISO_TRIG, PL, 1, 1)
 366    FIELD(REQ_ISO_TRIG, FP, 1, 0)
 367REG32(REQ_SWRST_STATUS, 0x410)
 368    FIELD(REQ_SWRST_STATUS, PL, 1, 31)
 369    FIELD(REQ_SWRST_STATUS, FP, 1, 30)
 370    FIELD(REQ_SWRST_STATUS, LP, 1, 29)
 371    FIELD(REQ_SWRST_STATUS, PS_ONLY, 1, 28)
 372    FIELD(REQ_SWRST_STATUS, IOU, 1, 27)
 373    FIELD(REQ_SWRST_STATUS, USB1, 1, 25)
 374    FIELD(REQ_SWRST_STATUS, USB0, 1, 24)
 375    FIELD(REQ_SWRST_STATUS, GEM3, 1, 23)
 376    FIELD(REQ_SWRST_STATUS, GEM2, 1, 22)
 377    FIELD(REQ_SWRST_STATUS, GEM1, 1, 21)
 378    FIELD(REQ_SWRST_STATUS, GEM0, 1, 20)
 379    FIELD(REQ_SWRST_STATUS, LS_R5, 1, 18)
 380    FIELD(REQ_SWRST_STATUS, R5_1, 1, 17)
 381    FIELD(REQ_SWRST_STATUS, R5_0, 1, 16)
 382    FIELD(REQ_SWRST_STATUS, DISPLAY_PORT, 1, 12)
 383    FIELD(REQ_SWRST_STATUS, SATA, 1, 10)
 384    FIELD(REQ_SWRST_STATUS, PCIE, 1, 9)
 385    FIELD(REQ_SWRST_STATUS, GPU, 1, 8)
 386    FIELD(REQ_SWRST_STATUS, PP1, 1, 7)
 387    FIELD(REQ_SWRST_STATUS, PP0, 1, 6)
 388    FIELD(REQ_SWRST_STATUS, APU, 1, 4)
 389    FIELD(REQ_SWRST_STATUS, ACPU3, 1, 3)
 390    FIELD(REQ_SWRST_STATUS, ACPU2, 1, 2)
 391    FIELD(REQ_SWRST_STATUS, ACPU1, 1, 1)
 392    FIELD(REQ_SWRST_STATUS, ACPU0, 1, 0)
 393REG32(REQ_SWRST_INT_MASK, 0x414)
 394    FIELD(REQ_SWRST_INT_MASK, PL, 1, 31)
 395    FIELD(REQ_SWRST_INT_MASK, FP, 1, 30)
 396    FIELD(REQ_SWRST_INT_MASK, LP, 1, 29)
 397    FIELD(REQ_SWRST_INT_MASK, PS_ONLY, 1, 28)
 398    FIELD(REQ_SWRST_INT_MASK, IOU, 1, 27)
 399    FIELD(REQ_SWRST_INT_MASK, USB1, 1, 25)
 400    FIELD(REQ_SWRST_INT_MASK, USB0, 1, 24)
 401    FIELD(REQ_SWRST_INT_MASK, GEM3, 1, 23)
 402    FIELD(REQ_SWRST_INT_MASK, GEM2, 1, 22)
 403    FIELD(REQ_SWRST_INT_MASK, GEM1, 1, 21)
 404    FIELD(REQ_SWRST_INT_MASK, GEM0, 1, 20)
 405    FIELD(REQ_SWRST_INT_MASK, LS_R5, 1, 18)
 406    FIELD(REQ_SWRST_INT_MASK, R5_1, 1, 17)
 407    FIELD(REQ_SWRST_INT_MASK, R5_0, 1, 16)
 408    FIELD(REQ_SWRST_INT_MASK, DISPLAY_PORT, 1, 12)
 409    FIELD(REQ_SWRST_INT_MASK, SATA, 1, 10)
 410    FIELD(REQ_SWRST_INT_MASK, PCIE, 1, 9)
 411    FIELD(REQ_SWRST_INT_MASK, GPU, 1, 8)
 412    FIELD(REQ_SWRST_INT_MASK, PP1, 1, 7)
 413    FIELD(REQ_SWRST_INT_MASK, PP0, 1, 6)
 414    FIELD(REQ_SWRST_INT_MASK, APU, 1, 4)
 415    FIELD(REQ_SWRST_INT_MASK, ACPU3, 1, 3)
 416    FIELD(REQ_SWRST_INT_MASK, ACPU2, 1, 2)
 417    FIELD(REQ_SWRST_INT_MASK, ACPU1, 1, 1)
 418    FIELD(REQ_SWRST_INT_MASK, ACPU0, 1, 0)
 419REG32(REQ_SWRST_INT_EN, 0x418)
 420    FIELD(REQ_SWRST_INT_EN, PL, 1, 31)
 421    FIELD(REQ_SWRST_INT_EN, FP, 1, 30)
 422    FIELD(REQ_SWRST_INT_EN, LP, 1, 29)
 423    FIELD(REQ_SWRST_INT_EN, PS_ONLY, 1, 28)
 424    FIELD(REQ_SWRST_INT_EN, IOU, 1, 27)
 425    FIELD(REQ_SWRST_INT_EN, USB1, 1, 25)
 426    FIELD(REQ_SWRST_INT_EN, USB0, 1, 24)
 427    FIELD(REQ_SWRST_INT_EN, GEM3, 1, 23)
 428    FIELD(REQ_SWRST_INT_EN, GEM2, 1, 22)
 429    FIELD(REQ_SWRST_INT_EN, GEM1, 1, 21)
 430    FIELD(REQ_SWRST_INT_EN, GEM0, 1, 20)
 431    FIELD(REQ_SWRST_INT_EN, LS_R5, 1, 18)
 432    FIELD(REQ_SWRST_INT_EN, R5_1, 1, 17)
 433    FIELD(REQ_SWRST_INT_EN, R5_0, 1, 16)
 434    FIELD(REQ_SWRST_INT_EN, DISPLAY_PORT, 1, 12)
 435    FIELD(REQ_SWRST_INT_EN, SATA, 1, 10)
 436    FIELD(REQ_SWRST_INT_EN, PCIE, 1, 9)
 437    FIELD(REQ_SWRST_INT_EN, GPU, 1, 8)
 438    FIELD(REQ_SWRST_INT_EN, PP1, 1, 7)
 439    FIELD(REQ_SWRST_INT_EN, PP0, 1, 6)
 440    FIELD(REQ_SWRST_INT_EN, APU, 1, 4)
 441    FIELD(REQ_SWRST_INT_EN, ACPU3, 1, 3)
 442    FIELD(REQ_SWRST_INT_EN, ACPU2, 1, 2)
 443    FIELD(REQ_SWRST_INT_EN, ACPU1, 1, 1)
 444    FIELD(REQ_SWRST_INT_EN, ACPU0, 1, 0)
 445REG32(REQ_SWRST_INT_DIS, 0x41c)
 446    FIELD(REQ_SWRST_INT_DIS, PL, 1, 31)
 447    FIELD(REQ_SWRST_INT_DIS, FP, 1, 30)
 448    FIELD(REQ_SWRST_INT_DIS, LP, 1, 29)
 449    FIELD(REQ_SWRST_INT_DIS, PS_ONLY, 1, 28)
 450    FIELD(REQ_SWRST_INT_DIS, IOU, 1, 27)
 451    FIELD(REQ_SWRST_INT_DIS, USB1, 1, 25)
 452    FIELD(REQ_SWRST_INT_DIS, USB0, 1, 24)
 453    FIELD(REQ_SWRST_INT_DIS, GEM3, 1, 23)
 454    FIELD(REQ_SWRST_INT_DIS, GEM2, 1, 22)
 455    FIELD(REQ_SWRST_INT_DIS, GEM1, 1, 21)
 456    FIELD(REQ_SWRST_INT_DIS, GEM0, 1, 20)
 457    FIELD(REQ_SWRST_INT_DIS, LS_R5, 1, 18)
 458    FIELD(REQ_SWRST_INT_DIS, R5_1, 1, 17)
 459    FIELD(REQ_SWRST_INT_DIS, R5_0, 1, 16)
 460    FIELD(REQ_SWRST_INT_DIS, DISPLAY_PORT, 1, 12)
 461    FIELD(REQ_SWRST_INT_DIS, SATA, 1, 10)
 462    FIELD(REQ_SWRST_INT_DIS, PCIE, 1, 9)
 463    FIELD(REQ_SWRST_INT_DIS, GPU, 1, 8)
 464    FIELD(REQ_SWRST_INT_DIS, PP1, 1, 7)
 465    FIELD(REQ_SWRST_INT_DIS, PP0, 1, 6)
 466    FIELD(REQ_SWRST_INT_DIS, APU, 1, 4)
 467    FIELD(REQ_SWRST_INT_DIS, ACPU3, 1, 3)
 468    FIELD(REQ_SWRST_INT_DIS, ACPU2, 1, 2)
 469    FIELD(REQ_SWRST_INT_DIS, ACPU1, 1, 1)
 470    FIELD(REQ_SWRST_INT_DIS, ACPU0, 1, 0)
 471REG32(REQ_SWRST_TRIG, 0x420)
 472    FIELD(REQ_SWRST_TRIG, PL, 1, 31)
 473    FIELD(REQ_SWRST_TRIG, FP, 1, 30)
 474    FIELD(REQ_SWRST_TRIG, LP, 1, 29)
 475    FIELD(REQ_SWRST_TRIG, PS_ONLY, 1, 28)
 476    FIELD(REQ_SWRST_TRIG, IOU, 1, 27)
 477    FIELD(REQ_SWRST_TRIG, USB1, 1, 25)
 478    FIELD(REQ_SWRST_TRIG, USB0, 1, 24)
 479    FIELD(REQ_SWRST_TRIG, GEM3, 1, 23)
 480    FIELD(REQ_SWRST_TRIG, GEM2, 1, 22)
 481    FIELD(REQ_SWRST_TRIG, GEM1, 1, 21)
 482    FIELD(REQ_SWRST_TRIG, GEM0, 1, 20)
 483    FIELD(REQ_SWRST_TRIG, LS_R5, 1, 18)
 484    FIELD(REQ_SWRST_TRIG, R5_1, 1, 17)
 485    FIELD(REQ_SWRST_TRIG, R5_0, 1, 16)
 486    FIELD(REQ_SWRST_TRIG, DISPLAY_PORT, 1, 12)
 487    FIELD(REQ_SWRST_TRIG, SATA, 1, 10)
 488    FIELD(REQ_SWRST_TRIG, PCIE, 1, 9)
 489    FIELD(REQ_SWRST_TRIG, GPU, 1, 8)
 490    FIELD(REQ_SWRST_TRIG, PP1, 1, 7)
 491    FIELD(REQ_SWRST_TRIG, PP0, 1, 6)
 492    FIELD(REQ_SWRST_TRIG, APU, 1, 4)
 493    FIELD(REQ_SWRST_TRIG, ACPU3, 1, 3)
 494    FIELD(REQ_SWRST_TRIG, ACPU2, 1, 2)
 495    FIELD(REQ_SWRST_TRIG, ACPU1, 1, 1)
 496    FIELD(REQ_SWRST_TRIG, ACPU0, 1, 0)
 497REG32(REQ_AUX_STATUS, 0x510)
 498    FIELD(REQ_AUX_STATUS, SERV_REQ_10, 1, 17)
 499    FIELD(REQ_AUX_STATUS, SERV_REQ_9, 1, 16)
 500    FIELD(REQ_AUX_STATUS, SERV_REQ_8, 1, 13)
 501    FIELD(REQ_AUX_STATUS, SERV_REQ_7, 1, 12)
 502    FIELD(REQ_AUX_STATUS, SERV_REQ_6, 1, 10)
 503    FIELD(REQ_AUX_STATUS, SERV_REQ_5, 1, 7)
 504    FIELD(REQ_AUX_STATUS, SERV_REQ_4, 1, 6)
 505    FIELD(REQ_AUX_STATUS, SERV_REQ_3, 1, 3)
 506    FIELD(REQ_AUX_STATUS, SERV_REQ_2, 1, 2)
 507    FIELD(REQ_AUX_STATUS, SERV_REQ_1, 1, 1)
 508    FIELD(REQ_AUX_STATUS, SERV_REQ_0, 1, 0)
 509REG32(REQ_AUX_INT_MASK, 0x514)
 510    FIELD(REQ_AUX_MASK, SERV_REQ_10, 1, 17)
 511    FIELD(REQ_AUX_MASK, SERV_REQ_9, 1, 16)
 512    FIELD(REQ_AUX_MASK, SERV_REQ_8, 1, 13)
 513    FIELD(REQ_AUX_MASK, SERV_REQ_7, 1, 12)
 514    FIELD(REQ_AUX_MASK, SERV_REQ_6, 1, 10)
 515    FIELD(REQ_AUX_MASK, SERV_REQ_5, 1, 7)
 516    FIELD(REQ_AUX_MASK, SERV_REQ_4, 1, 6)
 517    FIELD(REQ_AUX_MASK, SERV_REQ_3, 1, 3)
 518    FIELD(REQ_AUX_MASK, SERV_REQ_2, 1, 2)
 519    FIELD(REQ_AUX_MASK, SERV_REQ_1, 1, 1)
 520    FIELD(REQ_AUX_MASK, SERV_REQ_0, 1, 0)
 521REG32(REQ_AUX_INT_EN, 0x518)
 522    FIELD(REQ_AUX_INT_EN, SERV_REQ_10, 1, 17)
 523    FIELD(REQ_AUX_INT_EN, SERV_REQ_9, 1, 16)
 524    FIELD(REQ_AUX_INT_EN, SERV_REQ_8, 1, 13)
 525    FIELD(REQ_AUX_INT_EN, SERV_REQ_7, 1, 12)
 526    FIELD(REQ_AUX_INT_EN, SERV_REQ_6, 1, 10)
 527    FIELD(REQ_AUX_INT_EN, SERV_REQ_5, 1, 7)
 528    FIELD(REQ_AUX_INT_EN, SERV_REQ_4, 1, 6)
 529    FIELD(REQ_AUX_INT_EN, SERV_REQ_3, 1, 3)
 530    FIELD(REQ_AUX_INT_EN, SERV_REQ_2, 1, 2)
 531    FIELD(REQ_AUX_INT_EN, SERV_REQ_1, 1, 1)
 532    FIELD(REQ_AUX_INT_EN, SERV_REQ_0, 1, 0)
 533REG32(REQ_AUX_INT_DIS, 0x51c)
 534    FIELD(REQ_AUX_INT_DIS, SERV_REQ_10, 1, 17)
 535    FIELD(REQ_AUX_INT_DIS, SERV_REQ_9, 1, 16)
 536    FIELD(REQ_AUX_INT_DIS, SERV_REQ_8, 1, 13)
 537    FIELD(REQ_AUX_INT_DIS, SERV_REQ_7, 1, 12)
 538    FIELD(REQ_AUX_INT_DIS, SERV_REQ_6, 1, 10)
 539    FIELD(REQ_AUX_INT_DIS, SERV_REQ_5, 1, 7)
 540    FIELD(REQ_AUX_INT_DIS, SERV_REQ_4, 1, 6)
 541    FIELD(REQ_AUX_INT_DIS, SERV_REQ_3, 1, 3)
 542    FIELD(REQ_AUX_INT_DIS, SERV_REQ_2, 1, 2)
 543    FIELD(REQ_AUX_INT_DIS, SERV_REQ_1, 1, 1)
 544    FIELD(REQ_AUX_INT_DIS, SERV_REQ_0, 1, 0)
 545REG32(REQ_AUX_TRIG, 0x520)
 546    FIELD(REQ_AUX_TRIG, SERV_REQ_10, 1, 17)
 547    FIELD(REQ_AUX_TRIG, SERV_REQ_9, 1, 16)
 548    FIELD(REQ_AUX_TRIG, SERV_REQ_8, 1, 13)
 549    FIELD(REQ_AUX_TRIG, SERV_REQ_7, 1, 12)
 550    FIELD(REQ_AUX_TRIG, SERV_REQ_6, 1, 10)
 551    FIELD(REQ_AUX_TRIG, SERV_REQ_5, 1, 7)
 552    FIELD(REQ_AUX_TRIG, SERV_REQ_4, 1, 6)
 553    FIELD(REQ_AUX_TRIG, SERV_REQ_3, 1, 3)
 554    FIELD(REQ_AUX_TRIG, SERV_REQ_2, 1, 2)
 555    FIELD(REQ_AUX_TRIG, SERV_REQ_1, 1, 1)
 556    FIELD(REQ_AUX_TRIG, SERV_REQ_0, 1, 0)
 557REG32(LOGCLR_STATUS, 0x524)
 558    FIELD(LOGCLR_STATUS, FP, 1, 17)
 559    FIELD(LOGCLR_STATUS, LP, 1, 16)
 560    FIELD(LOGCLR_STATUS, USB1, 1, 13)
 561    FIELD(LOGCLR_STATUS, USB0, 1, 12)
 562    FIELD(LOGCLR_STATUS, RPU, 1, 10)
 563    FIELD(LOGCLR_STATUS, PP1, 1, 7)
 564    FIELD(LOGCLR_STATUS, PP0, 1, 6)
 565    FIELD(LOGCLR_STATUS, ACPU3, 1, 3)
 566    FIELD(LOGCLR_STATUS, ACPU2, 1, 2)
 567    FIELD(LOGCLR_STATUS, ACPU1, 1, 1)
 568    FIELD(LOGCLR_STATUS, ACPU0, 1, 0)
 569REG32(CSU_BR_ERROR, 0x528)
 570    FIELD(CSU_BR_ERROR, BR_ERROR, 1, 31)
 571    FIELD(CSU_BR_ERROR, ERR_TYPE, 16, 0)
 572REG32(MB_FAULT_STATUS, 0x52c)
 573    FIELD(MB_FAULT_STATUS, R_FFAIL, 8, 24)
 574    FIELD(MB_FAULT_STATUS, R_SLEEP_RST, 1, 19)
 575    FIELD(MB_FAULT_STATUS, R_LSFAIL, 3, 16)
 576    FIELD(MB_FAULT_STATUS, N_FFAIL, 8, 8)
 577    FIELD(MB_FAULT_STATUS, N_SLEEP_RST, 1, 3)
 578    FIELD(MB_FAULT_STATUS, N_LSFAIL, 3, 0)
 579REG32(ERROR_STATUS_1, 0x530)
 580    FIELD(ERROR_STATUS_1, AUX3, 1, 31)
 581    FIELD(ERROR_STATUS_1, AUX2, 1, 30)
 582    FIELD(ERROR_STATUS_1, AUX1, 1, 29)
 583    FIELD(ERROR_STATUS_1, AUX0, 1, 28)
 584    FIELD(ERROR_STATUS_1, DFT, 1, 27)
 585    FIELD(ERROR_STATUS_1, CLK_MON, 1, 26)
 586    FIELD(ERROR_STATUS_1, XMPU, 2, 24)
 587    FIELD(ERROR_STATUS_1, PWR_SUPPLY, 8, 16)
 588    FIELD(ERROR_STATUS_1, FPD_SWDT, 1, 13)
 589    FIELD(ERROR_STATUS_1, LPD_SWDT, 1, 12)
 590    FIELD(ERROR_STATUS_1, RPU_CCF, 1, 9)
 591    FIELD(ERROR_STATUS_1, RPU_LS, 2, 6)
 592    FIELD(ERROR_STATUS_1, FPD_TEMP, 1, 5)
 593    FIELD(ERROR_STATUS_1, LPD_TEMP, 1, 4)
 594    FIELD(ERROR_STATUS_1, RPU1, 1, 3)
 595    FIELD(ERROR_STATUS_1, RPU0, 1, 2)
 596    FIELD(ERROR_STATUS_1, OCM_ECC, 1, 1)
 597    FIELD(ERROR_STATUS_1, DDR_ECC, 1, 0)
 598REG32(ERROR_INT_MASK_1, 0x534)
 599    FIELD(ERROR_INT_MASK_1, AUX3, 1, 31)
 600    FIELD(ERROR_INT_MASK_1, AUX2, 1, 30)
 601    FIELD(ERROR_INT_MASK_1, AUX1, 1, 29)
 602    FIELD(ERROR_INT_MASK_1, AUX0, 1, 28)
 603    FIELD(ERROR_INT_MASK_1, DFT, 1, 27)
 604    FIELD(ERROR_INT_MASK_1, CLK_MON, 1, 26)
 605    FIELD(ERROR_INT_MASK_1, XMPU, 2, 24)
 606    FIELD(ERROR_INT_MASK_1, PWR_SUPPLY, 8, 16)
 607    FIELD(ERROR_INT_MASK_1, FPD_SWDT, 1, 13)
 608    FIELD(ERROR_INT_MASK_1, LPD_SWDT, 1, 12)
 609    FIELD(ERROR_INT_MASK_1, RPU_CCF, 1, 9)
 610    FIELD(ERROR_INT_MASK_1, RPU_LS, 2, 6)
 611    FIELD(ERROR_INT_MASK_1, FPD_TEMP, 1, 5)
 612    FIELD(ERROR_INT_MASK_1, LPD_TEMP, 1, 4)
 613    FIELD(ERROR_INT_MASK_1, RPU1, 1, 3)
 614    FIELD(ERROR_INT_MASK_1, RPU0, 1, 2)
 615    FIELD(ERROR_INT_MASK_1, OCM_ECC, 1, 1)
 616    FIELD(ERROR_INT_MASK_1, DDR_ECC, 1, 0)
 617REG32(ERROR_INT_EN_1, 0x538)
 618    FIELD(ERROR_INT_EN_1, AUX3, 1, 31)
 619    FIELD(ERROR_INT_EN_1, AUX2, 1, 30)
 620    FIELD(ERROR_INT_EN_1, AUX1, 1, 29)
 621    FIELD(ERROR_INT_EN_1, AUX0, 1, 28)
 622    FIELD(ERROR_INT_EN_1, DFT, 1, 27)
 623    FIELD(ERROR_INT_EN_1, CLK_MON, 1, 26)
 624    FIELD(ERROR_INT_EN_1, XMPU, 2, 24)
 625    FIELD(ERROR_INT_EN_1, PWR_SUPPLY, 8, 16)
 626    FIELD(ERROR_INT_EN_1, FPD_SWDT, 1, 13)
 627    FIELD(ERROR_INT_EN_1, LPD_SWDT, 1, 12)
 628    FIELD(ERROR_INT_EN_1, RPU_CCF, 1, 9)
 629    FIELD(ERROR_INT_EN_1, RPU_LS, 2, 6)
 630    FIELD(ERROR_INT_EN_1, FPD_TEMP, 1, 5)
 631    FIELD(ERROR_INT_EN_1, LPD_TEMP, 1, 4)
 632    FIELD(ERROR_INT_EN_1, RPU1, 1, 3)
 633    FIELD(ERROR_INT_EN_1, RPU0, 1, 2)
 634    FIELD(ERROR_INT_EN_1, OCM_ECC, 1, 1)
 635    FIELD(ERROR_INT_EN_1, DDR_ECC, 1, 0)
 636REG32(ERROR_INT_DIS_1, 0x53c)
 637    FIELD(ERROR_INT_DIS_1, AUX3, 1, 31)
 638    FIELD(ERROR_INT_DIS_1, AUX2, 1, 30)
 639    FIELD(ERROR_INT_DIS_1, AUX1, 1, 29)
 640    FIELD(ERROR_INT_DIS_1, AUX0, 1, 28)
 641    FIELD(ERROR_INT_DIS_1, DFT, 1, 27)
 642    FIELD(ERROR_INT_DIS_1, CLK_MON, 1, 26)
 643    FIELD(ERROR_INT_DIS_1, XMPU, 2, 24)
 644    FIELD(ERROR_INT_DIS_1, PWR_SUPPLY, 8, 16)
 645    FIELD(ERROR_INT_DIS_1, FPD_SWDT, 1, 13)
 646    FIELD(ERROR_INT_DIS_1, LPD_SWDT, 1, 12)
 647    FIELD(ERROR_INT_DIS_1, RPU_CCF, 1, 9)
 648    FIELD(ERROR_INT_DIS_1, RPU_LS, 2, 6)
 649    FIELD(ERROR_INT_DIS_1, FPD_TEMP, 1, 5)
 650    FIELD(ERROR_INT_DIS_1, LPD_TEMP, 1, 4)
 651    FIELD(ERROR_INT_DIS_1, RPU1, 1, 3)
 652    FIELD(ERROR_INT_DIS_1, RPU0, 1, 2)
 653    FIELD(ERROR_INT_DIS_1, OCM_ECC, 1, 1)
 654    FIELD(ERROR_INT_DIS_1, DDR_ECC, 1, 0)
 655REG32(ERROR_STATUS_2, 0x540)
 656    FIELD(ERROR_STATUS_2, CSU_ROM, 1, 26)
 657    FIELD(ERROR_STATUS_2, PMU_PB, 1, 25)
 658    FIELD(ERROR_STATUS_2, PMU_SERVICE, 1, 24)
 659    FIELD(ERROR_STATUS_2, PMU_FW, 4, 18)
 660    FIELD(ERROR_STATUS_2, PMU_UC, 1, 17)
 661    FIELD(ERROR_STATUS_2, CSU, 1, 16)
 662    FIELD(ERROR_STATUS_2, PLL_LOCK, 5, 8)
 663    FIELD(ERROR_STATUS_2, PL, 4, 2)
 664    FIELD(ERROR_STATUS_2, TO, 2, 0)
 665REG32(ERROR_INT_MASK_2, 0x544)
 666    FIELD(ERROR_INT_MASK_2, CSU_ROM, 1, 26)
 667    FIELD(ERROR_INT_MASK_2, PMU_PB, 1, 25)
 668    FIELD(ERROR_INT_MASK_2, PMU_SERVICE, 1, 24)
 669    FIELD(ERROR_INT_MASK_2, PMU_FW, 4, 18)
 670    FIELD(ERROR_INT_MASK_2, PMU_UC, 1, 17)
 671    FIELD(ERROR_INT_MASK_2, CSU, 1, 16)
 672    FIELD(ERROR_INT_MASK_2, PLL_LOCK, 5, 8)
 673    FIELD(ERROR_INT_MASK_2, PL, 4, 2)
 674    FIELD(ERROR_INT_MASK_2, TO, 2, 0)
 675REG32(ERROR_INT_EN_2, 0x548)
 676    FIELD(ERROR_INT_EN_2, CSU_ROM, 1, 26)
 677    FIELD(ERROR_INT_EN_2, PMU_PB, 1, 25)
 678    FIELD(ERROR_INT_EN_2, PMU_SERVICE, 1, 24)
 679    FIELD(ERROR_INT_EN_2, PMU_FW, 4, 18)
 680    FIELD(ERROR_INT_EN_2, PMU_UC, 1, 17)
 681    FIELD(ERROR_INT_EN_2, CSU, 1, 16)
 682    FIELD(ERROR_INT_EN_2, PLL_LOCK, 5, 8)
 683    FIELD(ERROR_INT_EN_2, PL, 4, 2)
 684    FIELD(ERROR_INT_EN_2, TO, 2, 0)
 685REG32(ERROR_INT_DIS_2, 0x54c)
 686    FIELD(ERROR_INT_DIS_2, CSU_ROM, 1, 26)
 687    FIELD(ERROR_INT_DIS_2, PMU_PB, 1, 25)
 688    FIELD(ERROR_INT_DIS_2, PMU_SERVICE, 1, 24)
 689    FIELD(ERROR_INT_DIS_2, PMU_FW, 4, 18)
 690    FIELD(ERROR_INT_DIS_2, PMU_UC, 1, 17)
 691    FIELD(ERROR_INT_DIS_2, CSU, 1, 16)
 692    FIELD(ERROR_INT_DIS_2, PLL_LOCK, 5, 8)
 693    FIELD(ERROR_INT_DIS_2, PL, 4, 2)
 694    FIELD(ERROR_INT_DIS_2, TO, 2, 0)
 695REG32(ERROR_POR_MASK_1, 0x550)
 696    FIELD(ERROR_POR_MASK_1, AUX3, 1, 31)
 697    FIELD(ERROR_POR_MASK_1, AUX2, 1, 30)
 698    FIELD(ERROR_POR_MASK_1, AUX1, 1, 29)
 699    FIELD(ERROR_POR_MASK_1, AUX0, 1, 28)
 700    FIELD(ERROR_POR_MASK_1, DFT, 1, 27)
 701    FIELD(ERROR_POR_MASK_1, CLK_MON, 1, 26)
 702    FIELD(ERROR_POR_MASK_1, XMPU, 2, 24)
 703    FIELD(ERROR_POR_MASK_1, PWR_SUPPLY, 8, 16)
 704    FIELD(ERROR_POR_MASK_1, FPD_SWDT, 1, 13)
 705    FIELD(ERROR_POR_MASK_1, LPD_SWDT, 1, 12)
 706    FIELD(ERROR_POR_MASK_1, RPU_CCF, 1, 9)
 707    FIELD(ERROR_POR_MASK_1, RPU_LS, 2, 6)
 708    FIELD(ERROR_POR_MASK_1, FPD_TEMP, 1, 5)
 709    FIELD(ERROR_POR_MASK_1, LPD_TEMP, 1, 4)
 710    FIELD(ERROR_POR_MASK_1, RPU1, 1, 3)
 711    FIELD(ERROR_POR_MASK_1, RPU0, 1, 2)
 712    FIELD(ERROR_POR_MASK_1, OCM_ECC, 1, 1)
 713    FIELD(ERROR_POR_MASK_1, DDR_ECC, 1, 0)
 714REG32(ERROR_POR_EN_1, 0x554)
 715    FIELD(ERROR_POR_EN_1, AUX3, 1, 31)
 716    FIELD(ERROR_POR_EN_1, AUX2, 1, 30)
 717    FIELD(ERROR_POR_EN_1, AUX1, 1, 29)
 718    FIELD(ERROR_POR_EN_1, AUX0, 1, 28)
 719    FIELD(ERROR_POR_EN_1, DFT, 1, 27)
 720    FIELD(ERROR_POR_EN_1, CLK_MON, 1, 26)
 721    FIELD(ERROR_POR_EN_1, XMPU, 2, 24)
 722    FIELD(ERROR_POR_EN_1, PWR_SUPPLY, 8, 16)
 723    FIELD(ERROR_POR_EN_1, FPD_SWDT, 1, 13)
 724    FIELD(ERROR_POR_EN_1, LPD_SWDT, 1, 12)
 725    FIELD(ERROR_POR_EN_1, RPU_CCF, 1, 9)
 726    FIELD(ERROR_POR_EN_1, RPU_LS, 2, 6)
 727    FIELD(ERROR_POR_EN_1, FPD_TEMP, 1, 5)
 728    FIELD(ERROR_POR_EN_1, LPD_TEMP, 1, 4)
 729    FIELD(ERROR_POR_EN_1, RPU1, 1, 3)
 730    FIELD(ERROR_POR_EN_1, RPU0, 1, 2)
 731    FIELD(ERROR_POR_EN_1, OCM_ECC, 1, 1)
 732    FIELD(ERROR_POR_EN_1, DDR_ECC, 1, 0)
 733REG32(ERROR_POR_DIS_1, 0x558)
 734    FIELD(ERROR_POR_DIS_1, AUX3, 1, 31)
 735    FIELD(ERROR_POR_DIS_1, AUX2, 1, 30)
 736    FIELD(ERROR_POR_DIS_1, AUX1, 1, 29)
 737    FIELD(ERROR_POR_DIS_1, AUX0, 1, 28)
 738    FIELD(ERROR_POR_DIS_1, DFT, 1, 27)
 739    FIELD(ERROR_POR_DIS_1, CLK_MON, 1, 26)
 740    FIELD(ERROR_POR_DIS_1, XMPU, 2, 24)
 741    FIELD(ERROR_POR_DIS_1, PWR_SUPPLY, 8, 16)
 742    FIELD(ERROR_POR_DIS_1, FPD_SWDT, 1, 13)
 743    FIELD(ERROR_POR_DIS_1, LPD_SWDT, 1, 12)
 744    FIELD(ERROR_POR_DIS_1, RPU_CCF, 1, 9)
 745    FIELD(ERROR_POR_DIS_1, RPU_LS, 2, 6)
 746    FIELD(ERROR_POR_DIS_1, FPD_TEMP, 1, 5)
 747    FIELD(ERROR_POR_DIS_1, LPD_TEMP, 1, 4)
 748    FIELD(ERROR_POR_DIS_1, RPU1, 1, 3)
 749    FIELD(ERROR_POR_DIS_1, RPU0, 1, 2)
 750    FIELD(ERROR_POR_DIS_1, OCM_ECC, 1, 1)
 751    FIELD(ERROR_POR_DIS_1, DDR_ECC, 1, 0)
 752REG32(ERROR_POR_MASK_2, 0x55c)
 753    FIELD(ERROR_POR_MASK_2, CSU_ROM, 1, 26)
 754    FIELD(ERROR_POR_MASK_2, PMU_PB, 1, 25)
 755    FIELD(ERROR_POR_MASK_2, PMU_SERVICE, 1, 24)
 756    FIELD(ERROR_POR_MASK_2, PMU_FW, 4, 18)
 757    FIELD(ERROR_POR_MASK_2, PMU_UC, 1, 17)
 758    FIELD(ERROR_POR_MASK_2, CSU, 1, 16)
 759    FIELD(ERROR_POR_MASK_2, PLL_LOCK, 5, 8)
 760    FIELD(ERROR_POR_MASK_2, PL, 4, 2)
 761    FIELD(ERROR_POR_MASK_2, TO, 2, 0)
 762REG32(ERROR_POR_EN_2, 0x560)
 763    FIELD(ERROR_POR_EN_2, CSU_ROM, 1, 26)
 764    FIELD(ERROR_POR_EN_2, PMU_PB, 1, 25)
 765    FIELD(ERROR_POR_EN_2, PMU_SERVICE, 1, 24)
 766    FIELD(ERROR_POR_EN_2, PMU_FW, 4, 18)
 767    FIELD(ERROR_POR_EN_2, PMU_UC, 1, 17)
 768    FIELD(ERROR_POR_EN_2, CSU, 1, 16)
 769    FIELD(ERROR_POR_EN_2, PLL_LOCK, 5, 8)
 770    FIELD(ERROR_POR_EN_2, PL, 4, 2)
 771    FIELD(ERROR_POR_EN_2, TO, 2, 0)
 772REG32(ERROR_POR_DIS_2, 0x564)
 773    FIELD(ERROR_POR_DIS_2, CSU_ROM, 1, 26)
 774    FIELD(ERROR_POR_DIS_2, PMU_PB, 1, 25)
 775    FIELD(ERROR_POR_DIS_2, PMU_SERVICE, 1, 24)
 776    FIELD(ERROR_POR_DIS_2, PMU_FW, 4, 18)
 777    FIELD(ERROR_POR_DIS_2, PMU_UC, 1, 17)
 778    FIELD(ERROR_POR_DIS_2, CSU, 1, 16)
 779    FIELD(ERROR_POR_DIS_2, PLL_LOCK, 5, 8)
 780    FIELD(ERROR_POR_DIS_2, PL, 4, 2)
 781    FIELD(ERROR_POR_DIS_2, TO, 2, 0)
 782REG32(ERROR_SRST_MASK_1, 0x568)
 783    FIELD(ERROR_SRST_MASK_1, AUX3, 1, 31)
 784    FIELD(ERROR_SRST_MASK_1, AUX2, 1, 30)
 785    FIELD(ERROR_SRST_MASK_1, AUX1, 1, 29)
 786    FIELD(ERROR_SRST_MASK_1, AUX0, 1, 28)
 787    FIELD(ERROR_SRST_MASK_1, DFT, 1, 27)
 788    FIELD(ERROR_SRST_MASK_1, CLK_MON, 1, 26)
 789    FIELD(ERROR_SRST_MASK_1, XMPU, 2, 24)
 790    FIELD(ERROR_SRST_MASK_1, PWR_SUPPLY, 8, 16)
 791    FIELD(ERROR_SRST_MASK_1, FPD_SWDT, 1, 13)
 792    FIELD(ERROR_SRST_MASK_1, LPD_SWDT, 1, 12)
 793    FIELD(ERROR_SRST_MASK_1, RPU_CCF, 1, 9)
 794    FIELD(ERROR_SRST_MASK_1, RPU_LS, 2, 6)
 795    FIELD(ERROR_SRST_MASK_1, FPD_TEMP, 1, 5)
 796    FIELD(ERROR_SRST_MASK_1, LPD_TEMP, 1, 4)
 797    FIELD(ERROR_SRST_MASK_1, RPU1, 1, 3)
 798    FIELD(ERROR_SRST_MASK_1, RPU0, 1, 2)
 799    FIELD(ERROR_SRST_MASK_1, OCM_ECC, 1, 1)
 800    FIELD(ERROR_SRST_MASK_1, DDR_ECC, 1, 0)
 801REG32(ERROR_SRST_EN_1, 0x56c)
 802    FIELD(ERROR_SRST_EN_1, AUX3, 1, 31)
 803    FIELD(ERROR_SRST_EN_1, AUX2, 1, 30)
 804    FIELD(ERROR_SRST_EN_1, AUX1, 1, 29)
 805    FIELD(ERROR_SRST_EN_1, AUX0, 1, 28)
 806    FIELD(ERROR_SRST_EN_1, DFT, 1, 27)
 807    FIELD(ERROR_SRST_EN_1, CLK_MON, 1, 26)
 808    FIELD(ERROR_SRST_EN_1, XMPU, 2, 24)
 809    FIELD(ERROR_SRST_EN_1, PWR_SUPPLY, 8, 16)
 810    FIELD(ERROR_SRST_EN_1, FPD_SWDT, 1, 13)
 811    FIELD(ERROR_SRST_EN_1, LPD_SWDT, 1, 12)
 812    FIELD(ERROR_SRST_EN_1, RPU_CCF, 1, 9)
 813    FIELD(ERROR_SRST_EN_1, RPU_LS, 2, 6)
 814    FIELD(ERROR_SRST_EN_1, FPD_TEMP, 1, 5)
 815    FIELD(ERROR_SRST_EN_1, LPD_TEMP, 1, 4)
 816    FIELD(ERROR_SRST_EN_1, RPU1, 1, 3)
 817    FIELD(ERROR_SRST_EN_1, RPU0, 1, 2)
 818    FIELD(ERROR_SRST_EN_1, OCM_ECC, 1, 1)
 819    FIELD(ERROR_SRST_EN_1, DDR_ECC, 1, 0)
 820REG32(ERROR_SRST_DIS_1, 0x570)
 821    FIELD(ERROR_SRST_DIS_1, AUX3, 1, 31)
 822    FIELD(ERROR_SRST_DIS_1, AUX2, 1, 30)
 823    FIELD(ERROR_SRST_DIS_1, AUX1, 1, 29)
 824    FIELD(ERROR_SRST_DIS_1, AUX0, 1, 28)
 825    FIELD(ERROR_SRST_DIS_1, DFT, 1, 27)
 826    FIELD(ERROR_SRST_DIS_1, CLK_MON, 1, 26)
 827    FIELD(ERROR_SRST_DIS_1, XMPU, 2, 24)
 828    FIELD(ERROR_SRST_DIS_1, PWR_SUPPLY, 8, 16)
 829    FIELD(ERROR_SRST_DIS_1, FPD_SWDT, 1, 13)
 830    FIELD(ERROR_SRST_DIS_1, LPD_SWDT, 1, 12)
 831    FIELD(ERROR_SRST_DIS_1, RPU_CCF, 1, 9)
 832    FIELD(ERROR_SRST_DIS_1, RPU_LS, 2, 6)
 833    FIELD(ERROR_SRST_DIS_1, FPD_TEMP, 1, 5)
 834    FIELD(ERROR_SRST_DIS_1, LPD_TEMP, 1, 4)
 835    FIELD(ERROR_SRST_DIS_1, RPU1, 1, 3)
 836    FIELD(ERROR_SRST_DIS_1, RPU0, 1, 2)
 837    FIELD(ERROR_SRST_DIS_1, OCM_ECC, 1, 1)
 838    FIELD(ERROR_SRST_DIS_1, DDR_ECC, 1, 0)
 839REG32(ERROR_SRST_MASK_2, 0x574)
 840    FIELD(ERROR_SRST_MASK_2, CSU_ROM, 1, 26)
 841    FIELD(ERROR_SRST_MASK_2, PMU_PB, 1, 25)
 842    FIELD(ERROR_SRST_MASK_2, PMU_SERVICE, 1, 24)
 843    FIELD(ERROR_SRST_MASK_2, PMU_FW, 4, 18)
 844    FIELD(ERROR_SRST_MASK_2, PMU_UC, 1, 17)
 845    FIELD(ERROR_SRST_MASK_2, CSU, 1, 16)
 846    FIELD(ERROR_SRST_MASK_2, PLL_LOCK, 5, 8)
 847    FIELD(ERROR_SRST_MASK_2, PL, 4, 2)
 848    FIELD(ERROR_SRST_MASK_2, TO, 2, 0)
 849REG32(ERROR_SRST_EN_2, 0x578)
 850    FIELD(ERROR_SRST_EN_2, CSU_ROM, 1, 26)
 851    FIELD(ERROR_SRST_EN_2, PMU_PB, 1, 25)
 852    FIELD(ERROR_SRST_EN_2, PMU_SERVICE, 1, 24)
 853    FIELD(ERROR_SRST_EN_2, PMU_FW, 4, 18)
 854    FIELD(ERROR_SRST_EN_2, PMU_UC, 1, 17)
 855    FIELD(ERROR_SRST_EN_2, CSU, 1, 16)
 856    FIELD(ERROR_SRST_EN_2, PLL_LOCK, 5, 8)
 857    FIELD(ERROR_SRST_EN_2, PL, 4, 2)
 858    FIELD(ERROR_SRST_EN_2, TO, 2, 0)
 859REG32(ERROR_SRST_DIS_2, 0x57c)
 860    FIELD(ERROR_SRST_DIS_2, CSU_ROM, 1, 26)
 861    FIELD(ERROR_SRST_DIS_2, PMU_PB, 1, 25)
 862    FIELD(ERROR_SRST_DIS_2, PMU_SERVICE, 1, 24)
 863    FIELD(ERROR_SRST_DIS_2, PMU_FW, 4, 18)
 864    FIELD(ERROR_SRST_DIS_2, PMU_UC, 1, 17)
 865    FIELD(ERROR_SRST_DIS_2, CSU, 1, 16)
 866    FIELD(ERROR_SRST_DIS_2, PLL_LOCK, 5, 8)
 867    FIELD(ERROR_SRST_DIS_2, PL, 4, 2)
 868    FIELD(ERROR_SRST_DIS_2, TO, 2, 0)
 869REG32(ERROR_SIG_MASK_1, 0x580)
 870    FIELD(ERROR_SIG_MASK_1, AUX3, 1, 31)
 871    FIELD(ERROR_SIG_MASK_1, AUX2, 1, 30)
 872    FIELD(ERROR_SIG_MASK_1, AUX1, 1, 29)
 873    FIELD(ERROR_SIG_MASK_1, AUX0, 1, 28)
 874    FIELD(ERROR_SIG_MASK_1, DFT, 1, 27)
 875    FIELD(ERROR_SIG_MASK_1, CLK_MON, 1, 26)
 876    FIELD(ERROR_SIG_MASK_1, XMPU, 2, 24)
 877    FIELD(ERROR_SIG_MASK_1, PWR_SUPPLY, 8, 16)
 878    FIELD(ERROR_SIG_MASK_1, FPD_SWDT, 1, 13)
 879    FIELD(ERROR_SIG_MASK_1, LPD_SWDT, 1, 12)
 880    FIELD(ERROR_SIG_MASK_1, RPU_CCF, 1, 9)
 881    FIELD(ERROR_SIG_MASK_1, RPU_LS, 2, 6)
 882    FIELD(ERROR_SIG_MASK_1, FPD_TEMP, 1, 5)
 883    FIELD(ERROR_SIG_MASK_1, LPD_TEMP, 1, 4)
 884    FIELD(ERROR_SIG_MASK_1, RPU1, 1, 3)
 885    FIELD(ERROR_SIG_MASK_1, RPU0, 1, 2)
 886    FIELD(ERROR_SIG_MASK_1, OCM_ECC, 1, 1)
 887    FIELD(ERROR_SIG_MASK_1, DDR_ECC, 1, 0)
 888REG32(ERROR_SIG_EN_1, 0x584)
 889    FIELD(ERROR_SIG_EN_1, AUX3, 1, 31)
 890    FIELD(ERROR_SIG_EN_1, AUX2, 1, 30)
 891    FIELD(ERROR_SIG_EN_1, AUX1, 1, 29)
 892    FIELD(ERROR_SIG_EN_1, AUX0, 1, 28)
 893    FIELD(ERROR_SIG_EN_1, DFT, 1, 27)
 894    FIELD(ERROR_SIG_EN_1, CLK_MON, 1, 26)
 895    FIELD(ERROR_SIG_EN_1, XMPU, 2, 24)
 896    FIELD(ERROR_SIG_EN_1, PWR_SUPPLY, 8, 16)
 897    FIELD(ERROR_SIG_EN_1, FPD_SWDT, 1, 13)
 898    FIELD(ERROR_SIG_EN_1, LPD_SWDT, 1, 12)
 899    FIELD(ERROR_SIG_EN_1, RPU_CCF, 1, 9)
 900    FIELD(ERROR_SIG_EN_1, RPU_LS, 2, 6)
 901    FIELD(ERROR_SIG_EN_1, FPD_TEMP, 1, 5)
 902    FIELD(ERROR_SIG_EN_1, LPD_TEMP, 1, 4)
 903    FIELD(ERROR_SIG_EN_1, RPU1, 1, 3)
 904    FIELD(ERROR_SIG_EN_1, RPU0, 1, 2)
 905    FIELD(ERROR_SIG_EN_1, OCM_ECC, 1, 1)
 906    FIELD(ERROR_SIG_EN_1, DDR_ECC, 1, 0)
 907REG32(ERROR_SIG_DIS_1, 0x588)
 908    FIELD(ERROR_SIG_DIS_1, AUX3, 1, 31)
 909    FIELD(ERROR_SIG_DIS_1, AUX2, 1, 30)
 910    FIELD(ERROR_SIG_DIS_1, AUX1, 1, 29)
 911    FIELD(ERROR_SIG_DIS_1, AUX0, 1, 28)
 912    FIELD(ERROR_SIG_DIS_1, DFT, 1, 27)
 913    FIELD(ERROR_SIG_DIS_1, CLK_MON, 1, 26)
 914    FIELD(ERROR_SIG_DIS_1, XMPU, 2, 24)
 915    FIELD(ERROR_SIG_DIS_1, PWR_SUPPLY, 8, 16)
 916    FIELD(ERROR_SIG_DIS_1, FPD_SWDT, 1, 13)
 917    FIELD(ERROR_SIG_DIS_1, LPD_SWDT, 1, 12)
 918    FIELD(ERROR_SIG_DIS_1, RPU_CCF, 1, 9)
 919    FIELD(ERROR_SIG_DIS_1, RPU_LS, 2, 6)
 920    FIELD(ERROR_SIG_DIS_1, FPD_TEMP, 1, 5)
 921    FIELD(ERROR_SIG_DIS_1, LPD_TEMP, 1, 4)
 922    FIELD(ERROR_SIG_DIS_1, RPU1, 1, 3)
 923    FIELD(ERROR_SIG_DIS_1, RPU0, 1, 2)
 924    FIELD(ERROR_SIG_DIS_1, OCM_ECC, 1, 1)
 925    FIELD(ERROR_SIG_DIS_1, DDR_ECC, 1, 0)
 926REG32(ERROR_SIG_MASK_2, 0x58c)
 927    FIELD(ERROR_SIG_MASK_2, CSU_ROM, 1, 26)
 928    FIELD(ERROR_SIG_MASK_2, PMU_PB, 1, 25)
 929    FIELD(ERROR_SIG_MASK_2, PMU_SERVICE, 1, 24)
 930    FIELD(ERROR_SIG_MASK_2, PMU_FW, 4, 18)
 931    FIELD(ERROR_SIG_MASK_2, PMU_UC, 1, 17)
 932    FIELD(ERROR_SIG_MASK_2, CSU, 1, 16)
 933    FIELD(ERROR_SIG_MASK_2, PLL_LOCK, 5, 8)
 934    FIELD(ERROR_SIG_MASK_2, PL, 4, 2)
 935    FIELD(ERROR_SIG_MASK_2, TO, 2, 0)
 936REG32(ERROR_SIG_EN_2, 0x590)
 937    FIELD(ERROR_SIG_EN_2, CSU_ROM, 1, 26)
 938    FIELD(ERROR_SIG_EN_2, PMU_PB, 1, 25)
 939    FIELD(ERROR_SIG_EN_2, PMU_SERVICE, 1, 24)
 940    FIELD(ERROR_SIG_EN_2, PMU_FW, 4, 18)
 941    FIELD(ERROR_SIG_EN_2, PMU_UC, 1, 17)
 942    FIELD(ERROR_SIG_EN_2, CSU, 1, 16)
 943    FIELD(ERROR_SIG_EN_2, PLL_LOCK, 5, 8)
 944    FIELD(ERROR_SIG_EN_2, PL, 4, 2)
 945    FIELD(ERROR_SIG_EN_2, TO, 2, 0)
 946REG32(ERROR_SIG_DIS_2, 0x594)
 947    FIELD(ERROR_SIG_DIS_2, CSU_ROM, 1, 26)
 948    FIELD(ERROR_SIG_DIS_2, PMU_PB, 1, 25)
 949    FIELD(ERROR_SIG_DIS_2, PMU_SERVICE, 1, 24)
 950    FIELD(ERROR_SIG_DIS_2, PMU_FW, 4, 18)
 951    FIELD(ERROR_SIG_DIS_2, PMU_UC, 1, 17)
 952    FIELD(ERROR_SIG_DIS_2, CSU, 1, 16)
 953    FIELD(ERROR_SIG_DIS_2, PLL_LOCK, 5, 8)
 954    FIELD(ERROR_SIG_DIS_2, PL, 4, 2)
 955    FIELD(ERROR_SIG_DIS_2, TO, 2, 0)
 956REG32(ERROR_EN_1, 0x5A0)
 957    FIELD(ERROR_EN_1, AUX3, 1, 31)
 958    FIELD(ERROR_EN_1, AUX2, 1, 30)
 959    FIELD(ERROR_EN_1, AUX1, 1, 29)
 960    FIELD(ERROR_EN_1, AUX0, 1, 28)
 961    FIELD(ERROR_EN_1, DFT, 1, 27)
 962    FIELD(ERROR_EN_1, CLK_MON, 1, 26)
 963    FIELD(ERROR_EN_1, XMPU, 2, 24)
 964    FIELD(ERROR_EN_1, PWR_SUPPLY, 8, 16)
 965    FIELD(ERROR_EN_1, FPD_SWDT, 1, 13)
 966    FIELD(ERROR_EN_1, LPD_SWDT, 1, 12)
 967    FIELD(ERROR_EN_1, RPU_CCF, 1, 9)
 968    FIELD(ERROR_EN_1, RPU_LS, 2, 6)
 969    FIELD(ERROR_EN_1, FPD_TEMP, 1, 5)
 970    FIELD(ERROR_EN_1, LPD_TEMP, 1, 4)
 971    FIELD(ERROR_EN_1, RPU1, 1, 3)
 972    FIELD(ERROR_EN_1, RPU0, 1, 2)
 973    FIELD(ERROR_EN_1, OCM_ECC, 1, 1)
 974    FIELD(ERROR_EN_1, DDR_ECC, 1, 0)
 975REG32(ERROR_EN_2, 0x5A4)
 976    FIELD(ERROR_EN_2, CSU_ROM, 1, 26)
 977    FIELD(ERROR_EN_2, PMU_PB, 1, 25)
 978    FIELD(ERROR_EN_2, PMU_SERVICE, 1, 24)
 979    FIELD(ERROR_EN_2, PMU_FW, 4, 18)
 980    FIELD(ERROR_EN_2, PMU_UC, 1, 17)
 981    FIELD(ERROR_EN_2, CSU, 1, 16)
 982    FIELD(ERROR_EN_2, PLL_LOCK, 5, 8)
 983    FIELD(ERROR_EN_2, PL, 4, 2)
 984    FIELD(ERROR_EN_2, TO, 2, 0)
 985REG32(AIB_CNTRL, 0x600)
 986    FIELD(AIB_CNTRL, FPD_AFI_FS, 1, 3)
 987    FIELD(AIB_CNTRL, FPD_AFI_FM, 1, 2)
 988    FIELD(AIB_CNTRL, LPDAFI_FS, 1, 1)
 989    FIELD(AIB_CNTRL, LPDAFI_FM, 1, 0)
 990REG32(AIB_STATUS, 0x604)
 991    FIELD(AIB_STATUS, FPD_AFI_FS, 1, 3)
 992    FIELD(AIB_STATUS, FPD_AFI_FM, 1, 2)
 993    FIELD(AIB_STATUS, LPDAFI_FS, 1, 1)
 994    FIELD(AIB_STATUS, LPDAFI_FM, 1, 0)
 995REG32(GLOBAL_RESET, 0x608)
 996    FIELD(GLOBAL_RESET, PS_ONLY_RST, 1, 10)
 997    FIELD(GLOBAL_RESET, FPD_RST, 1, 9)
 998    FIELD(GLOBAL_RESET, RPU_LS_RST, 1, 8)
 999REG32(ROM_VALIDATION_STATUS, 0x610)
1000    FIELD(ROM_VALIDATION_STATUS, PASS, 1, 1)
1001    FIELD(ROM_VALIDATION_STATUS, DONE, 1, 0)
1002REG32(ROM_VALIDATION_DIGEST_0, 0x614)
1003REG32(ROM_VALIDATION_DIGEST_1, 0x618)
1004REG32(ROM_VALIDATION_DIGEST_2, 0x61c)
1005REG32(ROM_VALIDATION_DIGEST_3, 0x620)
1006REG32(ROM_VALIDATION_DIGEST_4, 0x624)
1007REG32(ROM_VALIDATION_DIGEST_5, 0x628)
1008REG32(ROM_VALIDATION_DIGEST_6, 0x62c)
1009REG32(ROM_VALIDATION_DIGEST_7, 0x630)
1010REG32(ROM_VALIDATION_DIGEST_8, 0x634)
1011REG32(ROM_VALIDATION_DIGEST_9, 0x638)
1012REG32(ROM_VALIDATION_DIGEST_10, 0x63c)
1013REG32(ROM_VALIDATION_DIGEST_11, 0x640)
1014REG32(SAFETY_GATE, 0x650)
1015REG32(MBIST_RST, 0x700)
1016REG32(MBIST_PG_EN, 0x704)
1017REG32(MBIST_SETUP, 0x708)
1018REG32(MBIST_DONE, 0x710)
1019REG32(MBIST_GOOD, 0x714)
1020REG32(SAFETY_CHK, 0x800)
1021
1022#define R_MAX (R_SAFETY_CHK + 1)
1023
1024typedef struct PMU_GLOBAL {
1025    SysBusDevice parent_obj;
1026    MemoryRegion iomem;
1027    qemu_irq irq_req_pwrdwn_int;
1028    qemu_irq irq_req_swrst_int;
1029    qemu_irq irq_req_logclr_int;
1030    qemu_irq irq_req_pwrup_int;
1031    qemu_irq irq_addr_error_int;
1032    qemu_irq irq_error_int_2;
1033    qemu_irq irq_error_int_1;
1034    qemu_irq irq_req_iso_int;
1035
1036    bool ignore_pwr_req;
1037    /* Record hardware error events, so error status register can be updated
1038     * if error is enabled in error enable register.
1039     */
1040    uint32_t error_1;
1041    uint32_t error_2;
1042
1043    uint32_t regs[R_MAX];
1044    RegisterInfo regs_info[R_MAX];
1045} PMU_GLOBAL;
1046
1047static void req_pwrdwn_int_update_irq(PMU_GLOBAL *s)
1048{
1049    bool pending = s->regs[R_REQ_PWRDWN_STATUS] & ~s->regs[R_REQ_PWRDWN_INT_MASK];
1050    qemu_set_irq(s->irq_req_pwrdwn_int, pending);
1051}
1052
1053static void req_pwrdwn_status_postw(RegisterInfo *reg, uint64_t val64)
1054{
1055    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1056    req_pwrdwn_int_update_irq(s);
1057}
1058
1059static uint64_t req_pwrdwn_int_en_prew(RegisterInfo *reg, uint64_t val64)
1060{
1061    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1062    uint32_t val = val64;
1063
1064    s->regs[R_REQ_PWRDWN_INT_MASK] &= ~val;
1065    req_pwrdwn_int_update_irq(s);
1066    return 0;
1067}
1068
1069static uint64_t req_pwrdwn_int_dis_prew(RegisterInfo *reg, uint64_t val64)
1070{
1071    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1072    uint32_t val = val64;
1073
1074    s->regs[R_REQ_PWRDWN_INT_MASK] |= val;
1075    req_pwrdwn_int_update_irq(s);
1076    return 0;
1077}
1078
1079static uint64_t req_pwrdwn_trig_prew(RegisterInfo *reg, uint64_t val64)
1080{
1081    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1082    uint32_t val = val64;
1083
1084    s->regs[R_REQ_PWRDWN_STATUS] |= val;
1085    req_pwrdwn_int_update_irq(s);
1086    return 0;
1087}
1088
1089static void req_swrst_int_update_irq(PMU_GLOBAL *s)
1090{
1091    bool pending = s->regs[R_REQ_SWRST_STATUS] & ~s->regs[R_REQ_SWRST_INT_MASK];
1092    qemu_set_irq(s->irq_req_swrst_int, pending);
1093}
1094
1095static void req_swrst_status_postw(RegisterInfo *reg, uint64_t val64)
1096{
1097    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1098    req_swrst_int_update_irq(s);
1099}
1100
1101static uint64_t req_swrst_int_en_prew(RegisterInfo *reg, uint64_t val64)
1102{
1103    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1104    uint32_t val = val64;
1105
1106    s->regs[R_REQ_SWRST_INT_MASK] &= ~val;
1107    req_swrst_int_update_irq(s);
1108    return 0;
1109}
1110
1111static uint64_t req_swrst_int_dis_prew(RegisterInfo *reg, uint64_t val64)
1112{
1113    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1114    uint32_t val = val64;
1115
1116    s->regs[R_REQ_SWRST_INT_MASK] |= val;
1117    req_swrst_int_update_irq(s);
1118    return 0;
1119}
1120
1121static uint64_t req_swrst_trig_prew(RegisterInfo *reg, uint64_t val64)
1122{
1123    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1124    uint32_t val = val64;
1125
1126    s->regs[R_REQ_SWRST_STATUS] |= val;
1127    req_swrst_int_update_irq(s);
1128    return 0;
1129}
1130
1131static void req_aux_int_update_irq(PMU_GLOBAL *s)
1132{
1133    bool pending = s->regs[R_REQ_AUX_STATUS] & ~s->regs[R_REQ_AUX_INT_MASK];
1134    qemu_set_irq(s->irq_req_logclr_int, pending);
1135}
1136
1137static void req_aux_status_postw(RegisterInfo *reg, uint64_t val64)
1138{
1139    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1140    req_aux_int_update_irq(s);
1141}
1142
1143static uint64_t req_aux_int_en_prew(RegisterInfo *reg, uint64_t val64)
1144{
1145    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1146    uint32_t val = val64;
1147
1148    s->regs[R_REQ_AUX_INT_MASK] &= ~val;
1149    req_aux_int_update_irq(s);
1150    return 0;
1151}
1152
1153static uint64_t req_aux_int_dis_prew(RegisterInfo *reg, uint64_t val64)
1154{
1155    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1156    uint32_t val = val64;
1157
1158    s->regs[R_REQ_AUX_INT_MASK] |= val;
1159    req_aux_int_update_irq(s);
1160    return 0;
1161}
1162
1163static uint64_t req_aux_trig_prew(RegisterInfo *reg, uint64_t val64)
1164{
1165    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1166    uint32_t val = val64;
1167
1168    s->regs[R_REQ_AUX_STATUS] |= val;
1169    req_aux_int_update_irq(s);
1170    return 0;
1171}
1172
1173static uint64_t error_srst_en_2_prew(RegisterInfo *reg, uint64_t val64)
1174{
1175    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1176    uint32_t val = val64;
1177
1178    s->regs[R_ERROR_SRST_MASK_2] &= ~val;
1179    return 0;
1180}
1181
1182static uint64_t error_srst_dis_2_prew(RegisterInfo *reg, uint64_t val64)
1183{
1184    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1185    uint32_t val = val64;
1186
1187    s->regs[R_ERROR_SRST_MASK_2] |= val;
1188    return 0;
1189}
1190
1191static uint64_t error_srst_en_1_prew(RegisterInfo *reg, uint64_t val64)
1192{
1193    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1194    uint32_t val = val64;
1195
1196    s->regs[R_ERROR_SRST_MASK_1] &= ~val;
1197    return 0;
1198}
1199
1200static uint64_t error_srst_dis_1_prew(RegisterInfo *reg, uint64_t val64)
1201{
1202    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1203    uint32_t val = val64;
1204
1205    s->regs[R_ERROR_SRST_MASK_1] |= val;
1206    return 0;
1207}
1208
1209static uint64_t error_sig_en_2_prew(RegisterInfo *reg, uint64_t val64)
1210{
1211    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1212    uint32_t val = val64;
1213
1214    s->regs[R_ERROR_SIG_MASK_2] &= ~val;
1215    return 0;
1216}
1217
1218static uint64_t error_sig_dis_2_prew(RegisterInfo *reg, uint64_t val64)
1219{
1220    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1221    uint32_t val = val64;
1222
1223    s->regs[R_ERROR_SIG_MASK_2] |= val;
1224    return 0;
1225}
1226
1227static void req_pwrup_int_update_irq(PMU_GLOBAL *s)
1228{
1229    bool pending = s->regs[R_REQ_PWRUP_STATUS] & ~s->regs[R_REQ_PWRUP_INT_MASK];
1230    qemu_set_irq(s->irq_req_pwrup_int, pending);
1231}
1232
1233static void req_pwrup_status_postw(RegisterInfo *reg, uint64_t val64)
1234{
1235    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1236    req_pwrup_int_update_irq(s);
1237}
1238
1239static uint64_t req_pwrup_int_en_prew(RegisterInfo *reg, uint64_t val64)
1240{
1241    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1242    uint32_t val = val64;
1243
1244    s->regs[R_REQ_PWRUP_INT_MASK] &= ~val;
1245    req_pwrup_int_update_irq(s);
1246    return 0;
1247}
1248
1249static uint64_t req_pwrup_int_dis_prew(RegisterInfo *reg, uint64_t val64)
1250{
1251    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1252    uint32_t val = val64;
1253
1254    s->regs[R_REQ_PWRUP_INT_MASK] |= val;
1255    req_pwrup_int_update_irq(s);
1256    return 0;
1257}
1258
1259static uint64_t req_pwrup_trig_prew(RegisterInfo *reg, uint64_t val64)
1260{
1261    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1262    uint32_t val = val64;
1263
1264    if (!s->ignore_pwr_req) {
1265        s->regs[R_REQ_PWRUP_STATUS] |= val;
1266    }
1267    req_pwrup_int_update_irq(s);
1268    return 0;
1269}
1270
1271static uint64_t error_sig_en_1_prew(RegisterInfo *reg, uint64_t val64)
1272{
1273    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1274    uint32_t val = val64;
1275
1276    s->regs[R_ERROR_SIG_MASK_1] &= ~val;
1277    return 0;
1278}
1279
1280static uint64_t error_sig_dis_1_prew(RegisterInfo *reg, uint64_t val64)
1281{
1282    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1283    uint32_t val = val64;
1284
1285    s->regs[R_ERROR_SIG_MASK_1] |= val;
1286    return 0;
1287}
1288
1289static void addr_error_int_update_irq(PMU_GLOBAL *s)
1290{
1291    bool pending = s->regs[R_ADDR_ERROR_STATUS] & ~s->regs[R_ADDR_ERROR_INT_MASK];
1292    qemu_set_irq(s->irq_addr_error_int, pending);
1293}
1294
1295static void addr_error_status_postw(RegisterInfo *reg, uint64_t val64)
1296{
1297    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1298    addr_error_int_update_irq(s);
1299}
1300
1301static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
1302{
1303    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1304    uint32_t val = val64;
1305
1306    s->regs[R_ADDR_ERROR_INT_MASK] &= ~val;
1307    addr_error_int_update_irq(s);
1308    return 0;
1309}
1310
1311static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
1312{
1313    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1314    uint32_t val = val64;
1315
1316    s->regs[R_ADDR_ERROR_INT_MASK] |= val;
1317    addr_error_int_update_irq(s);
1318    return 0;
1319}
1320
1321static void error_int_2_update_irq(PMU_GLOBAL *s)
1322{
1323    bool pending = s->regs[R_ERROR_STATUS_2] & ~s->regs[R_ERROR_INT_MASK_2];
1324    qemu_set_irq(s->irq_error_int_2, pending);
1325}
1326
1327static void error_status_2_postw(RegisterInfo *reg, uint64_t val64)
1328{
1329    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1330    s->error_2 = val64;
1331    error_int_2_update_irq(s);
1332}
1333
1334static uint64_t error_int_en_2_prew(RegisterInfo *reg, uint64_t val64)
1335{
1336    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1337    uint32_t val = val64;
1338
1339    s->regs[R_ERROR_INT_MASK_2] &= ~val;
1340    error_int_2_update_irq(s);
1341    return 0;
1342}
1343
1344static uint64_t error_int_dis_2_prew(RegisterInfo *reg, uint64_t val64)
1345{
1346    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1347    uint32_t val = val64;
1348
1349    s->regs[R_ERROR_INT_MASK_2] |= val;
1350    error_int_2_update_irq(s);
1351    return 0;
1352}
1353
1354static void error_int_1_update_irq(PMU_GLOBAL *s)
1355{
1356    bool pending = s->regs[R_ERROR_STATUS_1] & ~s->regs[R_ERROR_INT_MASK_1];
1357    qemu_set_irq(s->irq_error_int_1, pending);
1358}
1359
1360/* Set error in ERROR_STATUS_1 register if it is enabled in ERROR_EN_1 and
1361 * error input is set.
1362 * Error is only cleared by explicitly writing a 1 to its corresponding
1363 * ERROR_STATUS_1 register bit.
1364 */
1365static void set_error_1(PMU_GLOBAL *s)
1366{
1367    s->regs[R_ERROR_STATUS_1] |= s->error_1 & s->regs[R_ERROR_EN_1];
1368    error_int_1_update_irq(s);
1369}
1370
1371static void error_en_1_postw(RegisterInfo *reg, uint64_t val64)
1372{
1373    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1374
1375    set_error_1(s);
1376}
1377
1378/* Set error in ERROR_STATUS_2 register if it is enabled in ERROR_EN_2 and
1379 * error input is set.
1380 * Error is only cleared by explicitly writing a 1 to its corresponding
1381 * ERROR_STATUS_2 register bit.
1382 */
1383static void set_error_2(PMU_GLOBAL *s)
1384{
1385    s->regs[R_ERROR_STATUS_2] |= s->error_2 & s->regs[R_ERROR_EN_2];
1386    error_int_2_update_irq(s);
1387}
1388
1389static void error_en_2_postw(RegisterInfo *reg, uint64_t val64)
1390{
1391    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1392
1393    set_error_2(s);
1394}
1395
1396static void error_status_1_postw(RegisterInfo *reg, uint64_t val64)
1397{
1398    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1399    s->error_1 = val64;
1400    error_int_1_update_irq(s);
1401}
1402
1403static uint64_t error_int_en_1_prew(RegisterInfo *reg, uint64_t val64)
1404{
1405    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1406    uint32_t val = val64;
1407
1408    s->regs[R_ERROR_INT_MASK_1] &= ~val;
1409    error_int_1_update_irq(s);
1410    return 0;
1411}
1412
1413static uint64_t error_int_dis_1_prew(RegisterInfo *reg, uint64_t val64)
1414{
1415    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1416    uint32_t val = val64;
1417
1418    s->regs[R_ERROR_INT_MASK_1] |= val;
1419    error_int_1_update_irq(s);
1420    return 0;
1421}
1422
1423static uint64_t error_por_en_2_prew(RegisterInfo *reg, uint64_t val64)
1424{
1425    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1426    uint32_t val = val64;
1427
1428    s->regs[R_ERROR_POR_MASK_2] &= ~val;
1429    return 0;
1430}
1431
1432static uint64_t error_por_dis_2_prew(RegisterInfo *reg, uint64_t val64)
1433{
1434    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1435    uint32_t val = val64;
1436
1437    s->regs[R_ERROR_POR_MASK_2] |= val;
1438    return 0;
1439}
1440
1441static uint64_t error_por_en_1_prew(RegisterInfo *reg, uint64_t val64)
1442{
1443    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1444    uint32_t val = val64;
1445
1446    s->regs[R_ERROR_POR_MASK_1] &= ~val;
1447    return 0;
1448}
1449
1450static uint64_t error_por_dis_1_prew(RegisterInfo *reg, uint64_t val64)
1451{
1452    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1453    uint32_t val = val64;
1454
1455    s->regs[R_ERROR_POR_MASK_1] |= val;
1456    return 0;
1457}
1458
1459static void req_iso_int_update_irq(PMU_GLOBAL *s)
1460{
1461    bool pending = s->regs[R_REQ_ISO_STATUS] & ~s->regs[R_REQ_ISO_INT_MASK];
1462    qemu_set_irq(s->irq_req_iso_int, pending);
1463}
1464
1465static void req_iso_status_postw(RegisterInfo *reg, uint64_t val64)
1466{
1467    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1468    req_iso_int_update_irq(s);
1469}
1470
1471static uint64_t req_iso_int_en_prew(RegisterInfo *reg, uint64_t val64)
1472{
1473    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1474    uint32_t val = val64;
1475
1476    s->regs[R_REQ_ISO_INT_MASK] &= ~val;
1477    req_iso_int_update_irq(s);
1478    return 0;
1479}
1480
1481static uint64_t req_iso_int_dis_prew(RegisterInfo *reg, uint64_t val64)
1482{
1483    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1484    uint32_t val = val64;
1485
1486    s->regs[R_REQ_ISO_INT_MASK] |= val;
1487    req_iso_int_update_irq(s);
1488    return 0;
1489}
1490
1491static uint64_t req_iso_trig_prew(RegisterInfo *reg, uint64_t val64)
1492{
1493    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1494    uint32_t val = val64;
1495
1496    s->regs[R_REQ_ISO_STATUS] |= val;
1497    req_iso_int_update_irq(s);
1498    return 0;
1499}
1500
1501static void mbist_rst_postw(RegisterInfo *reg, uint64_t val64)
1502{
1503    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1504
1505    /* Reset the MBIST_DONE, MBIST_GOOD registers */
1506    s->regs[R_MBIST_DONE] &= s->regs[R_MBIST_RST];
1507    s->regs[R_MBIST_GOOD] &= s->regs[R_MBIST_RST];
1508}
1509
1510static void mbist_pg_en_postw(RegisterInfo *reg, uint64_t val64)
1511{
1512    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1513
1514    s->regs[R_MBIST_DONE] |= s->regs[R_MBIST_RST]
1515                           & s->regs[R_MBIST_SETUP] & s->regs[R_MBIST_PG_EN];
1516    s->regs[R_MBIST_GOOD] |= s->regs[R_MBIST_RST]
1517                           & s->regs[R_MBIST_SETUP] & s->regs[R_MBIST_PG_EN];
1518}
1519
1520static RegisterAccessInfo pmu_global_regs_info[] = {
1521    {   .name = "GLOBAL_CNTRL",  .decode.addr = A_GLOBAL_CNTRL,
1522        .rsvd = 0xfffe00e8,
1523        .ro = 0xffff00e8,
1524        .reset = 0x00008800,
1525        .gpios = (RegisterGPIOMapping[]) {
1526            { .name = "pmu_wake", .bit_pos = 0, .width = 1 },
1527            {},
1528        }
1529    },{ .name = "PS_CNTRL",  .decode.addr = A_PS_CNTRL,
1530        .rsvd = 0xfffefffc,
1531        .ro = 0xfffffffc,
1532    },{ .name = "APU_PWR_STATUS_INIT",  .decode.addr = A_APU_PWR_STATUS_INIT,
1533        .rsvd = 0xfffffff0,
1534        .ro = 0xfffffff0,
1535    },{ .name = "ADDR_ERROR_STATUS",  .decode.addr = A_ADDR_ERROR_STATUS,
1536        .rsvd = 0xfffffffe,
1537        .ro = 0xfffffffe,
1538        .w1c = 0x1,
1539        .post_write = addr_error_status_postw,
1540    },{ .name = "ADDR_ERROR_INT_MASK",  .decode.addr = A_ADDR_ERROR_INT_MASK,
1541        .reset = 0x1,
1542        .rsvd = 0xfffffffe,
1543        .ro = 0xffffffff,
1544    },{ .name = "ADDR_ERROR_INT_EN",  .decode.addr = A_ADDR_ERROR_INT_EN,
1545        .pre_write = addr_error_int_en_prew,
1546    },{ .name = "ADDR_ERROR_INT_DIS",  .decode.addr = A_ADDR_ERROR_INT_DIS,
1547        .pre_write = addr_error_int_dis_prew,
1548    },{ .name = "GLOBAL_GEN_STORAGE0",  .decode.addr = A_GLOBAL_GEN_STORAGE0,
1549    },{ .name = "GLOBAL_GEN_STORAGE1",  .decode.addr = A_GLOBAL_GEN_STORAGE1,
1550    },{ .name = "GLOBAL_GEN_STORAGE2",  .decode.addr = A_GLOBAL_GEN_STORAGE2,
1551    },{ .name = "GLOBAL_GEN_STORAGE3",  .decode.addr = A_GLOBAL_GEN_STORAGE3,
1552    },{ .name = "GLOBAL_GEN_STORAGE4",  .decode.addr = A_GLOBAL_GEN_STORAGE4,
1553    },{ .name = "GLOBAL_GEN_STORAGE5",  .decode.addr = A_GLOBAL_GEN_STORAGE5,
1554    },{ .name = "GLOBAL_GEN_STORAGE6",  .decode.addr = A_GLOBAL_GEN_STORAGE6,
1555    },{ .name = "PERS_GLOB_GEN_STORAGE0",  .decode.addr = A_PERS_GLOB_GEN_STORAGE0,
1556        .inhibit_reset = 0xFFFFFFFF,
1557    },{ .name = "PERS_GLOB_GEN_STORAGE1",  .decode.addr = A_PERS_GLOB_GEN_STORAGE1,
1558        .inhibit_reset = 0xFFFFFFFF,
1559    },{ .name = "PERS_GLOB_GEN_STORAGE2",  .decode.addr = A_PERS_GLOB_GEN_STORAGE2,
1560        .inhibit_reset = 0xFFFFFFFF,
1561    },{ .name = "PERS_GLOB_GEN_STORAGE3",  .decode.addr = A_PERS_GLOB_GEN_STORAGE3,
1562        .inhibit_reset = 0xFFFFFFFF,
1563    },{ .name = "PERS_GLOB_GEN_STORAGE4",  .decode.addr = A_PERS_GLOB_GEN_STORAGE4,
1564        .inhibit_reset = 0xFFFFFFFF,
1565    },{ .name = "PERS_GLOB_GEN_STORAGE5",  .decode.addr = A_PERS_GLOB_GEN_STORAGE5,
1566        .inhibit_reset = 0xFFFFFFFF,
1567    },{ .name = "PERS_GLOB_GEN_STORAGE6",  .decode.addr = A_PERS_GLOB_GEN_STORAGE6,
1568        .inhibit_reset = 0xFFFFFFFF,
1569    },{ .name = "PERS_GLOB_GEN_STORAGE7",  .decode.addr = A_PERS_GLOB_GEN_STORAGE7,
1570        .inhibit_reset = 0xFFFFFFFF,
1571    },{ .name = "DDR_CNTRL",  .decode.addr = A_DDR_CNTRL,
1572        .rsvd = 0xfffffffe,
1573    },{ .name = "PWR_STATE",  .decode.addr = A_PWR_STATE,
1574        .reset = 0x00fffcbf,
1575        .rsvd = 0xff000340,
1576        .ro = 0xffffffff,
1577    },{ .name = "AUX_PWR_STATE",  .decode.addr = A_AUX_PWR_STATE,
1578        .reset = 0xff080,
1579        .rsvd = 0x7f00f7f,
1580        .ro = 0xffffffff,
1581    },{ .name = "RAM_RET_CNTRL",  .decode.addr = A_RAM_RET_CNTRL,
1582        .rsvd = 0xfff00f7f,
1583        .ro = 0xfff00f7f,
1584    },{ .name = "PWR_SUPPLY_STATUS",  .decode.addr = A_PWR_SUPPLY_STATUS,
1585        /* FIXME: Added 0x3 to reset bits so FPD will be
1586         * properly powered up by PMUROM.
1587         */
1588        .reset = 0x3,
1589        .rsvd = 0xfffffffc,
1590        .ro = 0xffffffff,
1591    },{ .name = "REQ_PWRUP_STATUS",  .decode.addr = A_REQ_PWRUP_STATUS,
1592        .rsvd = 0xff000b40,
1593        .ro = 0xff000b40,
1594        .w1c = 0xfff4bf,
1595        .post_write = req_pwrup_status_postw,
1596    },{ .name = "REQ_PWRUP_INT_MASK",  .decode.addr = A_REQ_PWRUP_INT_MASK,
1597        .reset = 0xfff4bf,
1598        .rsvd = 0xff000b40,
1599        .ro = 0xffffffff,
1600    },{ .name = "REQ_PWRUP_INT_EN",  .decode.addr = A_REQ_PWRUP_INT_EN,
1601        .pre_write = req_pwrup_int_en_prew,
1602    },{ .name = "REQ_PWRUP_INT_DIS",  .decode.addr = A_REQ_PWRUP_INT_DIS,
1603        .pre_write = req_pwrup_int_dis_prew,
1604    },{ .name = "REQ_PWRUP_TRIG",  .decode.addr = A_REQ_PWRUP_TRIG,
1605        .pre_write = req_pwrup_trig_prew,
1606    },{ .name = "REQ_PWRDWN_STATUS",  .decode.addr = A_REQ_PWRDWN_STATUS,
1607        .rsvd = 0xff000b40,
1608        .ro = 0xff000b40,
1609        .w1c = 0xfff4bf,
1610        .post_write = req_pwrdwn_status_postw,
1611    },{ .name = "REQ_PWRDWN_INT_MASK",  .decode.addr = A_REQ_PWRDWN_INT_MASK,
1612        .reset = 0xfff4bf,
1613        .rsvd = 0xff000b40,
1614        .ro = 0xffffffff,
1615    },{ .name = "REQ_PWRDWN_INT_EN",  .decode.addr = A_REQ_PWRDWN_INT_EN,
1616        .pre_write = req_pwrdwn_int_en_prew,
1617    },{ .name = "REQ_PWRDWN_INT_DIS",  .decode.addr = A_REQ_PWRDWN_INT_DIS,
1618        .pre_write = req_pwrdwn_int_dis_prew,
1619    },{ .name = "REQ_PWRDWN_TRIG",  .decode.addr = A_REQ_PWRDWN_TRIG,
1620        .pre_write = req_pwrdwn_trig_prew,
1621    },{ .name = "REQ_ISO_STATUS",  .decode.addr = A_REQ_ISO_STATUS,
1622        .rsvd = 0xffffffec,
1623        .ro = 0xffffffec,
1624        .w1c = 0x13,
1625        .post_write = req_iso_status_postw,
1626    },{ .name = "REQ_ISO_INT_MASK",  .decode.addr = A_REQ_ISO_INT_MASK,
1627        .reset = 0x13,
1628        .rsvd = 0xffffffec,
1629        .ro = 0xffffffff,
1630    },{ .name = "REQ_ISO_INT_EN",  .decode.addr = A_REQ_ISO_INT_EN,
1631        .pre_write = req_iso_int_en_prew,
1632    },{ .name = "REQ_ISO_INT_DIS",  .decode.addr = A_REQ_ISO_INT_DIS,
1633        .pre_write = req_iso_int_dis_prew,
1634    },{ .name = "REQ_ISO_TRIG",  .decode.addr = A_REQ_ISO_TRIG,
1635        .pre_write = req_iso_trig_prew,
1636    },{ .name = "REQ_SWRST_STATUS",  .decode.addr = A_REQ_SWRST_STATUS,
1637        .rsvd = 0x408e820,
1638        .ro = 0x408e820,
1639        .w1c = 0xfbf717df,
1640        .post_write = req_swrst_status_postw,
1641    },{ .name = "REQ_SWRST_INT_MASK",  .decode.addr = A_REQ_SWRST_INT_MASK,
1642        .reset = 0xfbf717df,
1643        .rsvd = 0x408e820,
1644        .ro = 0xffffffff,
1645    },{ .name = "REQ_SWRST_INT_EN",  .decode.addr = A_REQ_SWRST_INT_EN,
1646        .pre_write = req_swrst_int_en_prew,
1647    },{ .name = "REQ_SWRST_INT_DIS",  .decode.addr = A_REQ_SWRST_INT_DIS,
1648        .pre_write = req_swrst_int_dis_prew,
1649    },{ .name = "REQ_SWRST_TRIG",  .decode.addr = A_REQ_SWRST_TRIG,
1650        .pre_write = req_swrst_trig_prew,
1651    },{ .name = "REQ_AUX_STATUS",  .decode.addr = A_REQ_AUX_STATUS,
1652        .rsvd = 0xfffccb30,
1653        .ro = 0xfffccb30,
1654        .w1c = 0x334cf,
1655        .post_write = req_aux_status_postw,
1656    },{ .name = "REQ_AUX_INT_MASK",  .decode.addr = A_REQ_AUX_INT_MASK,
1657        .reset = 0x334cf,
1658        .rsvd = 0xfffccb30,
1659        .ro = 0xffffffff,
1660    },{ .name = "REQ_AUX_INT_EN",  .decode.addr = A_REQ_AUX_INT_EN,
1661        .pre_write = req_aux_int_en_prew,
1662    },{ .name = "REQ_AUX_INT_DIS",  .decode.addr = A_REQ_AUX_INT_DIS,
1663        .pre_write = req_aux_int_dis_prew,
1664    },{ .name = "REQ_AUX_TRIG",  .decode.addr = A_REQ_AUX_TRIG,
1665        .pre_write = req_aux_trig_prew,
1666    },{ .name = "LOGCLR_STATUS",  .decode.addr = A_LOGCLR_STATUS,
1667        .rsvd = 0xfffccb30,
1668        .ro = 0xffffffff,
1669    },{ .name = "CSU_BR_ERROR",  .decode.addr = A_CSU_BR_ERROR,
1670        .rsvd = 0x7fff0000,
1671        .ro = 0x7fff0000,
1672    },{ .name = "MB_FAULT_STATUS",  .decode.addr = A_MB_FAULT_STATUS,
1673        .rsvd = 0xf000f0,
1674        .ro = 0xffffffff,
1675    },{ .name = "ERROR_STATUS_1",  .decode.addr = A_ERROR_STATUS_1,
1676        .rsvd = 0xcd00,
1677        .ro = 0xcd00,
1678        .w1c = 0x3ff32ff,
1679        .post_write = error_status_1_postw,
1680    },{ .name = "ERROR_INT_MASK_1",  .decode.addr = A_ERROR_INT_MASK_1,
1681        .reset = 0x3ff32ff,
1682        .rsvd = 0xcd00,
1683        .ro = 0x3ffffff,
1684    },{ .name = "ERROR_INT_EN_1",  .decode.addr = A_ERROR_INT_EN_1,
1685        .rsvd = 0xcd00,
1686        .pre_write = error_int_en_1_prew,
1687    },{ .name = "ERROR_INT_DIS_1",  .decode.addr = A_ERROR_INT_DIS_1,
1688        .rsvd = 0xcd00,
1689        .pre_write = error_int_dis_1_prew,
1690    },{ .name = "ERROR_STATUS_2",  .decode.addr = A_ERROR_STATUS_2,
1691        .rsvd = 0xf8c0e0c0,
1692        .ro = 0xf8c0e0c0,
1693        .w1c = 0x73f1f3f,
1694        .post_write = error_status_2_postw,
1695    },{ .name = "ERROR_INT_MASK_2",  .decode.addr = A_ERROR_INT_MASK_2,
1696        .reset = 0x13f1f3f,
1697        .rsvd = 0xf8c0e0c0,
1698        .ro = 0xffffffff,
1699    },{ .name = "ERROR_INT_EN_2",  .decode.addr = A_ERROR_INT_EN_2,
1700        .rsvd = 0xf8c0e0c0,
1701        .pre_write = error_int_en_2_prew,
1702    },{ .name = "ERROR_INT_DIS_2",  .decode.addr = A_ERROR_INT_DIS_2,
1703        .rsvd = 0xf8c0e0c0,
1704        .pre_write = error_int_dis_2_prew,
1705    },{ .name = "ERROR_POR_MASK_1",  .decode.addr = A_ERROR_POR_MASK_1,
1706        .reset = 0x3ff32ff,
1707        .rsvd = 0xcd00,
1708        .ro = 0x3ffffff,
1709    },{ .name = "ERROR_POR_EN_1",  .decode.addr = A_ERROR_POR_EN_1,
1710        .rsvd = 0xcd00,
1711        .pre_write = error_por_en_1_prew,
1712    },{ .name = "ERROR_POR_DIS_1",  .decode.addr = A_ERROR_POR_DIS_1,
1713        .rsvd = 0xcd00,
1714        .pre_write = error_por_dis_1_prew,
1715    },{ .name = "ERROR_POR_MASK_2",  .decode.addr = A_ERROR_POR_MASK_2,
1716        .reset = 0x13f1f3f,
1717        .rsvd = 0xf8c0e0c0,
1718        .ro = 0xffffffff,
1719    },{ .name = "ERROR_POR_EN_2",  .decode.addr = A_ERROR_POR_EN_2,
1720        .rsvd = 0xf8c0e0c0,
1721        .pre_write = error_por_en_2_prew,
1722    },{ .name = "ERROR_POR_DIS_2",  .decode.addr = A_ERROR_POR_DIS_2,
1723        .rsvd = 0xf8c0e0c0,
1724        .pre_write = error_por_dis_2_prew,
1725    },{ .name = "ERROR_SRST_MASK_1",  .decode.addr = A_ERROR_SRST_MASK_1,
1726        .reset = 0x3ff32ff,
1727        .rsvd = 0xcd00,
1728        .ro = 0x3ffffff,
1729    },{ .name = "ERROR_SRST_EN_1",  .decode.addr = A_ERROR_SRST_EN_1,
1730        .rsvd = 0xcd00,
1731        .pre_write = error_srst_en_1_prew,
1732    },{ .name = "ERROR_SRST_DIS_1",  .decode.addr = A_ERROR_SRST_DIS_1,
1733        .rsvd = 0xcd00,
1734        .pre_write = error_srst_dis_1_prew,
1735    },{ .name = "ERROR_SRST_MASK_2",  .decode.addr = A_ERROR_SRST_MASK_2,
1736        .reset = 0x13f1f3f,
1737        .rsvd = 0xf8c0e0c0,
1738        .ro = 0xffffffff,
1739    },{ .name = "ERROR_SRST_EN_2",  .decode.addr = A_ERROR_SRST_EN_2,
1740        .rsvd = 0xf8c0e0c0,
1741        .pre_write = error_srst_en_2_prew,
1742    },{ .name = "ERROR_SRST_DIS_2",  .decode.addr = A_ERROR_SRST_DIS_2,
1743        .rsvd = 0xf8c0e0c0,
1744        .pre_write = error_srst_dis_2_prew,
1745    },{ .name = "ERROR_SIG_MASK_1",  .decode.addr = A_ERROR_SIG_MASK_1,
1746        .rsvd = 0xcd00,
1747        .ro = 0x3ffffff,
1748    },{ .name = "ERROR_SIG_EN_1",  .decode.addr = A_ERROR_SIG_EN_1,
1749        .rsvd = 0xcd00,
1750        .pre_write = error_sig_en_1_prew,
1751    },{ .name = "ERROR_SIG_DIS_1",  .decode.addr = A_ERROR_SIG_DIS_1,
1752        .rsvd = 0xcd00,
1753        .pre_write = error_sig_dis_1_prew,
1754    },{ .name = "ERROR_SIG_MASK_2",  .decode.addr = A_ERROR_SIG_MASK_2,
1755        .rsvd = 0xf8c0e0c0,
1756        .ro = 0xffffffff,
1757    },{ .name = "ERROR_SIG_EN_2",  .decode.addr = A_ERROR_SIG_EN_2,
1758        .rsvd = 0xf8c0e0c0,
1759        .pre_write = error_sig_en_2_prew,
1760    },{ .name = "ERROR_SIG_DIS_2",  .decode.addr = A_ERROR_SIG_DIS_2,
1761        .rsvd = 0xf8c0e0c0,
1762        .pre_write = error_sig_dis_2_prew,
1763    },{ .name = "ERROR_EN_1",  .decode.addr = A_ERROR_EN_1,
1764        .post_write = error_en_1_postw,
1765    },{ .name = "ERROR_EN_2",  .decode.addr = A_ERROR_EN_2,
1766        .post_write = error_en_2_postw,
1767    },{ .name = "AIB_CNTRL",  .decode.addr = A_AIB_CNTRL,
1768        .rsvd = 0xfffffff0,
1769    },{ .name = "AIB_STATUS",  .decode.addr = A_AIB_STATUS,
1770        .rsvd = 0xfffffff0,
1771        .ro = 0xffffffff,
1772    },{ .name = "GLOBAL_RESET",  .decode.addr = A_GLOBAL_RESET,
1773        .rsvd = 0xfffff8ff,
1774        .ro = 0xfffff8ff,
1775        .gpios = (RegisterGPIOMapping[]) {
1776            { .name = "FPD_RST", .bit_pos = 9, .width = 1 },
1777            { .name = "PS_ONLY_RST", .bit_pos = 10, .width = 1 },
1778            {},
1779        }
1780    },{ .name = "ROM_VALIDATION_STATUS",  .decode.addr = A_ROM_VALIDATION_STATUS,
1781        .rsvd = 0xfffffffc,
1782        .ro = 0xffffffff,
1783    },{ .name = "ROM_VALIDATION_DIGEST_0",  .decode.addr = A_ROM_VALIDATION_DIGEST_0,
1784        .ro = 0xffffffff,
1785    },{ .name = "ROM_VALIDATION_DIGEST_1",  .decode.addr = A_ROM_VALIDATION_DIGEST_1,
1786        .ro = 0xffffffff,
1787    },{ .name = "ROM_VALIDATION_DIGEST_2",  .decode.addr = A_ROM_VALIDATION_DIGEST_2,
1788        .ro = 0xffffffff,
1789    },{ .name = "ROM_VALIDATION_DIGEST_3",  .decode.addr = A_ROM_VALIDATION_DIGEST_3,
1790        .ro = 0xffffffff,
1791    },{ .name = "ROM_VALIDATION_DIGEST_4",  .decode.addr = A_ROM_VALIDATION_DIGEST_4,
1792        .ro = 0xffffffff,
1793    },{ .name = "ROM_VALIDATION_DIGEST_5",  .decode.addr = A_ROM_VALIDATION_DIGEST_5,
1794        .ro = 0xffffffff,
1795    },{ .name = "ROM_VALIDATION_DIGEST_6",  .decode.addr = A_ROM_VALIDATION_DIGEST_6,
1796        .ro = 0xffffffff,
1797    },{ .name = "ROM_VALIDATION_DIGEST_7",  .decode.addr = A_ROM_VALIDATION_DIGEST_7,
1798        .ro = 0xffffffff,
1799    },{ .name = "ROM_VALIDATION_DIGEST_8",  .decode.addr = A_ROM_VALIDATION_DIGEST_8,
1800        .ro = 0xffffffff,
1801    },{ .name = "ROM_VALIDATION_DIGEST_9",  .decode.addr = A_ROM_VALIDATION_DIGEST_9,
1802        .ro = 0xffffffff,
1803    },{ .name = "ROM_VALIDATION_DIGEST_10",  .decode.addr = A_ROM_VALIDATION_DIGEST_10,
1804        .ro = 0xffffffff,
1805    },{ .name = "ROM_VALIDATION_DIGEST_11",  .decode.addr = A_ROM_VALIDATION_DIGEST_11,
1806        .ro = 0xffffffff,
1807    },{ .name = "SAFETY_GATE",  .decode.addr = A_SAFETY_GATE,
1808    },{ .name = "MBIST_RST",  .decode.addr = A_MBIST_RST,
1809        .post_write = mbist_rst_postw,
1810    },{ .name = "MBIST_PG_EN",  .decode.addr = A_MBIST_PG_EN,
1811        .post_write = mbist_pg_en_postw,
1812    },{ .name = "MBIST_SETUP",  .decode.addr = A_MBIST_SETUP,
1813    },{ .name = "MBIST_DONE",  .decode.addr = A_MBIST_DONE, .ro = 0xffffffff,
1814    },{ .name = "MBIST_GOOD",  .decode.addr = A_MBIST_GOOD, .ro = 0xffffffff,
1815    },{ .name = "SAFETY_CHK",  .decode.addr = A_SAFETY_CHK,
1816    }
1817};
1818
1819static void pmu_global_reset(DeviceState *dev)
1820{
1821    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(dev);
1822    unsigned int i;
1823
1824    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
1825        register_reset(&s->regs_info[i]);
1826    }
1827
1828    s->error_1 = 0;
1829    s->error_2 = 0;
1830
1831    req_pwrdwn_int_update_irq(s);
1832    req_swrst_int_update_irq(s);
1833    req_aux_int_update_irq(s);
1834    req_pwrup_int_update_irq(s);
1835    addr_error_int_update_irq(s);
1836    error_int_2_update_irq(s);
1837    error_int_1_update_irq(s);
1838    req_iso_int_update_irq(s);
1839}
1840
1841static void pwr_state_handler(void *opaque, int n, int level)
1842{
1843    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1844
1845    s->regs[R_PWR_STATE] = deposit32(s->regs[R_PWR_STATE], n, 1, level);
1846}
1847
1848static void error_handler(void *opaque, int n, int level)
1849{
1850    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1851
1852    /* First 32 gpios are for ERROR_STATUS_1 */
1853    if (n < 32) {
1854        s->error_1 = deposit32(s->error_1, n, 1, level);
1855        set_error_1(s);
1856    } else {
1857        s->error_2 = deposit32(s->error_2, n, 1, level);
1858        set_error_2(s);
1859    }
1860}
1861
1862static uint64_t pmu_global_read(void *opaque, hwaddr addr, unsigned size,
1863                                MemTxAttrs attr)
1864{
1865    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1866    RegisterInfo *r = &s->regs_info[addr / 4];
1867
1868    if (!r->data) {
1869        qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
1870                 object_get_canonical_path(OBJECT(s)),
1871                 addr);
1872        s->regs[R_ADDR_ERROR_STATUS] |= R_ADDR_ERROR_STATUS_STATUS_MASK;
1873        addr_error_int_update_irq(s);
1874        return 0;
1875    }
1876    return register_read(r);
1877}
1878
1879static void pmu_global_write(void *opaque, hwaddr addr, uint64_t value,
1880                      unsigned size, MemTxAttrs attr)
1881{
1882    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1883    RegisterInfo *r = &s->regs_info[addr / 4];
1884
1885    if (!r->data) {
1886        qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
1887                 object_get_canonical_path(OBJECT(s)),
1888                 addr, value);
1889        s->regs[R_ADDR_ERROR_STATUS] |= R_ADDR_ERROR_STATUS_STATUS_MASK;
1890        addr_error_int_update_irq(s);
1891        return;
1892    }
1893    register_write(r, value, ~0);
1894}
1895
1896static void pmu_global_access(MemoryTransaction *tr)
1897{
1898    MemTxAttrs attr = tr->attr;
1899    void *opaque = tr->opaque;
1900    hwaddr addr = tr->addr;
1901    unsigned size = tr->size;
1902    uint64_t value = tr->data.u64;;
1903    bool is_write = tr->rw;
1904
1905    if (!attr.secure) {
1906        /* Ignore NS accesses.  */
1907        if (!is_write) {
1908            tr->data.u64 = 0;
1909        }
1910        qemu_log_mask(LOG_GUEST_ERROR,
1911                      "Non secure accesses to PMU global are invalid\n");
1912        return;
1913    }
1914
1915    if (is_write) {
1916        pmu_global_write(opaque, addr, value, size, attr);
1917    } else {
1918        tr->data.u64 = pmu_global_read(opaque, addr, size, attr);
1919    }
1920}
1921
1922static const MemoryRegionOps pmu_global_ops = {
1923    .access = pmu_global_access,
1924    .endianness = DEVICE_LITTLE_ENDIAN,
1925    .valid = {
1926        .min_access_size = 4,
1927        .max_access_size = 4,
1928    },
1929};
1930
1931static void gpio_mb_sleep_h(void *opaque, int n, int level)
1932{
1933    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1934    AF_DP32(s->regs, GLOBAL_CNTRL, MB_SLEEP, !!level);
1935}
1936
1937static void pmu_global_realize(DeviceState *dev, Error **errp)
1938{
1939    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(dev);
1940    const char *prefix = object_get_canonical_path(OBJECT(dev));
1941    unsigned int i;
1942
1943    for (i = 0; i < ARRAY_SIZE(pmu_global_regs_info); ++i) {
1944        RegisterInfo *r = &s->regs_info[pmu_global_regs_info[i].decode.addr/4];
1945
1946        *r = (RegisterInfo) {
1947            .data = (uint8_t *)&s->regs[
1948                    pmu_global_regs_info[i].decode.addr/4],
1949            .data_size = sizeof(uint32_t),
1950            .access = &pmu_global_regs_info[i],
1951            .debug = XILINX_PMU_GLOBAL_ERR_DEBUG,
1952            .prefix = prefix,
1953            .opaque = s,
1954        };
1955        register_init(r);
1956        qdev_pass_all_gpios(DEVICE(r), dev);
1957    }
1958}
1959
1960static void pmu_global_init(Object *obj)
1961{
1962    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(obj);
1963    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1964
1965    memory_region_init_io(&s->iomem, obj, &pmu_global_ops, s,
1966                          TYPE_XILINX_PMU_GLOBAL, R_MAX * 4);
1967    sysbus_init_mmio(sbd, &s->iomem);
1968    sysbus_init_irq(sbd, &s->irq_req_logclr_int); /* 23 */
1969    sysbus_init_irq(sbd, &s->irq_req_iso_int);    /* 24 */
1970    sysbus_init_irq(sbd, &s->irq_req_swrst_int);  /* 26 */
1971    sysbus_init_irq(sbd, &s->irq_req_pwrup_int);  /* 27 */
1972    sysbus_init_irq(sbd, &s->irq_req_pwrdwn_int); /* 28 */
1973    sysbus_init_irq(sbd, &s->irq_addr_error_int); /* 29 */
1974
1975    qdev_init_gpio_in_named(DEVICE(obj), gpio_mb_sleep_h, "mb_sleep", 1);
1976    qdev_init_gpio_in_named(DEVICE(obj), pwr_state_handler, "pwr_state", 24);
1977    qdev_init_gpio_out_named(DEVICE(obj), &s->irq_error_int_1,
1978                             "error_1_out", 1);
1979    qdev_init_gpio_out_named(DEVICE(obj), &s->irq_error_int_2,
1980                             "error_2_out", 1);
1981
1982    /* GPIOs that can be used from qtest */
1983    qdev_init_gpio_in(DEVICE(obj), error_handler, 64);
1984}
1985
1986static const VMStateDescription vmstate_pmu_global = {
1987    .name = TYPE_XILINX_PMU_GLOBAL,
1988    .version_id = 1,
1989    .minimum_version_id = 1,
1990    .minimum_version_id_old = 1,
1991    .fields = (VMStateField[]) {
1992        VMSTATE_UINT32_ARRAY(regs, PMU_GLOBAL, R_MAX),
1993        VMSTATE_END_OF_LIST(),
1994    }
1995};
1996
1997static const FDTGenericGPIOSet pmu_gpios[] = {
1998    {
1999      .names = &fdt_generic_gpio_name_set_gpio,
2000      .gpios = (FDTGenericGPIOConnection[]) {
2001        { .name = "pmu_wake", .fdt_index = 0 },
2002        { .name = "FPD_RST", .fdt_index = 2 },
2003        { .name = "PS_ONLY_RST", .fdt_index = 3 },
2004        { },
2005      },
2006    },
2007    { },
2008};
2009
2010static const FDTGenericGPIONameSet pwr_state_gpios_names = {
2011    .propname = "pwr-state-gpios",
2012    .cells_propname = "#gpio-cells",
2013    .names_propname = "pwr-state-gpio-names",
2014};
2015
2016static const FDTGenericGPIONameSet error_out_gpios_names = {
2017    .propname = "error-out-gpios",
2018    .cells_propname = "#gpio-cells",
2019    .names_propname = "error-out-names",
2020};
2021
2022static const FDTGenericGPIOSet pmu_global_client_gpios[] = {
2023    {
2024      .names = &pwr_state_gpios_names,
2025      .gpios = (FDTGenericGPIOConnection[]) {
2026        { .name = "pwr_state", .fdt_index = 0, .range = 24 },
2027        { },
2028      },
2029    },
2030    {
2031      .names = &fdt_generic_gpio_name_set_gpio,
2032      .gpios = (FDTGenericGPIOConnection[]) {
2033        { .name = "mb_sleep", .fdt_index = 1 },
2034        { },
2035      },
2036    },
2037    {
2038      .names = &error_out_gpios_names,
2039      .gpios = (FDTGenericGPIOConnection[]) {
2040        { .name = "error_1_out", .fdt_index = 0 },
2041        { .name = "error_2_out", .fdt_index = 1 },
2042        { },
2043      },
2044    },
2045    { },
2046};
2047
2048static Property pmu_global_properties[] = {
2049    DEFINE_PROP_BOOL("ignore-pwr-req", PMU_GLOBAL, ignore_pwr_req, false),
2050    DEFINE_PROP_END_OF_LIST(),
2051};
2052
2053static void pmu_global_class_init(ObjectClass *klass, void *data)
2054{
2055    DeviceClass *dc = DEVICE_CLASS(klass);
2056    FDTGenericGPIOClass *fggc = FDT_GENERIC_GPIO_CLASS(klass);
2057
2058    dc->reset = pmu_global_reset;
2059    dc->realize = pmu_global_realize;
2060    dc->vmsd = &vmstate_pmu_global;
2061    dc->props = pmu_global_properties;
2062    fggc->controller_gpios = pmu_gpios;
2063    fggc->client_gpios = pmu_global_client_gpios;
2064}
2065
2066static const TypeInfo pmu_global_info = {
2067    .name          = TYPE_XILINX_PMU_GLOBAL,
2068    .parent        = TYPE_SYS_BUS_DEVICE,
2069    .instance_size = sizeof(PMU_GLOBAL),
2070    .class_init    = pmu_global_class_init,
2071    .instance_init = pmu_global_init,
2072    .interfaces    = (InterfaceInfo[]) {
2073        { TYPE_FDT_GENERIC_GPIO },
2074        { }
2075    },
2076};
2077
2078static void pmu_global_register_types(void)
2079{
2080    type_register_static(&pmu_global_info);
2081}
2082
2083type_init(pmu_global_register_types)
2084