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25#include "qemu/osdep.h"
26#include <zlib.h>
27
28#include "hw/net/cadence_gem.h"
29#include "net/checksum.h"
30#include "sysemu/dma.h"
31#include "qemu/log.h"
32#include "qapi/error.h"
33#include "hw/net/cadence_gem.h"
34
35#ifdef CADENCE_GEM_ERR_DEBUG
36#define DB_PRINT(...) do { \
37 qemu_log_mask(DEV_LOG_NET_DEV, ": %s: ", __func__); \
38 qemu_log_mask(DEV_LOG_NET_DEV, ## __VA_ARGS__); \
39 } while (0);
40#else
41 #define DB_PRINT(...)
42#endif
43
44#define GEM_NWCTRL (0x00000000/4)
45#define GEM_NWCFG (0x00000004/4)
46#define GEM_NWSTATUS (0x00000008/4)
47#define GEM_USERIO (0x0000000C/4)
48#define GEM_DMACFG (0x00000010/4)
49#define GEM_TXSTATUS (0x00000014/4)
50#define GEM_RXQBASE (0x00000018/4)
51#define GEM_TXQBASE (0x0000001C/4)
52#define GEM_RXSTATUS (0x00000020/4)
53#define GEM_ISR (0x00000024/4)
54#define GEM_IER (0x00000028/4)
55#define GEM_IDR (0x0000002C/4)
56#define GEM_IMR (0x00000030/4)
57#define GEM_PHYMNTNC (0x00000034/4)
58#define GEM_RXPAUSE (0x00000038/4)
59#define GEM_TXPAUSE (0x0000003C/4)
60#define GEM_TXPARTIALSF (0x00000040/4)
61#define GEM_RXPARTIALSF (0x00000044/4)
62#define GEM_HASHLO (0x00000080/4)
63#define GEM_HASHHI (0x00000084/4)
64#define GEM_SPADDR1LO (0x00000088/4)
65#define GEM_SPADDR1HI (0x0000008C/4)
66#define GEM_SPADDR2LO (0x00000090/4)
67#define GEM_SPADDR2HI (0x00000094/4)
68#define GEM_SPADDR3LO (0x00000098/4)
69#define GEM_SPADDR3HI (0x0000009C/4)
70#define GEM_SPADDR4LO (0x000000A0/4)
71#define GEM_SPADDR4HI (0x000000A4/4)
72#define GEM_TIDMATCH1 (0x000000A8/4)
73#define GEM_TIDMATCH2 (0x000000AC/4)
74#define GEM_TIDMATCH3 (0x000000B0/4)
75#define GEM_TIDMATCH4 (0x000000B4/4)
76#define GEM_WOLAN (0x000000B8/4)
77#define GEM_IPGSTRETCH (0x000000BC/4)
78#define GEM_SVLAN (0x000000C0/4)
79#define GEM_REVISION (0x000000FC/4)
80#define GEM_OCTTXLO (0x00000100/4)
81#define GEM_OCTTXHI (0x00000104/4)
82#define GEM_TXCNT (0x00000108/4)
83#define GEM_TXBCNT (0x0000010C/4)
84#define GEM_TXMCNT (0x00000110/4)
85#define GEM_TXPAUSECNT (0x00000114/4)
86#define GEM_TX64CNT (0x00000118/4)
87#define GEM_TX65CNT (0x0000011C/4)
88#define GEM_TX128CNT (0x00000120/4)
89#define GEM_TX256CNT (0x00000124/4)
90#define GEM_TX512CNT (0x00000128/4)
91#define GEM_TX1024CNT (0x0000012C/4)
92#define GEM_TX1519CNT (0x00000130/4)
93#define GEM_TXURUNCNT (0x00000134/4)
94#define GEM_SINGLECOLLCNT (0x00000138/4)
95#define GEM_MULTCOLLCNT (0x0000013C/4)
96#define GEM_EXCESSCOLLCNT (0x00000140/4)
97#define GEM_LATECOLLCNT (0x00000144/4)
98#define GEM_DEFERTXCNT (0x00000148/4)
99#define GEM_CSENSECNT (0x0000014C/4)
100#define GEM_OCTRXLO (0x00000150/4)
101#define GEM_OCTRXHI (0x00000154/4)
102#define GEM_RXCNT (0x00000158/4)
103#define GEM_RXBROADCNT (0x0000015C/4)
104#define GEM_RXMULTICNT (0x00000160/4)
105#define GEM_RXPAUSECNT (0x00000164/4)
106#define GEM_RX64CNT (0x00000168/4)
107#define GEM_RX65CNT (0x0000016C/4)
108#define GEM_RX128CNT (0x00000170/4)
109#define GEM_RX256CNT (0x00000174/4)
110#define GEM_RX512CNT (0x00000178/4)
111#define GEM_RX1024CNT (0x0000017C/4)
112#define GEM_RX1519CNT (0x00000180/4)
113#define GEM_RXUNDERCNT (0x00000184/4)
114#define GEM_RXOVERCNT (0x00000188/4)
115#define GEM_RXJABCNT (0x0000018C/4)
116#define GEM_RXFCSCNT (0x00000190/4)
117#define GEM_RXLENERRCNT (0x00000194/4)
118#define GEM_RXSYMERRCNT (0x00000198/4)
119#define GEM_RXALIGNERRCNT (0x0000019C/4)
120#define GEM_RXRSCERRCNT (0x000001A0/4)
121#define GEM_RXORUNCNT (0x000001A4/4)
122#define GEM_RXIPCSERRCNT (0x000001A8/4)
123#define GEM_RXTCPCCNT (0x000001AC/4)
124#define GEM_RXUDPCCNT (0x000001B0/4)
125
126#define GEM_1588S (0x000001D0/4)
127#define GEM_1588NS (0x000001D4/4)
128#define GEM_1588ADJ (0x000001D8/4)
129#define GEM_1588INC (0x000001DC/4)
130#define GEM_PTPETXS (0x000001E0/4)
131#define GEM_PTPETXNS (0x000001E4/4)
132#define GEM_PTPERXS (0x000001E8/4)
133#define GEM_PTPERXNS (0x000001EC/4)
134#define GEM_PTPPTXS (0x000001E0/4)
135#define GEM_PTPPTXNS (0x000001E4/4)
136#define GEM_PTPPRXS (0x000001E8/4)
137#define GEM_PTPPRXNS (0x000001EC/4)
138
139
140#define GEM_DESCONF (0x00000280/4)
141#define GEM_DESCONF2 (0x00000284/4)
142#define GEM_DESCONF3 (0x00000288/4)
143#define GEM_DESCONF4 (0x0000028C/4)
144#define GEM_DESCONF5 (0x00000290/4)
145#define GEM_DESCONF6 (0x00000294/4)
146#define GEM_DESCONF7 (0x00000298/4)
147
148#define GEM_INT_Q1_STATUS (0x00000400/4)
149#define GEM_TRANSMIT_Q1_PTR (0x00000440/4)
150#define GEM_TRANSMIT_Q15_PTR (GEM_TRANSMIT_Q1_PTR + 14)
151#define GEM_RECEIVE_Q1_PTR (0x00000480/4)
152#define GEM_RECEIVE_Q15_PTR (GEM_RECEIVE_Q1_PTR + 14)
153#define GEM_DMA_RXBUF_SIZE_Q1 (0x000004a0/4)
154#define GEM_CBS_CONTROL (0x000004bc/4)
155#define GEM_CBS_IDLESLOPE_Q_A (0x000004c0/4)
156#define GEM_CBS_IDLESLOPE_Q_B (0x000004c4/4)
157#define GEM_MSB_BUFF_Q_BASE_ADDR (0x000004c8/4)
158
159#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500/4)
160
161#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
162#define GEM_ST1R_DSTC_ENABLE (1 << 28)
163#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
164#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
165#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
166#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
167#define GEM_ST1R_QUEUE_SHIFT (0)
168#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
169
170#define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540/4)
171
172#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
173#define GEM_ST2R_COMPARE_A_SHIFT (13)
174#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
175#define GEM_ST2R_COMPARE_END (31)
176#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
177#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
178#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
179 + 1)
180#define GEM_ST2R_QUEUE_SHIFT (0)
181#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
182
183
184#define GEM_RECIEVE_Q8_PTR (0x000005c0/4)
185#define GEM_DMA_RXBUF_SIZE_Q8 (0x000005e0/4)
186
187#define GEM_INT_Q1_ENABLE (0x00000600/4)
188#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
189#define GEM_INT_Q1_DISABLE (0x00000620/4)
190#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
191#define GEM_INT_Q1_MASK (0x00000640/4)
192#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
193#define GEM_INT_Q8_ENABLE (0x00000660/4)
194#define GEM_INT_Q15_ENABLE (GEM_INT_Q8_ENABLE + 7)
195#define GEM_INT_Q8_DISABLE (0x00000680/4)
196#define GEM_INT_Q15_DISABLE (GEM_INT_Q8_DISABLE + 7)
197#define GEM_INT_Q8_MASK (0x000006A0/4)
198#define GEM_INT_Q15_MASK (GEM_INT_Q8_MASK + 7)
199
200#define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0/4)
201#define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700/4)
202#define GEM_TYPE2_COMPARE_0_WORD_1 (0x00000704/4)
203
204#define gem_sr(queue, ...) \
205 ({ \
206 uint32_t array_args[] = { __VA_ARGS__ }; \
207 int __gem_sr_i__; \
208 uint32_t ret = 0; \
209 \
210 for (__gem_sr_i__ = 0; __gem_sr_i__ < ARRAY_SIZE(array_args); \
211 __gem_sr_i__ += 2) { \
212 if (queue >= array_args[__gem_sr_i__]) { \
213 ret = queue - array_args[__gem_sr_i__] + \
214 array_args[__gem_sr_i__ + 1]; \
215 } \
216 } \
217 assert(ret); \
218 ret; \
219 })
220
221#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
222#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
223#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
224#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
225
226
227#define GEM_NWCTRL_TXSTART 0x00000200
228#define GEM_NWCTRL_TXENA 0x00000008
229#define GEM_NWCTRL_RXENA 0x00000004
230#define GEM_NWCTRL_LOCALLOOP 0x00000002
231
232#define GEM_NWCFG_STRIP_FCS 0x00020000
233#define GEM_NWCFG_LERR_DISC 0x00010000
234#define GEM_NWCFG_BUFF_OFST_M 0x0000C000
235#define GEM_NWCFG_BUFF_OFST_S 14
236#define GEM_NWCFG_UCAST_HASH 0x00000080
237#define GEM_NWCFG_MCAST_HASH 0x00000040
238#define GEM_NWCFG_BCAST_REJ 0x00000020
239#define GEM_NWCFG_PROMISC 0x00000010
240
241#define GEM_DMACFG_ADDR_BUS_WIDTH_M 0x40000000
242#define GEM_DMACFG_TX_BD_EXT (1 << 29)
243#define GEM_DMACFG_RX_BD_EXT (1 << 28)
244#define GEM_DMACFG_RBUFSZ_M 0x00FF0000
245#define GEM_DMACFG_RBUFSZ_S 16
246#define GEM_DMACFG_RBUFSZ_MUL 64
247#define GEM_DMACFG_TXCSUM_OFFL 0x00000800
248
249#define GEM_TXSTATUS_TXCMPL 0x00000020
250#define GEM_TXSTATUS_USED 0x00000001
251
252#define GEM_RXSTATUS_FRMRCVD 0x00000002
253#define GEM_RXSTATUS_NOBUF 0x00000001
254
255
256#define GEM_INT_TXCMPL 0x00000080
257#define GEM_INT_TXUSED 0x00000008
258#define GEM_INT_RXUSED 0x00000004
259#define GEM_INT_RXCMPL 0x00000002
260#define GEM_INT_LINK_CHNG 0x00000200
261#define GEM_INT_AUTONEG 0x00010000
262
263#define GEM_PHYMNTNC_OP_R 0x20000000
264#define GEM_PHYMNTNC_OP_W 0x10000000
265#define GEM_PHYMNTNC_ADDR 0x0F800000
266#define GEM_PHYMNTNC_ADDR_SHFT 23
267#define GEM_PHYMNTNC_REG 0x007C0000
268#define GEM_PHYMNTNC_REG_SHIFT 18
269
270
271#define BOARD_PHY_ADDRESS 7
272
273#define PHY_REG_CONTROL 0
274#define PHY_REG_STATUS 1
275#define PHY_REG_PHYID1 2
276#define PHY_REG_PHYID2 3
277#define PHY_REG_ANEGADV 4
278#define PHY_REG_LINKPABIL 5
279#define PHY_REG_ANEGEXP 6
280#define PHY_REG_NEXTP 7
281#define PHY_REG_LINKPNEXTP 8
282#define PHY_REG_100BTCTRL 9
283#define PHY_REG_1000BTSTAT 10
284#define PHY_REG_EXTSTAT 15
285#define PHY_REG_PHYSPCFC_CTL 16
286#define PHY_REG_PHYSPCFC_ST 17
287#define PHY_REG_INT_EN 18
288#define PHY_REG_INT_ST 19
289#define PHY_REG_EXT_PHYSPCFC_CTL 20
290#define PHY_REG_RXERR 21
291#define PHY_REG_EACD 22
292#define PHY_REG_LED 24
293#define PHY_REG_LED_OVRD 25
294#define PHY_REG_EXT_PHYSPCFC_CTL2 26
295#define PHY_REG_EXT_PHYSPCFC_ST 27
296#define PHY_REG_CABLE_DIAG 28
297
298#define PHY_REG_CONTROL_RST 0x8000
299#define PHY_REG_CONTROL_LOOP 0x4000
300#define PHY_REG_CONTROL_ANEG 0x1000
301
302#define PHY_REG_STATUS_LINK 0x0004
303#define PHY_REG_STATUS_ANEGCMPL 0x0020
304
305#define PHY_REG_INT_ST_ANEGCMPL 0x0800
306#define PHY_REG_INT_ST_LINKC 0x0400
307#define PHY_REG_INT_ST_ENERGY 0x0010
308
309
310#define GEM_RX_REJECT (-1)
311#define GEM_RX_PROMISCUOUS_ACCEPT (-2)
312#define GEM_RX_BROADCAST_ACCEPT (-3)
313#define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
314#define GEM_RX_UNICAST_HASH_ACCEPT (-5)
315
316#define GEM_RX_SAR_ACCEPT 0
317
318
319
320#define DESC_1_USED 0x80000000
321#define DESC_1_LENGTH 0x00003FFF
322
323#define DESC_1_TX_WRAP 0x40000000
324#define DESC_1_TX_LAST 0x00008000
325
326#define DESC_0_RX_WRAP 0x00000002
327#define DESC_0_RX_OWNERSHIP 0x00000001
328
329#define R_DESC_1_RX_SAR_SHIFT 25
330#define R_DESC_1_RX_SAR_LENGTH 2
331#define R_DESC_1_RX_SAR_MATCH (1 << 27)
332#define R_DESC_1_RX_UNICAST_HASH (1 << 29)
333#define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
334#define R_DESC_1_RX_BROADCAST (1 << 31)
335
336#define DESC_1_RX_SOF 0x00004000
337#define DESC_1_RX_EOF 0x00008000
338
339#define GEM_REVISION_VALUE 0x00020118
340
341static inline unsigned tx_desc_get_used(unsigned *desc)
342{
343 return (desc[1] & DESC_1_USED) ? 1 : 0;
344}
345
346static inline void tx_desc_set_used(unsigned *desc)
347{
348 desc[1] |= DESC_1_USED;
349}
350
351static inline unsigned tx_desc_get_wrap(unsigned *desc)
352{
353 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
354}
355
356static inline unsigned tx_desc_get_last(unsigned *desc)
357{
358 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
359}
360
361static inline unsigned tx_desc_get_length(unsigned *desc)
362{
363 return desc[1] & DESC_1_LENGTH;
364}
365
366static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue)
367{
368 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
369 DB_PRINT("bufaddr: 0x%08x\n", *desc);
370 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
371 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc));
372 DB_PRINT("last: %d\n", tx_desc_get_last(desc));
373 DB_PRINT("length: %d\n", tx_desc_get_length(desc));
374}
375
376static inline unsigned rx_desc_get_wrap(unsigned *desc)
377{
378 return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
379}
380
381static inline unsigned rx_desc_get_ownership(unsigned *desc)
382{
383 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
384}
385
386static inline void rx_desc_set_ownership(unsigned *desc)
387{
388 desc[0] |= DESC_0_RX_OWNERSHIP;
389}
390
391static inline void rx_desc_set_sof(unsigned *desc)
392{
393 desc[1] |= DESC_1_RX_SOF;
394}
395
396static inline void rx_desc_set_eof(unsigned *desc)
397{
398 desc[1] |= DESC_1_RX_EOF;
399}
400
401static inline void rx_desc_set_length(unsigned *desc, unsigned len)
402{
403 desc[1] &= ~DESC_1_LENGTH;
404 desc[1] |= len;
405}
406
407static inline void rx_desc_set_broadcast(unsigned *desc)
408{
409 desc[1] |= R_DESC_1_RX_BROADCAST;
410}
411
412static inline void rx_desc_set_unicast_hash(unsigned *desc)
413{
414 desc[1] |= R_DESC_1_RX_UNICAST_HASH;
415}
416
417static inline void rx_desc_set_multicast_hash(unsigned *desc)
418{
419 desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
420}
421
422static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
423{
424 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
425 sar_idx);
426 desc[1] |= R_DESC_1_RX_SAR_MATCH;
427}
428
429#define GEM_MAX_PACKET_LEN (16 * 1024)
430#define GEM_MAX_DESC_LEN 4
431
432static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, unsigned *desc)
433{
434 uint64_t ret = desc[0];
435
436 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TX_BD_EXT) {
437 ret |= (uint64_t)desc[2] << 32;
438 }
439 return ret;
440}
441
442static inline uint64_t rx_desc_get_buffer(CadenceGEMState * s, unsigned *desc)
443{
444 uint64_t ret = desc[0] & ~0x3UL;
445
446 if (s->regs[GEM_DMACFG] & GEM_DMACFG_RX_BD_EXT) {
447 ret |= (uint64_t)desc[2] << 32;
448 }
449 return ret;
450}
451
452static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
453{
454 int ret = 2;
455
456 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_BUS_WIDTH_M) {
457 ret += 2;
458 }
459 if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
460 : GEM_DMACFG_TX_BD_EXT)) {
461 ret += 2;
462 }
463 return ret;
464}
465
466static inline void gem_set_isr_bit(CadenceGEMState *s, int q, uint32_t bit)
467{
468 s->regs[gem_sr(q, 0, GEM_ISR, 1, GEM_INT_Q1_STATUS)] |=
469 bit & ~(s->regs[gem_sr(q, 0, GEM_IMR, 1, GEM_INT_Q1_MASK,
470 8, GEM_INT_Q8_MASK)]);
471}
472
473
474static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
475
476
477
478
479
480
481static void gem_init_register_masks(CadenceGEMState *s)
482{
483 int i;
484
485 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
486 s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
487 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
488 s->regs_ro[GEM_DMACFG] = 0x8E00F000;
489 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
490 s->regs_ro[GEM_RXQBASE] = 0x00000003;
491 s->regs_ro[GEM_TXQBASE] = 0x00000003;
492 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
493 s->regs_ro[GEM_REVISION] = 0xFFFFFFFF;
494
495
496 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
497
498
499 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
500 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
501 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
502
503
504 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
505 s->regs_wo[GEM_NWCTRL] = 0x00073E60;
506
507
508 for (i = 0; i < MAX_PRIORITY_QUEUES; ++i) {
509 s->regs_rtc[gem_sr(i, 0, GEM_ISR, 1, GEM_INT_Q1_STATUS)] = 0xFFFFFFFF;
510 s->regs_ro[gem_sr(i, 0, GEM_ISR, 1, GEM_INT_Q1_STATUS)] = 0xFFFFFFFF;
511 s->regs_wo[gem_sr(i, 0, GEM_IER, 1, GEM_INT_Q1_ENABLE,
512 8, GEM_INT_Q8_ENABLE)] = 0x07FFFFFF;
513 s->regs_wo[gem_sr(i, 0, GEM_IDR, 1, GEM_INT_Q1_DISABLE,
514 8, GEM_INT_Q8_DISABLE)] = 0x07FFFFFF;
515 s->regs_ro[gem_sr(i, 0, GEM_IMR, 1, GEM_INT_Q1_MASK,
516 8, GEM_INT_Q8_MASK)] = 0x07FFFFFF;
517 }
518}
519
520
521
522
523
524static void phy_update_link(CadenceGEMState *s)
525{
526 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
527
528
529 if (!qemu_get_queue(s->nic)->link_down) {
530 s->regs[GEM_ISR] |= GEM_INT_AUTONEG & ~(s->regs[GEM_IMR]);
531 }
532 s->regs[GEM_ISR] |= GEM_INT_LINK_CHNG & ~(s->regs[GEM_IMR]);
533}
534
535static int gem_can_receive(NetClientState *nc)
536{
537 int i;
538 CadenceGEMState *s;
539
540 s = qemu_get_nic_opaque(nc);
541
542
543 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
544 if (s->can_rx_state != 1) {
545 s->can_rx_state = 1;
546 DB_PRINT("can't receive - no enable\n");
547 }
548 return 0;
549 }
550
551 for (i = 0; i < s->num_priority_queues &&
552 rx_desc_get_ownership(s->rx_desc[i]) == 1; ++i) {};
553 if (i == s->num_priority_queues) {
554 if (s->can_rx_state != 2) {
555 s->can_rx_state = 2;
556 for (i = 0; i < s->num_priority_queues; ++i) {
557 DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n",
558 i, s->rx_desc_addr[i]);
559 }
560 }
561 return 0;
562 }
563
564 if (s->can_rx_state != 0) {
565 s->can_rx_state = 0;
566 DB_PRINT("can receive\n");
567 }
568 return 1;
569}
570
571
572
573
574
575static void gem_update_int_status(CadenceGEMState *s)
576{
577 int i;
578
579 for (i = 0; i < s->num_priority_queues; ++i) {
580 uint32_t isr = s->regs[gem_sr(i, 0, GEM_ISR, 1, GEM_INT_Q1_STATUS)];
581 if (isr) {
582 DB_PRINT("asserting int. (q=%d, 0x%08x)\n", i, isr);
583 }
584 qemu_set_irq(s->irq[i], !!isr);
585 }
586}
587
588
589
590
591
592static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
593 unsigned bytes)
594{
595 uint64_t octets;
596
597
598 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
599 s->regs[GEM_OCTRXHI];
600 octets += bytes;
601 s->regs[GEM_OCTRXLO] = octets >> 32;
602 s->regs[GEM_OCTRXHI] = octets;
603
604
605 s->regs[GEM_RXCNT]++;
606
607
608 if (!memcmp(packet, broadcast_addr, 6)) {
609 s->regs[GEM_RXBROADCNT]++;
610 }
611
612
613 if (packet[0] == 0x01) {
614 s->regs[GEM_RXMULTICNT]++;
615 }
616
617 if (bytes <= 64) {
618 s->regs[GEM_RX64CNT]++;
619 } else if (bytes <= 127) {
620 s->regs[GEM_RX65CNT]++;
621 } else if (bytes <= 255) {
622 s->regs[GEM_RX128CNT]++;
623 } else if (bytes <= 511) {
624 s->regs[GEM_RX256CNT]++;
625 } else if (bytes <= 1023) {
626 s->regs[GEM_RX512CNT]++;
627 } else if (bytes <= 1518) {
628 s->regs[GEM_RX1024CNT]++;
629 } else {
630 s->regs[GEM_RX1519CNT]++;
631 }
632}
633
634
635
636
637static unsigned get_bit(const uint8_t *mac, unsigned bit)
638{
639 unsigned byte;
640
641 byte = mac[bit / 8];
642 byte >>= (bit & 0x7);
643 byte &= 1;
644
645 return byte;
646}
647
648
649
650
651static unsigned calc_mac_hash(const uint8_t *mac)
652{
653 int index_bit, mac_bit;
654 unsigned hash_index;
655
656 hash_index = 0;
657 mac_bit = 5;
658 for (index_bit = 5; index_bit >= 0; index_bit--) {
659 hash_index |= (get_bit(mac, mac_bit) ^
660 get_bit(mac, mac_bit + 6) ^
661 get_bit(mac, mac_bit + 12) ^
662 get_bit(mac, mac_bit + 18) ^
663 get_bit(mac, mac_bit + 24) ^
664 get_bit(mac, mac_bit + 30) ^
665 get_bit(mac, mac_bit + 36) ^
666 get_bit(mac, mac_bit + 42)) << index_bit;
667 mac_bit--;
668 }
669
670 return hash_index;
671}
672
673
674
675
676
677
678
679
680
681
682
683static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
684{
685 uint8_t *gem_spaddr;
686 int i;
687
688
689 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
690 return GEM_RX_PROMISCUOUS_ACCEPT;
691 }
692
693 if (!memcmp(packet, broadcast_addr, 6)) {
694
695 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
696 return GEM_RX_REJECT;
697 }
698 return GEM_RX_BROADCAST_ACCEPT;
699 }
700
701
702 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
703 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
704 unsigned hash_index;
705
706 hash_index = calc_mac_hash(packet);
707 if (hash_index < 32) {
708 if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
709 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
710 GEM_RX_UNICAST_HASH_ACCEPT;
711 }
712 } else {
713 hash_index -= 32;
714 if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
715 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
716 GEM_RX_UNICAST_HASH_ACCEPT;
717 }
718 }
719 }
720
721
722 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
723 for (i = 3; i >= 0; i--) {
724 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
725 return GEM_RX_SAR_ACCEPT + i;
726 }
727 }
728
729
730 return GEM_RX_REJECT;
731}
732
733static void gem_get_rx_desc(CadenceGEMState *s, int q)
734{
735 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
736
737 address_space_rw(s->dma_as, s->rx_desc_addr[q], *s->attr,
738 (uint8_t *)s->rx_desc[q],
739 sizeof(uint32_t) * gem_get_desc_len(s, true), false);
740
741
742 if (rx_desc_get_ownership(s->rx_desc[q]) == 1 &&
743 s->num_priority_queues == 1) {
744 DB_PRINT("descriptor 0x%x owned by sw.\n",
745 (unsigned)s->rx_desc_addr[q]);
746 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
747 gem_set_isr_bit(s, q, GEM_INT_RXUSED);
748
749 gem_update_int_status(s);
750 }
751}
752
753
754
755
756
757static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
758{
759 CadenceGEMState *s;
760 unsigned rxbufsize, bytes_to_copy;
761 unsigned rxbuf_offset;
762 uint8_t *rxbuf_ptr;
763 bool first_desc = true;
764 int maf;
765 int st1, st2;
766 int q = 0;
767
768 s = qemu_get_nic_opaque(nc);
769
770
771 maf = gem_mac_address_filter(s, buf);
772 if (maf == GEM_RX_REJECT) {
773 return -1;
774 }
775
776
777 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
778 unsigned type_len;
779
780
781 type_len = buf[12] << 8 | buf[13];
782
783 if (type_len < 0x600) {
784 if (size < type_len) {
785
786 return -1;
787 }
788 }
789 }
790
791
792
793
794 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
795 GEM_NWCFG_BUFF_OFST_S;
796
797
798
799
800 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
801 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
802 bytes_to_copy = size;
803
804
805
806
807
808 if (size < 60) {
809 size = 60;
810 }
811
812
813 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
814 rxbuf_ptr = (void *)buf;
815 } else {
816 unsigned crc_val;
817
818
819
820
821
822 rxbuf_ptr = s->packet;
823 memcpy(rxbuf_ptr, buf, size);
824 memset(rxbuf_ptr + size, 0, sizeof(s->packet) - size);
825 crc_val = cpu_to_le32(crc32(0, rxbuf_ptr, MAX(size, 60)));
826 memcpy(rxbuf_ptr + size, &crc_val, sizeof(crc_val));
827
828 bytes_to_copy += 4;
829 size += 4;
830 }
831
832 for (st1 = 0; st1 < s->num_type1_screeners; st1++) {
833 uint32_t reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + st1];
834 bool matched = false;
835 bool mismatched = false;
836
837 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
838 uint16_t udp_port = (uint16_t)rxbuf_ptr[14 + 20 + 2] << 8
839 | rxbuf_ptr[14 + 20 + 3];
840 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
841 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
842 matched = true;
843 } else {
844 mismatched = true;
845 }
846 }
847
848 if (reg & GEM_ST1R_DSTC_ENABLE) {
849 uint16_t dscp = rxbuf_ptr[14 + 1];
850 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
851 GEM_ST1R_DSTC_MATCH_WIDTH)) {
852 matched = true;
853 } else {
854 mismatched = false;
855 }
856 }
857
858 if (matched && !mismatched) {
859 q = extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
860 goto found_q;
861 }
862 }
863
864 for (st2 = 0; st2 < s->num_type2_screeners; st2++) {
865 uint32_t reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + st2];
866 bool matched = false;
867 bool mismatched = false;
868 int i;
869
870 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
871 uint16_t type = (uint16_t)rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
872 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
873 GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
874 if (et_idx > s->num_type2_screeners_ethtype) {
875 qemu_log_mask(LOG_GUEST_ERROR, "out of range ethertype "
876 "register index: %d\n", et_idx);
877 }
878 if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + et_idx]) {
879 matched = true;
880 } else {
881 mismatched = true;
882 }
883 }
884
885 for (i = 0; i < 3; i++) {
886 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (i * 6)))) {
887 continue;
888 }
889 uint32_t cr0, cr1;
890 int offset;
891 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + i * 6,
892 GEM_ST2R_COMPARE_WIDTH);
893
894 if (cr_idx > s->num_type2_screeners_compare) {
895 qemu_log_mask(LOG_GUEST_ERROR, "out of range compare "
896 "register index: %d\n", cr_idx);
897 }
898 cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
899 cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
900 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
901 GEM_T2CW1_OFFSET_VALUE_WIDTH);
902 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
903 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
904 case (3):
905 qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
906 "unimplemented - assuming UDP\n");
907 offset += 8;
908
909 case (2):
910 offset += 20;
911
912 case (1):
913 offset += 14;
914 }
915
916 uint16_t rx_cmp = rxbuf_ptr[offset] |
917 (uint16_t)rxbuf_ptr[offset] << 8;
918
919 uint16_t mask = extract32(cr0, 0, 16);
920 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
921 matched = true;
922 } else {
923 mismatched = true;
924 }
925 }
926 if (matched && !mismatched) {
927 q = extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
928 goto found_q;
929 }
930 }
931
932found_q:
933 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
934
935 while (bytes_to_copy) {
936
937 if (!gem_can_receive(nc)) {
938 qemu_log("%s:%d cannot receive? first_dest=%d\n",
939 __FILE__, __LINE__, first_desc);
940 break;
941 }
942
943 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
944 DB_PRINT("descriptor 0x%x owned by sw.\n",
945 (unsigned)s->rx_desc_addr[q]);
946 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
947 gem_set_isr_bit(s, q, GEM_INT_RXUSED);
948
949 gem_update_int_status(s);
950 return -1;
951 }
952
953 DB_PRINT("copy %d bytes to 0x%" PRIx64 "\n",
954 MIN(bytes_to_copy, rxbufsize),
955 rx_desc_get_buffer(s, s->rx_desc[q]));
956
957
958 address_space_rw(s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) +
959 rxbuf_offset, *s->attr,
960 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize), true);
961 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
962 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
963
964
965 if (first_desc) {
966 rx_desc_set_sof(s->rx_desc[q]);
967 first_desc = false;
968 }
969 if (bytes_to_copy == 0) {
970 rx_desc_set_eof(s->rx_desc[q]);
971 rx_desc_set_length(s->rx_desc[q], size);
972 }
973 rx_desc_set_ownership(s->rx_desc[q]);
974
975 switch (maf) {
976 case GEM_RX_PROMISCUOUS_ACCEPT:
977 break;
978 case GEM_RX_BROADCAST_ACCEPT:
979 rx_desc_set_broadcast(s->rx_desc[q]);
980 break;
981 case GEM_RX_UNICAST_HASH_ACCEPT:
982 rx_desc_set_unicast_hash(s->rx_desc[q]);
983 break;
984 case GEM_RX_MULTICAST_HASH_ACCEPT:
985 rx_desc_set_multicast_hash(s->rx_desc[q]);
986 break;
987 case GEM_RX_REJECT:
988 abort();
989 default:
990 rx_desc_set_sar(s->rx_desc[q], maf);
991 }
992
993
994 address_space_rw(s->dma_as, s->rx_desc_addr[q], *s->attr,
995 (uint8_t *)s->rx_desc[q],
996 sizeof(uint32_t) * gem_get_desc_len(s, true), true);
997
998
999 if (rx_desc_get_wrap(s->rx_desc[q])) {
1000 DB_PRINT("wrapping RX descriptor list\n");
1001 s->rx_desc_addr[q] = s->regs[gem_sr(q, 0, GEM_RXQBASE,
1002 1, GEM_RECEIVE_Q1_PTR)];
1003 } else {
1004 DB_PRINT("incrementing RX descriptor list\n");
1005 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
1006 }
1007
1008 gem_get_rx_desc(s, q);
1009 }
1010
1011
1012 gem_receive_updatestats(s, buf, size);
1013
1014 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
1015 gem_set_isr_bit(s, q, GEM_INT_RXCMPL);
1016
1017
1018 gem_update_int_status(s);
1019
1020 return size;
1021}
1022
1023
1024
1025
1026
1027static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
1028 unsigned bytes)
1029{
1030 uint64_t octets;
1031
1032
1033 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
1034 s->regs[GEM_OCTTXHI];
1035 octets += bytes;
1036 s->regs[GEM_OCTTXLO] = octets >> 32;
1037 s->regs[GEM_OCTTXHI] = octets;
1038
1039
1040 s->regs[GEM_TXCNT]++;
1041
1042
1043 if (!memcmp(packet, broadcast_addr, 6)) {
1044 s->regs[GEM_TXBCNT]++;
1045 }
1046
1047
1048 if (packet[0] == 0x01) {
1049 s->regs[GEM_TXMCNT]++;
1050 }
1051
1052 if (bytes <= 64) {
1053 s->regs[GEM_TX64CNT]++;
1054 } else if (bytes <= 127) {
1055 s->regs[GEM_TX65CNT]++;
1056 } else if (bytes <= 255) {
1057 s->regs[GEM_TX128CNT]++;
1058 } else if (bytes <= 511) {
1059 s->regs[GEM_TX256CNT]++;
1060 } else if (bytes <= 1023) {
1061 s->regs[GEM_TX512CNT]++;
1062 } else if (bytes <= 1518) {
1063 s->regs[GEM_TX1024CNT]++;
1064 } else {
1065 s->regs[GEM_TX1519CNT]++;
1066 }
1067}
1068
1069
1070
1071
1072
1073static void gem_transmit(CadenceGEMState *s)
1074{
1075 unsigned desc[GEM_MAX_DESC_LEN];
1076 hwaddr packet_desc_addr;
1077 uint8_t *p;
1078 unsigned total_bytes;
1079 int8_t q = s->num_priority_queues - 1;
1080 static bool first_run = true;
1081
1082
1083 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1084 return;
1085 }
1086
1087 DB_PRINT("\n");
1088
1089
1090
1091
1092
1093 p = s->packet;
1094 total_bytes = 0;
1095
1096 for (;;) {
1097 if (!s->tx_desc_addr[q] && !s->rx_desc_addr[q]) {
1098
1099
1100
1101 if (first_run) {
1102 qemu_log_mask(LOG_GUEST_ERROR, "Cadence Gem: The TX and RX "
1103 "address for channel %d are both set to zero. "
1104 "The transmission on this channel has been "
1105 "disabled.\n", q);
1106 }
1107 q--;
1108 continue;
1109 }
1110
1111
1112 packet_desc_addr = s->tx_desc_addr[q];
1113
1114 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1115 address_space_rw(s->dma_as, packet_desc_addr, *s->attr,
1116 (uint8_t *)desc,
1117 sizeof(uint32_t) * gem_get_desc_len(s, false),
1118 false);
1119
1120 while (tx_desc_get_used(desc) == 0) {
1121
1122
1123 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1124 return;
1125 }
1126 print_gem_tx_desc(desc, q);
1127
1128
1129
1130
1131 if ((tx_desc_get_buffer(s, desc) == 0) ||
1132 (tx_desc_get_length(desc) == 0) ||
1133 (tx_desc_get_length(desc) > GEM_MAX_PACKET_LEN)) {
1134 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
1135 (unsigned)packet_desc_addr);
1136 break;
1137 }
1138
1139
1140
1141
1142 address_space_rw(s->dma_as, tx_desc_get_buffer(s, desc), *s->attr,
1143 p, tx_desc_get_length(desc), false);
1144 p += tx_desc_get_length(desc);
1145 total_bytes += tx_desc_get_length(desc);
1146
1147
1148 if (tx_desc_get_last(desc)) {
1149 unsigned desc_first[2];
1150
1151
1152
1153
1154 address_space_rw(s->dma_as, s->tx_desc_addr[q], *s->attr,
1155 (uint8_t *)desc_first, sizeof(desc_first),
1156 false);
1157 tx_desc_set_used(desc_first);
1158 address_space_rw(s->dma_as, s->tx_desc_addr[q], *s->attr,
1159 (uint8_t *)desc_first, sizeof(desc_first),
1160 true);
1161
1162 if (tx_desc_get_wrap(desc)) {
1163 s->tx_desc_addr[q] = s->regs[gem_sr(q, 0, GEM_TXQBASE, 1,
1164 GEM_TRANSMIT_Q1_PTR)];
1165 } else {
1166 s->tx_desc_addr[q] = packet_desc_addr +
1167 4 * gem_get_desc_len(s, false);
1168 }
1169 DB_PRINT("TX descriptor next: 0x%" PRIx32 "\n",
1170 s->tx_desc_addr[q]);
1171
1172 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
1173 gem_set_isr_bit(s, q, GEM_INT_TXCMPL);
1174
1175
1176 gem_update_int_status(s);
1177
1178
1179 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
1180 net_checksum_calculate(s->packet, total_bytes);
1181 }
1182
1183
1184 gem_transmit_updatestats(s, s->packet, total_bytes);
1185
1186
1187 if (s->phy_loop || (s->regs[GEM_NWCTRL] &
1188 GEM_NWCTRL_LOCALLOOP)) {
1189 gem_receive(qemu_get_queue(s->nic), s->packet,
1190 total_bytes);
1191 } else {
1192 qemu_send_packet(qemu_get_queue(s->nic), s->packet,
1193 total_bytes);
1194 }
1195
1196
1197 p = s->packet;
1198 total_bytes = 0;
1199 }
1200
1201
1202 if (tx_desc_get_wrap(desc)) {
1203 packet_desc_addr = s->regs[gem_sr(q, 0, GEM_TXQBASE,
1204 1, GEM_TRANSMIT_Q1_PTR)];
1205 } else {
1206 packet_desc_addr += 4 * gem_get_desc_len(s, false);
1207 }
1208 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1209 address_space_rw(s->dma_as, packet_desc_addr, *s->attr,
1210 (uint8_t *)desc,
1211 sizeof(uint32_t) * gem_get_desc_len(s, false),
1212 false);
1213 }
1214
1215 if (tx_desc_get_used(desc) && !q) {
1216 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
1217 gem_set_isr_bit(s, q, GEM_INT_TXUSED);
1218 gem_update_int_status(s);
1219 }
1220
1221 if (q < 1) {
1222 first_run = false;
1223 break;
1224 }
1225 q--;
1226 }
1227}
1228
1229static void gem_reset(DeviceState *d)
1230{
1231 int i;
1232 uint32_t qmask;
1233 CadenceGEMState *s = CADENCE_GEM(d);
1234 const uint8_t *a;
1235
1236 DB_PRINT("\n");
1237
1238
1239 memset(&s->regs[0], 0, sizeof(s->regs));
1240 s->regs[GEM_NWCFG] = 0x00080000;
1241 s->regs[GEM_NWSTATUS] = 0x00000006;
1242 s->regs[GEM_DMACFG] = 0x00020784;
1243 s->regs[GEM_IMR] = 0x07ffffff;
1244 s->regs[GEM_TXPAUSE] = 0x0000ffff;
1245 s->regs[GEM_TXPARTIALSF] = 0x000003ff;
1246 s->regs[GEM_RXPARTIALSF] = 0x000003ff;
1247 s->regs[GEM_REVISION] = s->revision;
1248 s->regs[GEM_DESCONF] = 0x02500111;
1249 s->regs[GEM_DESCONF2] = 0x2ab13fff;
1250 s->regs[GEM_DESCONF5] = 0x002f2145;
1251 s->regs[GEM_DESCONF6] = 0x00000200;
1252
1253
1254 a = &s->conf.macaddr.a[0];
1255 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
1256 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
1257
1258
1259 assert(s->num_priority_queues <= 8);
1260 qmask = (1 << s->num_priority_queues) - 1;
1261
1262 qmask &= ~1;
1263 s->regs[GEM_DESCONF6] |= qmask;
1264
1265 for (i = 0; i < 4; i++) {
1266 s->sar_active[i] = false;
1267 }
1268
1269 phy_update_link(s);
1270 gem_update_int_status(s);
1271}
1272
1273static void gem_phy_loopback_setup(CadenceGEMState *s, unsigned reg_num,
1274 uint16_t val)
1275{
1276 switch (reg_num) {
1277 case PHY_REG_CONTROL:
1278 if (val & PHY_REG_CONTROL_RST) {
1279
1280 s->phy_loop = 0;
1281 }
1282 if (val & PHY_REG_CONTROL_LOOP) {
1283 DB_PRINT("PHY placed in loopback\n");
1284 s->phy_loop = 1;
1285 } else {
1286 s->phy_loop = 0;
1287 }
1288 break;
1289 }
1290}
1291
1292
1293
1294
1295
1296static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1297{
1298 CadenceGEMState *s;
1299 uint32_t retval;
1300
1301 s = (CadenceGEMState *)opaque;
1302
1303 offset >>= 2;
1304 retval = s->regs[offset];
1305
1306 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1307
1308 switch (offset) {
1309 case GEM_PHYMNTNC:
1310 if (retval & GEM_PHYMNTNC_OP_R) {
1311 uint32_t phy_addr, reg_num;
1312
1313 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1314 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1315 retval &= 0xFFFF0000;
1316 if (s->mdio) {
1317 retval |= s->mdio->read(s->mdio, phy_addr, reg_num);
1318 }
1319 }
1320 break;
1321 }
1322
1323
1324 s->regs[offset] &= ~(s->regs_rtc[offset]);
1325
1326
1327 retval &= ~(s->regs_wo[offset]);
1328
1329 DB_PRINT("0x%08x\n", retval);
1330 gem_update_int_status(s);
1331 return retval;
1332}
1333
1334
1335
1336
1337
1338static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1339 unsigned size)
1340{
1341 CadenceGEMState *s = (CadenceGEMState *)opaque;
1342 uint32_t readonly;
1343
1344 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1345 offset >>= 2;
1346
1347
1348 val &= ~(s->regs_ro[offset]);
1349
1350 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1351
1352
1353 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1354
1355
1356 s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1357
1358
1359 switch (offset) {
1360 case GEM_NWCTRL:
1361 if (val & GEM_NWCTRL_RXENA) {
1362 int i;
1363
1364 for (i = 0; i < s->num_priority_queues; ++i) {
1365 gem_get_rx_desc(s, i);
1366 }
1367 }
1368 if (val & GEM_NWCTRL_TXSTART) {
1369 gem_transmit(s);
1370 }
1371 if (!(val & GEM_NWCTRL_TXENA)) {
1372 int i;
1373
1374
1375 for (i = 0; i < s->num_priority_queues; i++) {
1376 s->tx_desc_addr[i] = s->regs[gem_sr(i, 0, GEM_TXQBASE,
1377 1, GEM_TRANSMIT_Q1_PTR)];
1378 }
1379 }
1380 if (gem_can_receive(qemu_get_queue(s->nic))) {
1381 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1382 }
1383 break;
1384
1385 case GEM_TXSTATUS:
1386 gem_update_int_status(s);
1387 break;
1388 case GEM_RXQBASE:
1389 s->rx_desc_addr[0] = val;
1390 break;
1391 case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q15_PTR:
1392 s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
1393 break;
1394 case GEM_TXQBASE:
1395 s->tx_desc_addr[0] = val;
1396 break;
1397 case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q15_PTR:
1398 s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
1399 break;
1400 case GEM_RXSTATUS:
1401 gem_update_int_status(s);
1402 break;
1403 case GEM_IER:
1404 s->regs[GEM_IMR] &= ~val;
1405 gem_update_int_status(s);
1406 break;
1407 case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
1408 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
1409 gem_update_int_status(s);
1410 break;
1411 case GEM_INT_Q8_ENABLE ... GEM_INT_Q15_ENABLE:
1412 s->regs[GEM_INT_Q8_MASK + offset - GEM_INT_Q8_ENABLE] &= ~val;
1413 gem_update_int_status(s);
1414 break;
1415 case GEM_IDR:
1416 s->regs[GEM_IMR] |= val;
1417 gem_update_int_status(s);
1418 break;
1419 case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
1420 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
1421 gem_update_int_status(s);
1422 break;
1423 case GEM_INT_Q8_DISABLE ... GEM_INT_Q15_DISABLE:
1424 s->regs[GEM_INT_Q8_MASK + offset - GEM_INT_Q8_DISABLE] |= val;
1425 gem_update_int_status(s);
1426 break;
1427 case GEM_SPADDR1LO:
1428 case GEM_SPADDR2LO:
1429 case GEM_SPADDR3LO:
1430 case GEM_SPADDR4LO:
1431 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1432 break;
1433 case GEM_SPADDR1HI:
1434 case GEM_SPADDR2HI:
1435 case GEM_SPADDR3HI:
1436 case GEM_SPADDR4HI:
1437 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1438 break;
1439 case GEM_PHYMNTNC:
1440 if (val & GEM_PHYMNTNC_OP_W) {
1441 uint32_t phy_addr, reg_num;
1442
1443 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1444 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1445 gem_phy_loopback_setup(s, reg_num, val);
1446 if (s->mdio) {
1447 s->mdio->write(s->mdio, phy_addr, reg_num, val);
1448 }
1449 }
1450 break;
1451 }
1452
1453 DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1454}
1455
1456static const MemoryRegionOps gem_ops = {
1457 .read = gem_read,
1458 .write = gem_write,
1459 .endianness = DEVICE_LITTLE_ENDIAN,
1460};
1461
1462static void gem_cleanup(NetClientState *nc)
1463{
1464 CadenceGEMState *s = qemu_get_nic_opaque(nc);
1465
1466 DB_PRINT("\n");
1467 s->nic = NULL;
1468}
1469
1470static void gem_set_link(NetClientState *nc)
1471{
1472 CadenceGEMState *s = qemu_get_nic_opaque(nc);
1473
1474 DB_PRINT("\n");
1475 phy_update_link(s);
1476 gem_update_int_status(s);
1477}
1478
1479static NetClientInfo net_gem_info = {
1480 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1481 .size = sizeof(NICState),
1482 .can_receive = gem_can_receive,
1483 .receive = gem_receive,
1484 .cleanup = gem_cleanup,
1485 .link_status_changed = gem_set_link,
1486};
1487
1488static void gem_realize(DeviceState *dev, Error **errp)
1489{
1490 CadenceGEMState *s = CADENCE_GEM(dev);
1491
1492 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1493
1494 s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1495 object_get_typename(OBJECT(dev)), dev->id, s);
1496 s->dma_as = s->dma_mr ? address_space_init_shareable(s->dma_mr, NULL)
1497 : &address_space_memory;
1498
1499 if (s->num_priority_queues == 0 ||
1500 s->num_priority_queues > MAX_PRIORITY_QUEUES) {
1501 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8,
1502 s->num_priority_queues);
1503 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) {
1504 error_setg(errp, "Invalid num-num-type1-screeners value: %" PRIx8,
1505 s->num_type1_screeners);
1506 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) {
1507 error_setg(errp, "Invalid num-num-type2-screeners value: %" PRIx8,
1508 s->num_type2_screeners);
1509 } else if (s->num_type2_screeners_ethtype > MAX_TYPE2_SCREENERS_ETHTYPE) {
1510 error_setg(errp, "Invalid num-num-type1-screeners-ethtype value: %"
1511 PRIx8, s->num_type2_screeners_ethtype);
1512 } else if (s->num_type2_screeners_compare > MAX_TYPE2_SCREENERS_COMPARE) {
1513 error_setg(errp, "Invalid num-num-type1-screeners-compare value: %"
1514 PRIx8, s->num_type2_screeners_compare);
1515 } else {
1516 int i;
1517 for (i = 0; i < s->num_priority_queues; ++i) {
1518 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1519 }
1520 }
1521
1522 if (!s->attr) {
1523 s->attr = MEMORY_TRANSACTION_ATTR(
1524 object_new(TYPE_MEMORY_TRANSACTION_ATTR));
1525 }
1526}
1527
1528static void gem_init(Object *obj)
1529{
1530 CadenceGEMState *s = CADENCE_GEM(obj);
1531
1532 gem_init_register_masks(s);
1533 memory_region_init_io(&s->iomem, obj, &gem_ops, s, "enet", sizeof(s->regs));
1534 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
1535
1536 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
1537 (Object **)&s->dma_mr,
1538 qdev_prop_allow_set_link_before_realize,
1539 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1540 &error_abort);
1541 object_property_add_link(obj, "memattr", TYPE_MEMORY_TRANSACTION_ATTR,
1542 (Object **)&s->attr,
1543 qdev_prop_allow_set_link_before_realize,
1544 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1545 &error_abort);
1546 object_property_add_link(obj, "mdio", TYPE_MDIO, (Object **)&s->mdio,
1547 qdev_prop_allow_set_link,
1548 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1549 &error_abort);
1550}
1551
1552static const VMStateDescription vmstate_cadence_gem = {
1553 .name = "cadence_gem",
1554 .version_id = 3,
1555 .minimum_version_id = 3,
1556 .fields = (VMStateField[]) {
1557 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1558 VMSTATE_UINT8(phy_loop, CadenceGEMState),
1559 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState,
1560 MAX_PRIORITY_QUEUES),
1561 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState,
1562 MAX_PRIORITY_QUEUES),
1563 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1564 VMSTATE_END_OF_LIST(),
1565 }
1566};
1567
1568static Property gem_properties[] = {
1569 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1570 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
1571 GEM_REVISION_VALUE),
1572 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
1573 num_priority_queues, 1),
1574 DEFINE_PROP_UINT8("num-type-1-screeners", CadenceGEMState,
1575 num_type1_screeners, 4),
1576 DEFINE_PROP_UINT8("num-type-2-screeners", CadenceGEMState,
1577 num_type2_screeners, 4),
1578 DEFINE_PROP_UINT8("num-type-2-screeners-ethtype", CadenceGEMState,
1579 num_type2_screeners_ethtype, 4),
1580 DEFINE_PROP_UINT8("num-type-2-screeners-compare", CadenceGEMState,
1581 num_type2_screeners_compare, 4),
1582 DEFINE_PROP_END_OF_LIST(),
1583};
1584
1585static void gem_class_init(ObjectClass *klass, void *data)
1586{
1587 DeviceClass *dc = DEVICE_CLASS(klass);
1588
1589 dc->realize = gem_realize;
1590 dc->props = gem_properties;
1591 dc->vmsd = &vmstate_cadence_gem;
1592 dc->reset = gem_reset;
1593}
1594
1595static const TypeInfo gem_info = {
1596 .name = TYPE_CADENCE_GEM,
1597 .parent = TYPE_SYS_BUS_DEVICE,
1598 .instance_size = sizeof(CadenceGEMState),
1599 .instance_init = gem_init,
1600 .class_init = gem_class_init,
1601};
1602
1603
1604static void gem_register_types(void)
1605{
1606 type_register_static(&gem_info);
1607}
1608
1609type_init(gem_register_types)
1610