1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 Linux NICS <linux.nics@intel.com> 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28/* e1000_hw.h 29 * Structures, enums, and macros for the MAC 30 */ 31 32#ifndef _E1000_HW_H_ 33#define _E1000_HW_H_ 34 35 36/* PCI Device IDs */ 37#define E1000_DEV_ID_82542 0x1000 38#define E1000_DEV_ID_82543GC_FIBER 0x1001 39#define E1000_DEV_ID_82543GC_COPPER 0x1004 40#define E1000_DEV_ID_82544EI_COPPER 0x1008 41#define E1000_DEV_ID_82544EI_FIBER 0x1009 42#define E1000_DEV_ID_82544GC_COPPER 0x100C 43#define E1000_DEV_ID_82544GC_LOM 0x100D 44#define E1000_DEV_ID_82540EM 0x100E 45#define E1000_DEV_ID_82540EM_LOM 0x1015 46#define E1000_DEV_ID_82540EP_LOM 0x1016 47#define E1000_DEV_ID_82540EP 0x1017 48#define E1000_DEV_ID_82540EP_LP 0x101E 49#define E1000_DEV_ID_82545EM_COPPER 0x100F 50#define E1000_DEV_ID_82545EM_FIBER 0x1011 51#define E1000_DEV_ID_82545GM_COPPER 0x1026 52#define E1000_DEV_ID_82545GM_FIBER 0x1027 53#define E1000_DEV_ID_82545GM_SERDES 0x1028 54#define E1000_DEV_ID_82546EB_COPPER 0x1010 55#define E1000_DEV_ID_82546EB_FIBER 0x1012 56#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 57#define E1000_DEV_ID_82541EI 0x1013 58#define E1000_DEV_ID_82541EI_MOBILE 0x1018 59#define E1000_DEV_ID_82541ER_LOM 0x1014 60#define E1000_DEV_ID_82541ER 0x1078 61#define E1000_DEV_ID_82547GI 0x1075 62#define E1000_DEV_ID_82541GI 0x1076 63#define E1000_DEV_ID_82541GI_MOBILE 0x1077 64#define E1000_DEV_ID_82541GI_LF 0x107C 65#define E1000_DEV_ID_82546GB_COPPER 0x1079 66#define E1000_DEV_ID_82546GB_FIBER 0x107A 67#define E1000_DEV_ID_82546GB_SERDES 0x107B 68#define E1000_DEV_ID_82546GB_PCIE 0x108A 69#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 70#define E1000_DEV_ID_82547EI 0x1019 71#define E1000_DEV_ID_82547EI_MOBILE 0x101A 72#define E1000_DEV_ID_82571EB_COPPER 0x105E 73#define E1000_DEV_ID_82571EB_FIBER 0x105F 74#define E1000_DEV_ID_82571EB_SERDES 0x1060 75#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 76#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 77#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 78#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC 79#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 80#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 81#define E1000_DEV_ID_82572EI_COPPER 0x107D 82#define E1000_DEV_ID_82572EI_FIBER 0x107E 83#define E1000_DEV_ID_82572EI_SERDES 0x107F 84#define E1000_DEV_ID_82572EI 0x10B9 85#define E1000_DEV_ID_82573E 0x108B 86#define E1000_DEV_ID_82573E_IAMT 0x108C 87#define E1000_DEV_ID_82573L 0x109A 88#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 89#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 90#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 91#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 92#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 93 94#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 95#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 96#define E1000_DEV_ID_ICH8_IGP_C 0x104B 97#define E1000_DEV_ID_ICH8_IFE 0x104C 98#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 99#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 100#define E1000_DEV_ID_ICH8_IGP_M 0x104D 101 102/* Device Specific Register Defaults */ 103#define E1000_PHY_ID2_82541x 0x380 104#define E1000_PHY_ID2_82544x 0xC30 105#define E1000_PHY_ID2_8254xx_DEFAULT 0xC20 /* 82540x, 82545x, and 82546x */ 106#define E1000_PHY_ID2_82573x 0xCC0 107 108/* Register Set. (82543, 82544) 109 * 110 * Registers are defined to be 32 bits and should be accessed as 32 bit values. 111 * These registers are physically located on the NIC, but are mapped into the 112 * host memory address space. 113 * 114 * RW - register is both readable and writable 115 * RO - register is read only 116 * WO - register is write only 117 * R/clr - register is read only and is cleared when read 118 * A - register array 119 */ 120#define E1000_CTRL 0x00000 /* Device Control - RW */ 121#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 122#define E1000_STATUS 0x00008 /* Device Status - RO */ 123#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 124#define E1000_EERD 0x00014 /* EEPROM Read - RW */ 125#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 126#define E1000_FLA 0x0001C /* Flash Access - RW */ 127#define E1000_MDIC 0x00020 /* MDI Control - RW */ 128#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 129#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ 130#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 131#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 132#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 133#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 134#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 135#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 136#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 137#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 138#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 139#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 140#define E1000_RCTL 0x00100 /* RX Control - RW */ 141#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ 142#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ 143#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ 144#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ 145#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ 146#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ 147#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 148#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 149#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 150#define E1000_TCTL 0x00400 /* TX Control - RW */ 151#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 152#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 153#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 154#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 155#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 156#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 157#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 158#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 159#define FEXTNVM_SW_CONFIG 0x0001 160#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 161#define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */ 162#define E1000_PBS 0x01008 /* Packet Buffer Size - RW */ 163#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 164#define E1000_FLASH_UPDATES 1000 165#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 166#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 167#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 168#define E1000_FLSWCTL 0x01030 /* FLASH control register */ 169#define E1000_FLSWDATA 0x01034 /* FLASH data register */ 170#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 171#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 172#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 173#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 174#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 175#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 176#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 177#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 178#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 179#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 180#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 181#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 182#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ 183#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ 184#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ 185#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 186#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 187#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 188#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ 189#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ 190#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 191#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 192#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 193#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 194#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 195#define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */ 196#define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */ 197#define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */ 198#define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */ 199#define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */ 200#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 201#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 202#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 203#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 204#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 205#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 206#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 207#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 208#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 209#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 210#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 211#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 212#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 213#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 214#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ 215#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ 216#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ 217#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ 218#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ 219#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ 220#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ 221#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ 222#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 223#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 224#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 225#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 226#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 227#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 228#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 229#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 230#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 231#define E1000_COLC 0x04028 /* Collision Count - R/clr */ 232#define E1000_DC 0x04030 /* Defer Count - R/clr */ 233#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 234#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 235#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 236#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 237#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 238#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 239#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 240#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 241#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 242#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 243#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 244#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 245#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 246#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 247#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 248#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 249#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 250#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 251#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 252#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 253#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 254#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 255#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 256#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 257#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 258#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 259#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 260#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 261#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 262#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 263#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 264#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 265#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 266#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 267#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 268#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 269#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 270#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 271#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 272#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 273#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 274#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 275#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 276#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 277#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 278#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 279#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 280#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 281#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ 282#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ 283#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ 284#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ 285#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 286#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ 287#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 288#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 289#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 290#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 291#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 292#define E1000_RA 0x05400 /* Receive Address - RW Array */ 293#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 294#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 295#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 296#define E1000_WUS 0x05810 /* Wakeup Status - RO */ 297#define E1000_MANC 0x05820 /* Management Control - RW */ 298#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 299#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 300#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 301#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 302#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 303#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 304#define E1000_HOST_IF 0x08800 /* Host Interface */ 305#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 306#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 307 308#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 309#define E1000_MDPHYA 0x0003C /* PHY address - RW */ 310#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 311#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 312 313#define E1000_GCR 0x05B00 /* PCI-Ex Control */ 314#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 315#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 316#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 317#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 318#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 319#define E1000_SWSM 0x05B50 /* SW Semaphore */ 320#define E1000_FWSM 0x05B54 /* FW Semaphore */ 321#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 322#define E1000_HICR 0x08F00 /* Host Inteface Control */ 323 324/* RSS registers */ 325#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 326#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 327#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ 328#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ 329#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ 330#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ 331 332/* PHY 1000 MII Register/Bit Definitions */ 333/* PHY Registers defined by IEEE */ 334#define PHY_CTRL 0x00 /* Control Register */ 335#define PHY_STATUS 0x01 /* Status Regiser */ 336#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 337#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 338#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 339#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 340#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 341#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 342#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 343#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 344#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 345#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 346 347#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 348#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ 349 350/* M88E1000 Specific Registers */ 351#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 352#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 353#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 354#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 355#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 356#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 357 358#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 359#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 360#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 361#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 362#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 363 364/* PHY Control Register */ 365#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 366#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 367#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 368#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 369#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 370#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 371#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 372#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 373#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 374#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 375 376/* PHY Status Register */ 377#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 378#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 379#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 380#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 381#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 382#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 383#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 384#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 385#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 386#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 387#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 388#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 389#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 390#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 391#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 392 393/* PHY Link Partner Ability Register */ 394#define MII_LPAR_LPACK 0x4000 /* Acked by link partner */ 395 396/* Interrupt Cause Read */ 397#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 398#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 399#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 400#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 401#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 402#define E1000_ICR_RXO 0x00000040 /* rx overrun */ 403#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 404#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 405#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 406#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 407#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 408#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 409#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 410#define E1000_ICR_TXD_LOW 0x00008000 411#define E1000_ICR_SRPD 0x00010000 412#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 413#define E1000_ICR_MNG 0x00040000 /* Manageability event */ 414#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 415#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 416#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 417#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 418#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 419#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 420#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 421#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 422#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 423#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 424#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 425#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ 426 427/* Interrupt Cause Set */ 428#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 429#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 430#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 431#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 432#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 433#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 434#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 435#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 436#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 437#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 438#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 439#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 440#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 441#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 442#define E1000_ICS_SRPD E1000_ICR_SRPD 443#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 444#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 445#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 446#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 447#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 448#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 449#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 450#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 451#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 452#define E1000_ICS_DSW E1000_ICR_DSW 453#define E1000_ICS_PHYINT E1000_ICR_PHYINT 454#define E1000_ICS_EPRST E1000_ICR_EPRST 455 456/* Interrupt Mask Set */ 457#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 458#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 459#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 460#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 461#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 462#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 463#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 464#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 465#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 466#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 467#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 468#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 469#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 470#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 471#define E1000_IMS_SRPD E1000_ICR_SRPD 472#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 473#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 474#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 475#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 476#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 477#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 478#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 479#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 480#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 481#define E1000_IMS_DSW E1000_ICR_DSW 482#define E1000_IMS_PHYINT E1000_ICR_PHYINT 483#define E1000_IMS_EPRST E1000_ICR_EPRST 484 485/* Interrupt Mask Clear */ 486#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 487#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 488#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 489#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 490#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 491#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 492#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 493#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 494#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 495#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 496#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 497#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 498#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 499#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 500#define E1000_IMC_SRPD E1000_ICR_SRPD 501#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ 502#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ 503#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ 504#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 505#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 506#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 507#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 508#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 509#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 510#define E1000_IMC_DSW E1000_ICR_DSW 511#define E1000_IMC_PHYINT E1000_ICR_PHYINT 512#define E1000_IMC_EPRST E1000_ICR_EPRST 513 514/* Receive Control */ 515#define E1000_RCTL_RST 0x00000001 /* Software reset */ 516#define E1000_RCTL_EN 0x00000002 /* enable */ 517#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 518#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 519#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 520#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 521#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 522#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 523#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 524#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 525#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 526#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 527#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 528#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 529#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 530#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 531#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 532#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 533#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 534#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 535#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 536#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 537/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 538#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 539#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 540#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 541#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 542/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 543#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 544#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 545#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 546#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 547#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 548#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 549#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 550#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 551#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 552#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 553#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 554#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 555 556 557#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 558#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 559#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ 560#define E1000_EEPROM_RW_REG_DONE 0x10 /* Offset to READ/WRITE done bit */ 561#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ 562#define E1000_EEPROM_RW_ADDR_SHIFT 8 /* Shift to the address bits */ 563#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ 564#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ 565/* Register Bit Masks */ 566/* Device Control */ 567#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 568#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 569#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 570#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 571#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 572#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 573#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 574#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 575#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 576#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 577#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 578#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 579#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 580#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 581#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 582#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 583#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 584#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 585#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 586#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 587#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ 588#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 589#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 590#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 591#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 592#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 593#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 594#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 595#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 596#define E1000_CTRL_RST 0x04000000 /* Global reset */ 597#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 598#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 599#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 600#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 601#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 602#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 603 604/* Device Status */ 605#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 606#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 607#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 608#define E1000_STATUS_FUNC_SHIFT 2 609#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 610#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 611#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 612#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 613#define E1000_STATUS_SPEED_MASK 0x000000C0 614#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 615#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 616#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 617#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion 618 by EEPROM/Flash */ 619#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 620#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 621#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 622#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 623#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 624#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 625#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 626#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 627#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 628#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 629#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 630#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 631#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ 632#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 633#define E1000_STATUS_FUSE_8 0x04000000 634#define E1000_STATUS_FUSE_9 0x08000000 635#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 636#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 637 638/* EEPROM/Flash Control */ 639#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 640#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 641#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 642#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 643#define E1000_EECD_FWE_MASK 0x00000030 644#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 645#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 646#define E1000_EECD_FWE_SHIFT 4 647#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 648#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 649#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 650#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 651#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 652 * (0-small, 1-large) */ 653#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 654#ifndef E1000_EEPROM_GRANT_ATTEMPTS 655#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 656#endif 657#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 658#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 659#define E1000_EECD_SIZE_EX_SHIFT 11 660#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 661#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 662#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 663#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 664#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 665#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 666#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 667#define E1000_EECD_SECVAL_SHIFT 22 668#define E1000_STM_OPCODE 0xDB00 669#define E1000_HICR_FW_RESET 0xC0 670 671#define E1000_SHADOW_RAM_WORDS 2048 672#define E1000_ICH_NVM_SIG_WORD 0x13 673#define E1000_ICH_NVM_SIG_MASK 0xC0 674 675/* MDI Control */ 676#define E1000_MDIC_DATA_MASK 0x0000FFFF 677#define E1000_MDIC_REG_MASK 0x001F0000 678#define E1000_MDIC_REG_SHIFT 16 679#define E1000_MDIC_PHY_MASK 0x03E00000 680#define E1000_MDIC_PHY_SHIFT 21 681#define E1000_MDIC_OP_WRITE 0x04000000 682#define E1000_MDIC_OP_READ 0x08000000 683#define E1000_MDIC_READY 0x10000000 684#define E1000_MDIC_INT_EN 0x20000000 685#define E1000_MDIC_ERROR 0x40000000 686 687/* EEPROM Commands - Microwire */ 688#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 689#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 690#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 691#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 692#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 693 694/* EEPROM Word Offsets */ 695#define EEPROM_COMPAT 0x0003 696#define EEPROM_ID_LED_SETTINGS 0x0004 697#define EEPROM_VERSION 0x0005 698#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 699#define EEPROM_PHY_CLASS_WORD 0x0007 700#define EEPROM_INIT_CONTROL1_REG 0x000A 701#define EEPROM_INIT_CONTROL2_REG 0x000F 702#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 703#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 704#define EEPROM_INIT_3GIO_3 0x001A 705#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 706#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 707#define EEPROM_CFG 0x0012 708#define EEPROM_FLASH_VERSION 0x0032 709#define EEPROM_CHECKSUM_REG 0x003F 710 711#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ 712#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ 713 714/* Transmit Descriptor */ 715struct e1000_tx_desc { 716 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 717 union { 718 uint32_t data; 719 struct { 720 uint16_t length; /* Data buffer length */ 721 uint8_t cso; /* Checksum offset */ 722 uint8_t cmd; /* Descriptor control */ 723 } flags; 724 } lower; 725 union { 726 uint32_t data; 727 struct { 728 uint8_t status; /* Descriptor status */ 729 uint8_t css; /* Checksum start */ 730 uint16_t special; 731 } fields; 732 } upper; 733}; 734 735/* Transmit Descriptor bit definitions */ 736#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 737#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 738#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 739#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 740#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 741#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 742#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 743#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 744#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 745#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 746#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 747#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 748#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 749#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 750#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 751#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 752#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 753#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 754#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 755#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 756 757/* Transmit Control */ 758#define E1000_TCTL_RST 0x00000001 /* software reset */ 759#define E1000_TCTL_EN 0x00000002 /* enable tx */ 760#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 761#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 762#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 763#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 764#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 765#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 766#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 767#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 768#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 769 770/* Receive Descriptor */ 771struct e1000_rx_desc { 772 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 773 uint16_t length; /* Length of data DMAed into data buffer */ 774 uint16_t csum; /* Packet checksum */ 775 uint8_t status; /* Descriptor status */ 776 uint8_t errors; /* Descriptor Errors */ 777 uint16_t special; 778}; 779 780/* Receive Descriptor bit definitions */ 781#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 782#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 783#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 784#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 785#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 786#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 787#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 788#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 789#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 790#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 791#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 792#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 793#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 794#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 795#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 796#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 797#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 798#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 799#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 800#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 801#define E1000_RXD_SPC_PRI_SHIFT 13 802#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 803#define E1000_RXD_SPC_CFI_SHIFT 12 804 805#define E1000_RXDEXT_STATERR_CE 0x01000000 806#define E1000_RXDEXT_STATERR_SE 0x02000000 807#define E1000_RXDEXT_STATERR_SEQ 0x04000000 808#define E1000_RXDEXT_STATERR_CXE 0x10000000 809#define E1000_RXDEXT_STATERR_TCPE 0x20000000 810#define E1000_RXDEXT_STATERR_IPE 0x40000000 811#define E1000_RXDEXT_STATERR_RXE 0x80000000 812 813#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 814#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 815 816/* Receive Address */ 817#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 818 819/* Offload Context Descriptor */ 820struct e1000_context_desc { 821 union { 822 uint32_t ip_config; 823 struct { 824 uint8_t ipcss; /* IP checksum start */ 825 uint8_t ipcso; /* IP checksum offset */ 826 uint16_t ipcse; /* IP checksum end */ 827 } ip_fields; 828 } lower_setup; 829 union { 830 uint32_t tcp_config; 831 struct { 832 uint8_t tucss; /* TCP checksum start */ 833 uint8_t tucso; /* TCP checksum offset */ 834 uint16_t tucse; /* TCP checksum end */ 835 } tcp_fields; 836 } upper_setup; 837 uint32_t cmd_and_length; /* */ 838 union { 839 uint32_t data; 840 struct { 841 uint8_t status; /* Descriptor status */ 842 uint8_t hdr_len; /* Header length */ 843 uint16_t mss; /* Maximum segment size */ 844 } fields; 845 } tcp_seg_setup; 846}; 847 848/* Offload data descriptor */ 849struct e1000_data_desc { 850 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 851 union { 852 uint32_t data; 853 struct { 854 uint16_t length; /* Data buffer length */ 855 uint8_t typ_len_ext; /* */ 856 uint8_t cmd; /* */ 857 } flags; 858 } lower; 859 union { 860 uint32_t data; 861 struct { 862 uint8_t status; /* Descriptor status */ 863 uint8_t popts; /* Packet Options */ 864 uint16_t special; /* */ 865 } fields; 866 } upper; 867}; 868 869/* Management Control */ 870#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 871#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 872#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 873#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 874#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 875#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 876#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 877#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 878#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 879#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 880 * Filtering */ 881#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 882#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 883#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 884#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 885#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 886#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 887#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 888 * filtering */ 889#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 890 * memory */ 891#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 892 * filtering */ 893#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 894#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 895#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 896#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 897#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 898#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 899#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 900#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 901 902#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 903#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 904 905/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 906#define EEPROM_SUM 0xBABA 907 908#endif /* _E1000_HW_H_ */ 909