1#ifndef HW_PCNET_H
2#define HW_PCNET_H 1
3
4#define PCNET_IOPORT_SIZE 0x20
5#define PCNET_PNPMMIO_SIZE 0x20
6
7#define PCNET_LOOPTEST_CRC 1
8#define PCNET_LOOPTEST_NOCRC 2
9
10#include "exec/memory.h"
11
12
13#define BCR_MSRDA 0
14#define BCR_MSWRA 1
15#define BCR_MC 2
16#define BCR_LNKST 4
17#define BCR_LED1 5
18#define BCR_LED2 6
19#define BCR_LED3 7
20#define BCR_FDC 9
21#define BCR_BSBC 18
22#define BCR_EECAS 19
23#define BCR_SWS 20
24#define BCR_PLAT 22
25
26#define BCR_TMAULOOP(S) !!((S)->bcr[BCR_MC ] & 0x4000)
27#define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100)
28#define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
29#define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
30#define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
31
32typedef struct PCNetState_st PCNetState;
33
34struct PCNetState_st {
35 NICState *nic;
36 NICConf conf;
37 QEMUTimer *poll_timer;
38 int rap, isr, lnkst;
39 uint32_t rdra, tdra;
40 uint8_t prom[16];
41 uint16_t csr[128];
42 uint16_t bcr[32];
43 int xmit_pos;
44 uint64_t timer;
45 MemoryRegion mmio;
46 uint8_t buffer[4096];
47 qemu_irq irq;
48 void (*phys_mem_read)(void *dma_opaque, hwaddr addr,
49 uint8_t *buf, int len, int do_bswap);
50 void (*phys_mem_write)(void *dma_opaque, hwaddr addr,
51 uint8_t *buf, int len, int do_bswap);
52 void *dma_opaque;
53 int tx_busy;
54 int looptest;
55};
56
57void pcnet_h_reset(void *opaque);
58void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val);
59uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr);
60void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val);
61uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr);
62uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
63ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_);
64void pcnet_set_link_status(NetClientState *nc);
65void pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info);
66extern const VMStateDescription vmstate_pcnet;
67#endif
68
