LXR qemu/hw/pci-bridge/xio3130

   1/*
   2 * xio3130_upstream.c
   3 * TI X3130 pci express upstream port switch
   4 *
   5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6 *                    VA Linux Systems Japan K.K.
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License along
  19 * with this program; if not, see <http://www.gnu.org/licenses/>.
  20 */
  21
  22#include "qemu/osdep.h"
  23#include "hw/pci/pci_ids.h"
  24#include "hw/pci/msi.h"
  25#include "hw/pci/pcie.h"
  26#include "xio3130_upstream.h"
  27
  28#define PCI_DEVICE_ID_TI_XIO3130U       0x8232  /* upstream port */
  29#define XIO3130_REVISION                0x2
  30#define XIO3130_MSI_OFFSET              0x70
  31#define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  32#define XIO3130_MSI_NR_VECTOR           1
  33#define XIO3130_SSVID_OFFSET            0x80
  34#define XIO3130_SSVID_SVID              0
  35#define XIO3130_SSVID_SSID              0
  36#define XIO3130_EXP_OFFSET              0x90
  37#define XIO3130_AER_OFFSET              0x100
  38
  39static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
  40                                          uint32_t val, int len)
  41{
  42    pci_bridge_write_config(d, address, val, len);
  43    pcie_cap_flr_write_config(d, address, val, len);
  44    pcie_aer_write_config(d, address, val, len);
  45}
  46
  47static void xio3130_upstream_reset(DeviceState *qdev)
  48{
  49    PCIDevice *d = PCI_DEVICE(qdev);
  50
  51    pci_bridge_reset(qdev);
  52    pcie_cap_deverr_reset(d);
  53}
  54
  55static int xio3130_upstream_initfn(PCIDevice *d)
  56{
  57    PCIEPort *p = PCIE_PORT(d);
  58    int rc;
  59
  60    pci_bridge_initfn(d, TYPE_PCIE_BUS);
  61    pcie_port_init_reg(d);
  62
  63    rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  64                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  65                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
  66    if (rc < 0) {
  67        goto err_bridge;
  68    }
  69    rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  70                               XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  71    if (rc < 0) {
  72        goto err_bridge;
  73    }
  74    rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
  75                       p->port);
  76    if (rc < 0) {
  77        goto err_msi;
  78    }
  79    pcie_cap_flr_init(d);
  80    pcie_cap_deverr_init(d);
  81    rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF);
  82    if (rc < 0) {
  83        goto err;
  84    }
  85
  86    return 0;
  87
  88err:
  89    pcie_cap_exit(d);
  90err_msi:
  91    msi_uninit(d);
  92err_bridge:
  93    pci_bridge_exitfn(d);
  94    return rc;
  95}
  96
  97static void xio3130_upstream_exitfn(PCIDevice *d)
  98{
  99    pcie_aer_exit(d);
 100    pcie_cap_exit(d);
 101    msi_uninit(d);
 102    pci_bridge_exitfn(d);
 103}
 104
 105PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
 106                             const char *bus_name, pci_map_irq_fn map_irq,
 107                             uint8_t port)
 108{
 109    PCIDevice *d;
 110    PCIBridge *br;
 111    DeviceState *qdev;
 112
 113    d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
 114    if (!d) {
 115        return NULL;
 116    }
 117    br = PCI_BRIDGE(d);
 118
 119    qdev = DEVICE(d);
 120    pci_bridge_map_irq(br, bus_name, map_irq);
 121    qdev_prop_set_uint8(qdev, "port", port);
 122    qdev_init_nofail(qdev);
 123
 124    return PCIE_PORT(d);
 125}
 126
 127static const VMStateDescription vmstate_xio3130_upstream = {
 128    .name = "xio3130-express-upstream-port",
 129    .version_id = 1,
 130    .minimum_version_id = 1,
 131    .fields = (VMStateField[]) {
 132        VMSTATE_PCIE_DEVICE(parent_obj.parent_obj, PCIEPort),
 133        VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0,
 134                       vmstate_pcie_aer_log, PCIEAERLog),
 135        VMSTATE_END_OF_LIST()
 136    }
 137};
 138
 139static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
 140{
 141    DeviceClass *dc = DEVICE_CLASS(klass);
 142    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 143
 144    k->is_express = 1;
 145    k->is_bridge = 1;
 146    k->config_write = xio3130_upstream_write_config;
 147    k->init = xio3130_upstream_initfn;
 148    k->exit = xio3130_upstream_exitfn;
 149    k->vendor_id = PCI_VENDOR_ID_TI;
 150    k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
 151    k->revision = XIO3130_REVISION;
 152    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 153    dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
 154    dc->reset = xio3130_upstream_reset;
 155    dc->vmsd = &vmstate_xio3130_upstream;
 156}
 157
 158static const TypeInfo xio3130_upstream_info = {
 159    .name          = "x3130-upstream",
 160    .parent        = TYPE_PCIE_PORT,
 161    .class_init    = xio3130_upstream_class_init,
 162};
 163
 164static void xio3130_upstream_register_types(void)
 165{
 166    type_register_static(&xio3130_upstream_info);
 167}
 168
 169type_init(xio3130_upstream_register_types)
 170
 171
 172/*
 173 * Local variables:
 174 *  c-indent-level: 4
 175 *  c-basic-offset: 4
 176 *  tab-width: 8
 177 *  indent-tab-mode: nil
 178 * End:
 179 */
 180