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21#include "qemu/osdep.h"
22#include "hw/pci/msi.h"
23#include "hw/xen/xen.h"
24#include "qemu/range.h"
25
26
27#define PCI_MSI_ADDRESS_LO_MASK (~0x3)
28
29
30#define PCI_MSI_32_SIZEOF 0x0a
31#define PCI_MSI_64_SIZEOF 0x0e
32#define PCI_MSI_32M_SIZEOF 0x14
33#define PCI_MSI_64M_SIZEOF 0x18
34
35#define PCI_MSI_VECTORS_MAX 32
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51bool msi_nonbroken;
52
53
54static inline uint8_t msi_cap_sizeof(uint16_t flags)
55{
56 switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
57 case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
58 return PCI_MSI_64M_SIZEOF;
59 case PCI_MSI_FLAGS_64BIT:
60 return PCI_MSI_64_SIZEOF;
61 case PCI_MSI_FLAGS_MASKBIT:
62 return PCI_MSI_32M_SIZEOF;
63 case 0:
64 return PCI_MSI_32_SIZEOF;
65 default:
66 abort();
67 break;
68 }
69 return 0;
70}
71
72
73
74#ifdef MSI_DEBUG
75# define MSI_DPRINTF(fmt, ...) \
76 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
77#else
78# define MSI_DPRINTF(fmt, ...) do { } while (0)
79#endif
80#define MSI_DEV_PRINTF(dev, fmt, ...) \
81 MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
82
83static inline unsigned int msi_nr_vectors(uint16_t flags)
84{
85 return 1U <<
86 ((flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE));
87}
88
89static inline uint8_t msi_flags_off(const PCIDevice* dev)
90{
91 return dev->msi_cap + PCI_MSI_FLAGS;
92}
93
94static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
95{
96 return dev->msi_cap + PCI_MSI_ADDRESS_LO;
97}
98
99static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
100{
101 return dev->msi_cap + PCI_MSI_ADDRESS_HI;
102}
103
104static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
105{
106 return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
107}
108
109static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
110{
111 return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
112}
113
114static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
115{
116 return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
117}
118
119
120
121
122
123void msi_set_message(PCIDevice *dev, MSIMessage msg)
124{
125 uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
126 bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
127
128 if (msi64bit) {
129 pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address);
130 } else {
131 pci_set_long(dev->config + msi_address_lo_off(dev), msg.address);
132 }
133 pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data);
134}
135
136MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector)
137{
138 uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
139 bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
140 unsigned int nr_vectors = msi_nr_vectors(flags);
141 MSIMessage msg;
142
143 assert(vector < nr_vectors);
144
145 if (msi64bit) {
146 msg.address = pci_get_quad(dev->config + msi_address_lo_off(dev));
147 } else {
148 msg.address = pci_get_long(dev->config + msi_address_lo_off(dev));
149 }
150
151
152 msg.data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
153 if (nr_vectors > 1) {
154 msg.data &= ~(nr_vectors - 1);
155 msg.data |= vector;
156 }
157
158 return msg;
159}
160
161bool msi_enabled(const PCIDevice *dev)
162{
163 return msi_present(dev) &&
164 (pci_get_word(dev->config + msi_flags_off(dev)) &
165 PCI_MSI_FLAGS_ENABLE);
166}
167
168int msi_init(struct PCIDevice *dev, uint8_t offset,
169 unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask)
170{
171 unsigned int vectors_order;
172 uint16_t flags;
173 uint8_t cap_size;
174 int config_offset;
175
176 if (!msi_nonbroken) {
177 return -ENOTSUP;
178 }
179
180 MSI_DEV_PRINTF(dev,
181 "init offset: 0x%"PRIx8" vector: %"PRId8
182 " 64bit %d mask %d\n",
183 offset, nr_vectors, msi64bit, msi_per_vector_mask);
184
185 assert(!(nr_vectors & (nr_vectors - 1)));
186 assert(nr_vectors > 0);
187 assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
188
189 vectors_order = ctz32(nr_vectors);
190
191 flags = vectors_order << ctz32(PCI_MSI_FLAGS_QMASK);
192 if (msi64bit) {
193 flags |= PCI_MSI_FLAGS_64BIT;
194 }
195 if (msi_per_vector_mask) {
196 flags |= PCI_MSI_FLAGS_MASKBIT;
197 }
198
199 cap_size = msi_cap_sizeof(flags);
200 config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size);
201 if (config_offset < 0) {
202 return config_offset;
203 }
204
205 dev->msi_cap = config_offset;
206 dev->cap_present |= QEMU_PCI_CAP_MSI;
207
208 pci_set_word(dev->config + msi_flags_off(dev), flags);
209 pci_set_word(dev->wmask + msi_flags_off(dev),
210 PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
211 pci_set_long(dev->wmask + msi_address_lo_off(dev),
212 PCI_MSI_ADDRESS_LO_MASK);
213 if (msi64bit) {
214 pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
215 }
216 pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
217
218 if (msi_per_vector_mask) {
219
220 pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
221 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
222 }
223 return config_offset;
224}
225
226void msi_uninit(struct PCIDevice *dev)
227{
228 uint16_t flags;
229 uint8_t cap_size;
230
231 if (!msi_present(dev)) {
232 return;
233 }
234 flags = pci_get_word(dev->config + msi_flags_off(dev));
235 cap_size = msi_cap_sizeof(flags);
236 pci_del_capability(dev, PCI_CAP_ID_MSI, cap_size);
237 dev->cap_present &= ~QEMU_PCI_CAP_MSI;
238
239 MSI_DEV_PRINTF(dev, "uninit\n");
240}
241
242void msi_reset(PCIDevice *dev)
243{
244 uint16_t flags;
245 bool msi64bit;
246
247 if (!msi_present(dev)) {
248 return;
249 }
250
251 flags = pci_get_word(dev->config + msi_flags_off(dev));
252 flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
253 msi64bit = flags & PCI_MSI_FLAGS_64BIT;
254
255 pci_set_word(dev->config + msi_flags_off(dev), flags);
256 pci_set_long(dev->config + msi_address_lo_off(dev), 0);
257 if (msi64bit) {
258 pci_set_long(dev->config + msi_address_hi_off(dev), 0);
259 }
260 pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
261 if (flags & PCI_MSI_FLAGS_MASKBIT) {
262 pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
263 pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
264 }
265 MSI_DEV_PRINTF(dev, "reset\n");
266}
267
268static bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
269{
270 uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
271 uint32_t mask, data;
272 bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
273 assert(vector < PCI_MSI_VECTORS_MAX);
274
275 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
276 return false;
277 }
278
279 data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
280 if (xen_is_pirq_msi(data)) {
281 return false;
282 }
283
284 mask = pci_get_long(dev->config +
285 msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
286 return mask & (1U << vector);
287}
288
289void msi_notify(PCIDevice *dev, unsigned int vector)
290{
291 uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
292 bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
293 unsigned int nr_vectors = msi_nr_vectors(flags);
294 MSIMessage msg;
295
296 assert(vector < nr_vectors);
297 if (msi_is_masked(dev, vector)) {
298 assert(flags & PCI_MSI_FLAGS_MASKBIT);
299 pci_long_test_and_set_mask(
300 dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
301 MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
302 return;
303 }
304
305 msg = msi_get_message(dev, vector);
306
307 MSI_DEV_PRINTF(dev,
308 "notify vector 0x%x"
309 " address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
310 vector, msg.address, msg.data);
311 msi_send_message(dev, msg);
312}
313
314void msi_send_message(PCIDevice *dev, MSIMessage msg)
315{
316 MemTxAttrs attrs = {};
317
318 attrs.requester_id = pci_requester_id(dev);
319 address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,
320 attrs, NULL);
321}
322
323
324void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
325{
326 uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
327 bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
328 bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
329 unsigned int nr_vectors;
330 uint8_t log_num_vecs;
331 uint8_t log_max_vecs;
332 unsigned int vector;
333 uint32_t pending;
334
335 if (!msi_present(dev) ||
336 !ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
337 return;
338 }
339
340#ifdef MSI_DEBUG
341 MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
342 addr, val, len);
343 MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
344 flags,
345 pci_get_long(dev->config + msi_address_lo_off(dev)));
346 if (msi64bit) {
347 fprintf(stderr, " address-hi: 0x%"PRIx32,
348 pci_get_long(dev->config + msi_address_hi_off(dev)));
349 }
350 fprintf(stderr, " data: 0x%"PRIx16,
351 pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
352 if (flags & PCI_MSI_FLAGS_MASKBIT) {
353 fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
354 pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
355 pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
356 }
357 fprintf(stderr, "\n");
358#endif
359
360 if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
361 return;
362 }
363
364
365
366
367
368
369
370
371
372
373
374
375 pci_device_deassert_intx(dev);
376
377
378
379
380
381
382 log_num_vecs =
383 (flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE);
384 log_max_vecs =
385 (flags & PCI_MSI_FLAGS_QMASK) >> ctz32(PCI_MSI_FLAGS_QMASK);
386 if (log_num_vecs > log_max_vecs) {
387 flags &= ~PCI_MSI_FLAGS_QSIZE;
388 flags |= log_max_vecs << ctz32(PCI_MSI_FLAGS_QSIZE);
389 pci_set_word(dev->config + msi_flags_off(dev), flags);
390 }
391
392 if (!msi_per_vector_mask) {
393
394
395 return;
396 }
397
398 nr_vectors = msi_nr_vectors(flags);
399
400
401 pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
402 pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
403 pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
404
405
406 for (vector = 0; vector < nr_vectors; ++vector) {
407 if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
408 continue;
409 }
410
411 pci_long_test_and_clear_mask(
412 dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
413 msi_notify(dev, vector);
414 }
415}
416
417unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
418{
419 uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
420 return msi_nr_vectors(flags);
421}
422