LXR qemu/hw/ppc/mac.h

   1/*
   2 * QEMU PowerMac emulation shared definitions and prototypes
   3 *
   4 * Copyright (c) 2004-2007 Fabrice Bellard
   5 * Copyright (c) 2007 Jocelyn Mayer
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25#if !defined(__PPC_MAC_H__)
  26#define __PPC_MAC_H__
  27
  28#include "exec/memory.h"
  29#include "hw/sysbus.h"
  30#include "hw/ide/internal.h"
  31#include "hw/input/adb.h"
  32
  33/* SMP is not enabled, for now */
  34#define MAX_CPUS 1
  35
  36#define BIOS_SIZE     (1024 * 1024)
  37#define NVRAM_SIZE        0x2000
  38#define PROM_FILENAME    "openbios-ppc"
  39#define PROM_ADDR         0xfff00000
  40
  41#define KERNEL_LOAD_ADDR 0x01000000
  42#define KERNEL_GAP       0x00100000
  43
  44#define ESCC_CLOCK 3686400
  45
  46/* Cuda */
  47#define TYPE_CUDA "cuda"
  48#define CUDA(obj) OBJECT_CHECK(CUDAState, (obj), TYPE_CUDA)
  49
  50/**
  51 * CUDATimer:
  52 * @counter_value: counter value at load time
  53 */
  54typedef struct CUDATimer {
  55    int index;
  56    uint16_t latch;
  57    uint16_t counter_value;
  58    int64_t load_time;
  59    int64_t next_irq_time;
  60    uint64_t frequency;
  61    QEMUTimer *timer;
  62} CUDATimer;
  63
  64/**
  65 * CUDAState:
  66 * @b: B-side data
  67 * @a: A-side data
  68 * @dirb: B-side direction (1=output)
  69 * @dira: A-side direction (1=output)
  70 * @sr: Shift register
  71 * @acr: Auxiliary control register
  72 * @pcr: Peripheral control register
  73 * @ifr: Interrupt flag register
  74 * @ier: Interrupt enable register
  75 * @anh: A-side data, no handshake
  76 * @last_b: last value of B register
  77 * @last_acr: last value of ACR register
  78 */
  79typedef struct CUDAState {
  80    /*< private >*/
  81    SysBusDevice parent_obj;
  82    /*< public >*/
  83
  84    MemoryRegion mem;
  85    /* cuda registers */
  86    uint8_t b;
  87    uint8_t a;
  88    uint8_t dirb;
  89    uint8_t dira;
  90    uint8_t sr;
  91    uint8_t acr;
  92    uint8_t pcr;
  93    uint8_t ifr;
  94    uint8_t ier;
  95    uint8_t anh;
  96
  97    ADBBusState adb_bus;
  98    CUDATimer timers[2];
  99
 100    uint32_t tick_offset;
 101    uint64_t frequency;
 102
 103    uint8_t last_b;
 104    uint8_t last_acr;
 105
 106    /* MacOS 9 is racy and requires a delay upon setting the SR_INT bit */
 107    QEMUTimer *sr_delay_timer;
 108
 109    int data_in_size;
 110    int data_in_index;
 111    int data_out_index;
 112
 113    qemu_irq irq;
 114    uint16_t adb_poll_mask;
 115    uint8_t autopoll_rate_ms;
 116    uint8_t autopoll;
 117    uint8_t data_in[128];
 118    uint8_t data_out[16];
 119    QEMUTimer *adb_poll_timer;
 120} CUDAState;
 121
 122/* MacIO */
 123#define TYPE_OLDWORLD_MACIO "macio-oldworld"
 124#define TYPE_NEWWORLD_MACIO "macio-newworld"
 125
 126#define TYPE_MACIO_IDE "macio-ide"
 127#define MACIO_IDE(obj) OBJECT_CHECK(MACIOIDEState, (obj), TYPE_MACIO_IDE)
 128
 129typedef struct MACIOIDEState {
 130    /*< private >*/
 131    SysBusDevice parent_obj;
 132    /*< public >*/
 133
 134    qemu_irq irq;
 135    qemu_irq dma_irq;
 136
 137    MemoryRegion mem;
 138    IDEBus bus;
 139    IDEDMA dma;
 140    void *dbdma;
 141    bool dma_active;
 142} MACIOIDEState;
 143
 144void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table);
 145void macio_ide_register_dma(MACIOIDEState *ide, void *dbdma, int channel);
 146
 147void macio_init(PCIDevice *dev,
 148                MemoryRegion *pic_mem,
 149                MemoryRegion *escc_mem);
 150
 151/* Heathrow PIC */
 152qemu_irq *heathrow_pic_init(MemoryRegion **pmem,
 153                            int nb_cpus, qemu_irq **irqs);
 154
 155/* Grackle PCI */
 156#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
 157PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
 158                         MemoryRegion *address_space_mem,
 159                         MemoryRegion *address_space_io);
 160
 161/* UniNorth PCI */
 162PCIBus *pci_pmac_init(qemu_irq *pic,
 163                      MemoryRegion *address_space_mem,
 164                      MemoryRegion *address_space_io);
 165PCIBus *pci_pmac_u3_init(qemu_irq *pic,
 166                         MemoryRegion *address_space_mem,
 167                         MemoryRegion *address_space_io);
 168
 169/* Mac NVRAM */
 170#define TYPE_MACIO_NVRAM "macio-nvram"
 171#define MACIO_NVRAM(obj) \
 172    OBJECT_CHECK(MacIONVRAMState, (obj), TYPE_MACIO_NVRAM)
 173
 174typedef struct MacIONVRAMState {
 175    /*< private >*/
 176    SysBusDevice parent_obj;
 177    /*< public >*/
 178
 179    uint32_t size;
 180    uint32_t it_shift;
 181
 182    MemoryRegion mem;
 183    uint8_t *data;
 184} MacIONVRAMState;
 185
 186void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
 187#endif /* !defined(__PPC_MAC_H__) */
 188